JP3341458B2 - Power supply - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device for simultaneously reducing a ripple component generated on an input side and an output side.

[0002]

2. Description of the Related Art Generally, a DC input voltage is intermittently applied to a primary winding of a transformer by a switching operation of a switching element, and a voltage induced in a secondary winding is rectified and smoothed to obtain a predetermined DC output voltage. For example, in a forward-type switching power supply device, a filter circuit including a choke coil and a smoothing capacitor is provided on an input side and an output side of a transformer in order to remove a ripple component synchronized with a switching cycle accompanying an exciting current of the transformer. ing. On the other hand, in order to obtain a small and lightweight power supply device, simplification of a filter circuit and the like is indispensable. Conventionally, increasing the switching frequency has been known as an effective means for reducing the choke coil and the capacitor. Had been.

[0003]

In the above prior art, when the switching frequency of the power supply device is increased, the filter circuit can be simplified to some extent, but the switching loss and noise of the switching element gradually increase. There are drawbacks. In order to avoid such drawbacks, a switching element other than the main switching element is provided, and a clamp circuit for clamping the flyback voltage of the transformer is formed by the switching element and the capacitor. On the other hand, it is possible to use a partial resonance converter that discharges a parasitic capacitor existing in one switching element when the other switching element is turned on by alternately supplying a drive signal having an appropriate dead time from the control circuit. Conceivable. However, even when such a partial resonance converter is used, the ripple component is superimposed on the DC input voltage and DC output voltage lines with the switching of the main switching element. There was a problem that the capacitors could not be made smaller at the same time.

In view of the above problems, an object of the present invention is to provide a power supply device capable of simultaneously reducing the size of the input-side and output-side smoothing capacitors and simplifying the filter circuit.

[0005]

According to the present invention, there is provided a power supply apparatus comprising: a transformer for insulating a primary side and a secondary side; and a first for intermittently applying a common DC input voltage to a primary winding of the transformer.
A switching element, a clamp circuit having a second switching element for clamping a flyback voltage of the transformer, and a control circuit for alternately supplying a drive signal having a dead time to the first and second switching elements. Are connected to a common load, and the first partial resonance converter group of the one
The switching element has a duty of 0.44 or more.
An oscillator for supplying a drive signal in a range of 55 or less, and an inverter for inverting an output from the oscillator and supplying a drive signal to a first switching element of the other partial resonance converter group. is there. In this case, it is preferable that the plurality of partial resonance converters are connected in series to the load. In addition, it is preferable that a plurality of partial resonance type converters forming the one converter group and a plurality of partial resonance type converters forming the other converter group are provided with connection terminals which enable connection to the outside in each transformer. preferable. Further, the duty is preferably 0.5.

[0006]

According to the above arrangement, a driving signal having a predetermined duty is supplied from the oscillator to the first switching element forming one converter, and the oscillator is supplied to the first switching element forming the other converter. A drive signal having a predetermined duty, which is an output inverted from the drive signal, is supplied. Therefore, while the first switching element of one converter is ON, the first switching element of the other converter is ON.
Switching element is turned off, and the first
While the other switching element is off, the first switching element of the other converter is on. At this time,
Since the current flows into the input side of each converter substantially alternately, the ripple component generated in the input current of the power supply device is significantly smaller than the ripple component of the input current in the converter alone. Further, the ripple component of the current generated on the output side of each converter is suppressed to 10% or less of that when the forward converter is operated independently.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows the overall configuration of a single-transformer type switching power supply device according to the present embodiment. In FIG. Small-capacity smoothing capacitor, and the first switching element
, The DC input voltage Vi is intermittently applied to the primary winding 1A of the transformer 1. Reference numeral 4 denotes a clamp circuit that is connected between the primary windings 1A of the transformer 1 and clamps a flyback voltage of the transformer 1. The clamp circuit 4 includes a second MOS-type FET 5 as a second switching element, It is composed of a series circuit with the blocking capacitor 6. Between the drain and source of each of the FETs 3 and 5, although not shown, a unique parasitic capacitor and a body diode exist as characteristics of the FETs 3 and 5 themselves. And each F
The drive signals from the pulse width control circuit 7 as a control circuit are alternately applied to the gates of the ETs 3 and 5 with an appropriate dead time, that is, a time during which both the FETs 3 and 5 are turned off.

On the other hand, on the secondary side of the transformer 1, rectifier diodes 8, 9 as secondary rectifiers are connected to the dot side terminal and the non-dot side terminal of the secondary winding 1B, respectively. Reference numerals 10 and 12 denote a choke coil and a small-capacity smoothing capacitor constituting a smoothing circuit. And the F
The voltage induced in the secondary winding 1B of the transformer 1 due to the switching operation of the ET3 is rectified by the rectifier diodes 8 and 9, and is output via the choke coil 10 to the output terminal + Vou.
The DC output voltage Vo1 is supplied to t1 and -Vout1. Each of these elements constitutes a partial resonance converter 11 that suppresses switching loss of the FETs 3 and 5.

Reference numeral 31 denotes a resonance converter having the same configuration as the above-described resonance converter 11. On the primary winding 21A side of the transformer 21 constituting the resonance type converter 31, a series circuit of a first FET 23 as a first switching element, a second FET 25 as a second switching element and a blocking capacitor 26 is provided. A clamp circuit 24 and a pulse width control circuit 27 for alternately supplying a drive signal having an appropriate dead time to each of the FETs 23 and 25 are provided. On the secondary winding 21B side of the transformer 21, rectifier diodes 28 and 29 as secondary rectifiers, a choke coil 30 forming a smoothing circuit, and a small-capacity smoothing capacitor 32 are provided.
The output terminal + Vout2 through this choke coil 30
The DC output voltage Vo2 is supplied between -Vout2. The input terminals + Vin and -Vin are provided commonly to the converters 11 and 31, and the primary windings 1A and 21
A common DC input voltage Vi is intermittently applied to A by the switching operation of the first FETs 3 and 23. Also,
In this embodiment, the converters 11 and 31 are connected in series to a common load 41, and the output terminal of one converter 11 + Vout
1 and the output terminal -Vout2 of the other converter 31, a load 41 is connected, and the output terminal -Vout1 of one converter 11 and the output terminal + V of the other converter 31 are connected.
out2 is connected.

An oscillator 42 supplies a rectangular wave having a predetermined oscillation frequency to each of the converters 11 and 31. As shown in the waveform diagram of FIG.
The duty D, which is the ratio of the ON time within the range, is 0.
Set to 5. The output signal of the oscillator 42 is
It is supplied as it is as a drive signal for the first FET 3 via the pulse width control circuit 7 constituting one converter 11 as it is. Reference numeral 43 denotes an inverter inserted and connected between the pulse width control circuit 27 constituting the other converter 31 and the oscillator 42. The inverter 43 inverts the output waveform from the oscillator 42. That is, as shown in the waveform diagram of FIG.
Is output from the inverter 43 to the pulse width control circuit 27, and the pulse width control circuit 27 outputs the output waveform from the inverter 43. The output signal is supplied as it is as a drive signal for the first FET 23 constituting the other converter 31. The oscillator 42 and the inverter 43 drive the first FET 3 of the converter 11 which is one of the converter groups and the first FET 23 of the converter 31 which is the other converter group with a duty D, D ′ = 0.5. An oscillation circuit 44 for supplying signals with a phase difference of 180 ° is formed.

In this embodiment, two partial resonance converters 11, 31 are used. However, as shown in FIG. 5, two or more converters 11, 11a, 11b and converters 31, 31 are used.
a and 31b may be connected in series. In this case, the converter
11, 11a, 11b, 31, 31a, 31b are divided into two groups, the output signal from the oscillator 42 is supplied to the converters 11, 11a, 11b constituting one converter group, and the converter 31 constituting the other converter group. , 31a, 31b have inverters 43, 43a,
It is preferable to provide an output signal from 43b. Further, an output signal may be supplied from one inverter 43 to the other converter group.

As shown in FIG. 6, one converter group is composed of a plurality of converters 11 and 11a, and the other converter group is composed of a plurality of converters 31 and 31a. , 31, 31a transformers 1, 21
May be provided with connection terminals 51, 52, 53, 61, 62, 63 for enabling electrical connection with the outside. In this case, any of the connection terminals 51, 52, 53, 61, 62, 63
A desired output voltage and output current can be obtained by connecting a rectifying smoothing element and a load to the power supply.

Next, the operation and operation of the power supply device having the above configuration will be described in detail with reference to the waveform diagrams shown in FIGS. 2 and 3 show the duty D, D
2 shows the waveforms of the various parts of the converters 11 and 31 in the case of '= 0.5. The uppermost waveform is the output waveform of the oscillator 42, and the next waveform is the output waveform of the inverter 43. FIG. Of the current Ix1 flowing through the primary winding 1A,
21, the waveform of the current Ix2 flowing through the primary winding 21A, the waveform of the input current I1 of the converter 11, and the input current I of the converter 31.
2, the input current Ii obtained by integrating the converters 11 and 31
FIG. 3 shows a voltage VLD1 generated between the cathode of the diode 8 and the output terminal -Vout1.
Waveform, cathode of diode 9 and output terminal -Vout
Waveform of voltage VLD1 'generated between 1 and choke coil
2 shows a waveform of a voltage VL1 applied between the output terminal 10 and the output terminal -Vout1, and a waveform of a current IL1 flowing through the choke coil 10.

First, the operation of each of the converters 11 and 31 will be described. In the converter 11, the first FET 3 is turned on by a drive signal from the pulse width control circuit 7 and turned on.
When the off control is performed, the DC input voltage Vi between the input terminals + Vin and -Vin is intermittently applied to the primary winding 1A of the transformer 1. The second FE is controlled by the pulse width control circuit 7.
T5 is turned on and off alternately with the first FET 3, but each F5
Control is performed such that a predetermined dead time exists when the ETs 3 and 5 are switched on and off.

At this time, when the first FET 3 is turned off, a charge is accumulated in a parasitic capacitor existing in the first FET 3, so that the drain-source voltage of the first FET 3 rises slowly. Therefore, the intersection between the drain-source voltage and the current of the first FET 3 approaches zero. On the other hand, during a dead time period from when the first FET 3 is turned off to when the second FET 5 is turned on, the energy stored in the primary winding 1A of each transformer 1 is stored in the parasitic capacitor of the second FET 5. The discharged charge is discharged. Therefore, after that, the second FE
Even if T5 is turned on, the electric charge stored in the parasitic capacitor of the second FET 5 is discharged immediately before,
No large loss or noise is generated when the second FET 5 is turned on. When the first FET 3 is off,
A flyback voltage is generated in the primary winding 1A of each transformer 1, but when the second FET 5 is turned on, the flyback voltage generated in the primary winding 1A is charged to the low-impedance capacitor 6 to have a substantially constant value. Clamped.

Thereafter, when the second FET 5 is turned off, charges are accumulated in the parasitic capacitor existing in the second FET 5, and the drain-source voltage of the second FET 5 rises slowly. Therefore, the intersection between the drain-source voltage and the current of the second FET 5 also approaches zero.
On the other hand, after the second FET 5 is turned off, the first FE
During the dead time period until T3 turns on, the energy stored in the primary winding 1A causes the first FE
The electric charge stored in the parasitic capacitor of T3 is discharged. Therefore, even if the first FET 3 is turned on thereafter, the electric charge stored in the parasitic capacitor of the first FET 3 is discharged immediately before, so that a large loss and noise are generated when the first FET 3 is turned on. do not do. By repeating the switching operation of each of the FETs 3 and 5, zero-voltage switching with small switching loss is achieved even when the switching frequency is high. The same operation is performed for the FETs 23 and 25 of the other converter 31.

The pulse width control circuit 7 of the converter 11 includes:
An output signal having a duty D = 0.5 is supplied from the oscillator 42, and the pulse width control circuit 27 of the converter 31
Duty D '= 0.5 inverted from the output waveform from 42
Is supplied via an inverter 43. converter
While the first FET 3 on the 11 side is on, the DC input voltage Vi is applied to the primary winding 1A of the transformer 1, so that
As shown in FIG. 2, the current Ix1 flowing through the primary winding 1A rises with the exciting current, and the converter 11
Accordingly, the input current I1 to the input also rises with this. On the secondary side of the transformer 1, a positive voltage is induced on the dot side of the secondary winding 1 </ b> B, and one diode 8 is turned on, while the other diode 9 is turned off. At this time, as shown in FIG. 3, a rectangular voltage VL is applied between the cathode of the diode 8 and the output terminal -Vout1.
D1 occurs. On the other hand, when the first FET 3 is turned off,
This time, the input current I1 to the converter 11 is cut off, and the current Ix1 flowing through the primary winding 1A slightly falls near zero. Also, a positive voltage is induced on the non-dot side of the secondary winding 1B, and the other diode 9 conducts, while one diode 8 becomes non-conductive, and the cathode of the diode 9 and the output terminal A rectangular voltage VLD1 'is generated between -Vout1. The voltage VL1 applied between the choke coil 10 and the output terminal -Vout1 is the voltage VLD1 generated between the cathode of the diode 8 and the output terminal -Vout1, and the voltage VLD1 between the cathode of the diode 9 and the output terminal -Vout1.
The value is a value obtained by adding the voltage VLD1 ′ generated between Vout1 and the voltage VL especially when the duty D = 0.5.
D1 and VLD1 'have vertically symmetric waveforms, and the voltage VL1 has a ripple-free waveform equal to the output voltage Vo.

The first F of the converter 11 is controlled by the inverter 43.
While ET3 is on, the first FET of converter 31
23 is off, and conversely, while the first FET 3 is off,
Since the first FET 3 of the converter 31 is turned on, rectangular input currents I1 and I2 flow into the converters 11 and 31 alternately. Accordingly, as shown in FIG. 2, the input current Ii of the entire power supply device obtained by combining the input currents I1 and I2 of the converters 11 and 31 is, as shown in FIG.
Even if it is 0.5, it will not be a complete zero ripple, but its ripple value will be much smaller than when the converters 11 and 31 are operated independently, and the smoothing capacitor 2 on the input side
Can be significantly reduced in size. In the partial resonance converters 11 and 31 shown in FIG. 1, the ripple component can be made closer to zero by increasing the reactance on the primary side of the transformer 1. In this case, however, the function as the partial resonance is sufficiently satisfied. , It is desirable to set the reactance value of the primary side of the transformer 1. Also, the duty D
= 0.5, choke coil 10 and output terminal -Vou
The voltage VL1 applied during t1 becomes equal to the output voltage Vo1, and the current IL1 flowing through the choke coil 10 does not include any ripple component. Therefore, each converter 11,
Zero ripple is achieved on the secondary side of 31, and the output-side smoothing capacitors 12, 32 can be significantly reduced in size at the same time as the input-side smoothing capacitor 2. In this case, both FETs
Since drive signals having a dead time are given to the FETs 3 and 23 and the FETs 5 and 25, some ripple components are generated on the output side. However, when the oscillation frequency of the oscillator 42 is reduced, the dead time for one cycle T is reduced. To be smaller,
Accordingly, the capacity of each of the smoothing capacitors 12 and 32 can be reduced. If the duty D = 0.5, zero ripple can be achieved by the converters 11 and 31 alone without operating the converters 11 and 31 in series or in parallel.

FIG. 4 shows waveforms at various parts when the duty D of the output waveform from the oscillator 42 is not 0.5.
This will be described with reference to FIG. FIG. 4 shows that the duty D = 1.
/ 3, the duty of D '= 2/3 shows the waveform of each part of the converters 11 and 31.
The output waveform at the next stage is the output waveform of the inverter 43,
Hereinafter, the waveform of the voltage VL1 applied between the choke coil 10 and the output terminal -Vout1, the waveform of the current IL1 flowing through the choke coil 10, the choke coil 30 and the output terminal -Vout1
2 shows a waveform of a voltage VL2 applied between the two, and a waveform of a current IL2 flowing through the choke coil 30. For convenience of explanation, the turn ratio between the primary winding 1A of the transformer 1 and each of the secondary windings 1B divided by the center tap is 1: 1: 1.

In each of the converters 11 and 31, a first FET
Since the on-period and the off-period for 3, 23 are different, the waveforms of the voltage VL1 applied between the choke coil 10 and the output terminal -Vout1 and the voltage VL2 applied between the choke coil 30 and the output terminal -Vout2 are proportional to this. It fluctuates in shape. Also, the output voltage Vo of each converter 11, 31
1, Vo2 is proportional to the duty D, D '.
One converter 11 generates an output voltage of Vo1 = (2/3) × Vi, and the other converter 31 generates an output voltage of Vo2 = (4/3) × Vi, and
The output voltage Vo of Vo1 + Vo2 = 2 × Vi is supplied to 41 as in the case of the duty D and D ′ = 0.5. The current IL flowing through each of the choke coils 10 and 30
1, IL2 pulsates according to the fluctuations of the voltage VL1 and the voltage VL2. Current IL flowing through choke coils 10 and 30
1 and IL2 have the same phase, and each converter 1
Due to the difference between the duties D and D 'for 1 and 31,
The peak value difference between the ripple components of the current IL2 is twice the peak value difference between the ripple components of the current IL1. Therefore, as the duties D and D 'depart from 0.5,
The ripple current generated on the output side gradually increases, and the smoothing capacitors 12 and 32 for absorbing the ripple current become indispensable. However, if the duties D and D 'are within a certain range, the size of the smoothing capacitors 12 and 32 can be reduced.

In this embodiment, the converters 11, 31 are connected in series to the load 41.
Even when the load 31 is connected in parallel to the load 41, the same operation and effect can be obtained. However, when the converters 11 and 31 are operated in parallel, the output current IL from each of the converters 11 and 31 to the load 41 is
1, IL2 must be shared equally. This is because if the output currents IL1 and IL2 are not equally shared, the output current I
This is because the converters 11 and 31 with less L1 and IL2 stop oscillating. On the other hand, when the converters 11 and 31 are operated in series, it is not necessary to consider stopping the oscillation of each of the converters 11 and 31, and the output currents IL1 and IL2 are shared equally as in the case of parallel operation. Since no means is required, the ripple components on the input and output sides can be made close to zero with a simple configuration.

Next, the correlation between the duties D and D 'and the ripple components generated on the output side of the converters 11 and 31 will be described with reference to FIGS. 7 and 8 which are circuit diagrams of a forward converter and a partial resonance converter. It will be described based on the following. The turns ratio between the primary winding and the secondary winding of the transformer T in the forward converter shown in FIG. 7 is set to N: 1, and the primary winding of the transformer T 'in the partial resonance converter shown in FIG. The turns ratio between the wire and the secondary winding is N:
It is set to 1: 1. First, in the partial resonance converter of FIG. 8, the ripple current Δi flowing through the choke coil L
L is represented by the following equation.

[0023]

(Equation 1)

Here, VIN is the input voltage of the DC power source E, Vo
Is the output voltage, L is the inductance of the choke coil L,
T is the period of the drive signal supplied to the switching element Q1,
D is the duty of the drive signal.

In the partial resonance type converter, the following equation holds.

[0026]

(Equation 2)

Therefore, the following equation is obtained by substituting the equation shown in Equation 2 into Equation 1.

[0028]

(Equation 3)

When this is normalized, the following equation is obtained.

[0030]

(Equation 4)

That is, in the partial resonance converter, the ripple current ΔiL becomes zero when the duty D = 0.5.

On the other hand, in the forward converter of FIG. 7, the ripple current ΔiL flowing through the choke coil L is:
It is shown by the following equation.

[0033]

(Equation 5)

Here, VIN is the input voltage of the DC power supply E, Vo
Is the output voltage, L is the inductance of the choke coil L,
T is the period of the drive signal supplied to the switching element Q1,
D is the duty of the drive signal. That is, this has the same relationship as the partial resonance type converter shown in FIG.

In the forward converter, the following equation is established.

[0036]

(Equation 6)

Therefore, the following equation is obtained by substituting the equation shown in Equation 6 into Equation 5.

[0038]

(Equation 7)

When this is normalized, the following equation is obtained.

[0040]

(Equation 8)

Here, when the ratio R of the ripple current ΔiLI of the partial resonance type converter with respect to the forward type converter is calculated based on the mathematical expressions shown in Expressions 4 and 8, the following expression is obtained.

[0042]

(Equation 9)

FIG. 9 is a graph showing the relationship between the ratio R of the ripple current ΔiLI and the duty D.
That is, if the duty D is controlled in the range of 0.33 or more and 0.6 or less, the ripple current ΔiLI of the partial resonance type converter is changed to the ripple current Δi of the forward type converter.
It can be less than 1/4 of LI. Further, if the duty D is controlled in the range of 0.44 or more and 0.55 or less, the ripple current ΔiLI of the partial resonance type converter becomes 1/10 of the ripple current ΔiLI of the forward type converter.
The output ripple current ΔiLI can be made completely zero by setting the duty D to 0.5. Therefore, in FIG. 1, even if the output waveform of the oscillator 42 fluctuates somewhat, if the duty D is in the range of 0.44 or more and 0.55 or less,
The output-side ripple can be almost suppressed to 10% or less of the conventional forward converter, and the output-side smoothing capacitors 12 and 32 can be reduced in size.

As described above, according to the above-described embodiment, the transformer 1 that insulates the primary side from the secondary side corresponds to the first aspect.
1 and 21 and a first FE for intermittently applying a common DC input voltage Vi to the primary windings 1A and 21A of the transformers 11 and 21.
T3, 23, a clamp circuit 4, 24 having a second FET 5, 25 for clamping the flyback voltage of the transformers 11, 21, and the first and second FETs 3, 5, 23, 25
A plurality of partial resonance type converters 11 and 31 including pulse width control circuits 7 and 27 for alternately providing a drive signal having a dead time are connected to a common load 41, and the one partial resonance type converter 11 An oscillator 42 for supplying a drive signal having a duty D in a range of 0.44 or more and 0.55 or less to the first FETs 3 and 23, and an output of the other oscillator 42 by inverting the output from the oscillator 42; FET5 of 1
And an inverter 43 for supplying a drive signal to the inverter. In this case, the use of the partial resonance type converters 11 and 31 having a small switching loss even if the switching frequency is increased can reduce the size of the input side filter circuit and the like to some extent. Multiple loads 41
And a first FET constituting one converter 11
The duty D from the oscillator 42 is 0.44 or more and 0.5
By supplying a drive signal in a range of 5 or less and a drive signal obtained by inverting the output from the oscillator 42 to the first FET 23 constituting the other converter 31 from the inverter 43, the input side of the power supply device and The ripple component generated on the output side of each of the converters 11 and 31 can approach zero.
In particular, as shown in FIGS. 7 to 9, when the duty D is in the range of 0.44 or more and 0.55 or less, the output-side ripple can be suppressed to 10% or less of the conventional forward type converter. , Even if the duties D and D 'of the output waveforms from the oscillator 42 and the inverter 43 slightly fluctuate,
Each of the smoothing capacitors 2, 12, and 32 provided on the input side and the output side of each of the converters 11, 31 can be simultaneously miniaturized to simplify the filter circuit. Further, by making the ripple components of the input current Ii and the output current Io close to zero, noise from the power supply device can be reduced.

Further, in this embodiment, according to the second aspect,
Since the plurality of partial resonance type converters 11 and 31 are connected in series to the load 41, there is no need for a means for equally sharing the output currents IL1 and IL2 as in the case of the parallel operation, and a simple configuration allows the input side Also, the size of the smoothing capacitors 2, 12, 32 on the output side can be reduced at the same time, and the filter circuit can be simplified.

When the converters 11 and 31 are connected in series to the load 41, the output voltage Vo applied to both ends of the load 41 becomes
The output voltages Vo1 and Vo2 of the converters 11 and 31 are added, but the output voltages Vo1 and Vo2 of the converters 11 and 31 are added.
Since Vo2 is proportional to the duty ratios D and D 'of the drive signals for the FETs 3 and 23, the output voltage Vo is equal to D +
It will be proportional to D '. However, the output from the oscillator 42 as the drive signal of the FET 3 is inverted by the inverter 43,
The inverted output is used as a drive signal for the FET 23 as each FET.
By controlling 3, 23, D + D 'is always 1 even if the duty D of the output waveform from the oscillator 42 fluctuates, and the effect that the output voltage Vo can be kept stable can be obtained.

In particular, in FIG. 6 of this embodiment, a plurality of partial resonance converters 11 and 11a forming one converter group and a plurality of partial resonance converters forming the other converter group correspond to claim 3. Terminals 51, 52, 5 that enable external connection to the transformers 1, 21 of the type converters 31, 31a.
3, 61, 62 and 63 are provided, and in addition to the functions and effects of claim 1, optional connection terminals 51, 52, 53, 61,
A desired output voltage and output current can be obtained by connecting a rectifying smoothing element and a load to 62 and 63.

In the present embodiment, if the duties D and D '= 0.5, the currents IL1 and IL1 flowing through the choke coils 10 and 30 on the output side of the converters 11 and 31, respectively, correspond to claim 4. The ripple component of IL2 becomes zero, the size of the smoothing capacitors 12, 32 can be significantly reduced, and the choke coils 10, 30 become unnecessary. In this case, if a plurality of partial resonance type converters 11 and 31 are connected in series to the load 41 as in claim 2, the output current IL can be changed as in the case of parallel operation.
Means for evenly sharing 1 and IL2 are unnecessary, and the output-side smoothing capacitors 11 and 31 can be significantly reduced in size with a simple configuration.

The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the present invention. For example, in the embodiment, a one-transformer type converter is shown, but a two-transformer type partial resonance converter may be used.

[0050]

According to a first aspect of the present invention, there is provided a power supply apparatus comprising: a transformer for insulating a primary side from a secondary side; and a first switching element for intermittently applying a common DC input voltage to a primary winding of the transformer. A clamp circuit having a second switching element for clamping a flyback voltage of the transformer; and a control circuit for alternately supplying a drive signal having a dead time to the first and second switching elements. An oscillator that connects the partial resonance type converter to a common load, and supplies a drive signal having a duty of 0.44 or more and 0.55 or less to the first switching element of the one partial resonance type converter group; An inverter for inverting an output from an oscillator and supplying a drive signal to a first switching element of the other partial resonance type converter group. Ri, even somewhat change the duty of the output waveform from the oscillator, a is downsized simultaneously smoothing capacitor on the input side and the output side, it is possible to simplify the filter circuit.

Further, the power supply device according to the present invention is such that the plurality of partial resonance converters are connected in series to the load, and the input side and output side smoothing capacitors are simultaneously reduced in size with a simple configuration. Thus, the filter circuit can be simplified.

According to a third aspect of the present invention, there is provided the power supply device, wherein a plurality of partial resonance converters constituting the one converter group and a plurality of partial resonance converters constituting the other converter group are provided externally. A connection terminal is provided to enable connection of the filter circuit, and it is possible to obtain a desired output voltage and output current, to simultaneously reduce the size of the input side and output side smoothing capacitors and to simplify the filter circuit. It becomes possible to plan.

Further, the power supply device according to claim 4 is characterized in that the duty is 0.5, the output-side smoothing capacitor can be significantly reduced in size, and no choke coil is required. Becomes

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a power supply device showing one embodiment of the present invention.

FIG. 2 is a waveform diagram of each section when duties D and D 'are the same.

FIG. 3 is a waveform diagram of each unit when the duties D and D 'are the same.

FIG. 4 is a waveform diagram of each unit when the duties D and D 'are not equal.

FIG. 5 is a circuit configuration diagram of a power supply device showing another modification.

FIG. 6 is a circuit configuration diagram of a main part of a power supply device according to another modification.

FIG. 7 is a circuit configuration diagram of a forward converter for explaining a relationship between a duty and a ripple component according to the embodiment.

FIG. 8 is a circuit configuration diagram of a partial resonance converter illustrating a relationship between a duty and a ripple component.

FIG. 9 is a graph showing a relationship between a ratio of a ripple current and a duty;

[Description of Signs] 1,21 Transformer 3,23 First MOS-type FET (first switching element) 4,24 Clamp circuit 5,25 Second MOS-type FET (second switching element) 7,27 pulse Width control circuit (control circuit) 11, 11a, 11b, 31, 31a, 31b Partial resonance converter 41 Load 42 Oscillator 43 Inverter 51, 52, 53, 61, 62, 63 Connection terminal

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 3/28

Claims (4)

(57) [Claims] 1. A transformer for insulating a primary side and a secondary side from each other, a first switching element for intermittently applying a common DC input voltage to a primary winding of the transformer, and a flyback voltage of the transformer. A plurality of partial resonance type converters each comprising a clamp circuit having a second switching element to be clamped and a control circuit for alternately providing a drive signal having a dead time to the first and second switching elements are connected to a common load. And an oscillator for supplying a drive signal having a duty in a range of 0.44 or more and 0.55 or less to a first switching element of the one partial resonance type converter group, and inverting an output from the oscillator to supply the drive signal. An inverter for supplying a drive signal to the first switching element of the other partial resonance type converter group. 2. The power supply device according to claim 1, wherein said plurality of partial resonance converters are connected in series to said load. 3. A connection terminal for enabling external connection to each of the plurality of partial resonance type converters forming the one converter group and the plurality of partial resonance type converters forming the other converter group. The power supply device according to claim 1, wherein the power supply device is provided. 4. The power supply device according to claim 1, wherein said duty is 0.5.