JP3336977B2 - High frequency circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-frequency circuit for handling a high-frequency signal. In particular, it relates to a high-frequency circuit that needs to reduce capacitive coupling between a high-frequency line and a semiconductor element. For example, it can be applied to a high-frequency switch element, a high-frequency detector, and the like.

[0002]

2. Description of the Related Art Conventionally, there has been known a so-called planar line in which a signal line and a ground line are formed on the same plane by using a semiconductor integration technique, and a semiconductor element is connected between the signal line and the ground line. I have.

For example, a one-input three-switch output high-frequency switch MMIC using a PIN diode as a semiconductor element
Michael on IEEE MTT-S digest, 1997
l A paper by Case et al., “High-Performance W ⁰¹ and GaAs
PIN Diode Single-Pole Triple-Throw Switch CPW MMI
C "is an example.

According to the document, the cross-sectional shape of the PIN diode used has the basic structure shown in FIG. On the semi-insulating substrate, a P-type semiconductor 33 is formed by etching based on a semiconductor laminated structure in which an N-type semiconductor 31, an I-type semiconductor 32 and a P-type semiconductor 33 each having a desired layer thickness are sequentially laminated from below.
The I-type semiconductor 32 is processed to have a predetermined width, and the N-type semiconductor 31 is processed by etching to have a wider width than the predetermined width of the P-type semiconductor 33 and the I-type semiconductor 32. . And, for electrical connection to the outside, P
A P-type ohmic electrode 36 is formed on the upper surface of the type semiconductor 33, and the N-type
The basic structure is a structure in which an N-type ohmic electrode 37 is formed on the upper surface of a type semiconductor. This structure is generally manufactured by a so-called semiconductor planar processing technology such as an ion implantation technology or an epitaxial growth technology, a photolithography technology, a semiconductor etching technology, an insulating film formation technology, and an electrode formation technology.

This PIN diode is combined with a coplanar line to constitute a high frequency switch of one input and three switching outputs. The three switching is a configuration in which three unit switch configurations are connected. According to the above-mentioned document, the unit switch configuration is as shown in FIG. One end is connected to a high-frequency signal source, and the other end is connected to the middle of the coplanar line signal line 10 connected to the output terminal. The anode of the PIN diode 30 is connected to the ground, and the cathode of the PIN diode 30 is connected to the ground line 20. I have.

The operation of the unit switch will be described. PI
When the N diode 30 is forward biased, the PIN diode 30 becomes equivalently a resistance component of several Ω, and the signal line 10
Is short-circuited to the ground line 20, and as a result, the high-frequency signal input to the signal line is reflected here and is not output. This is the switch-off state.

On the other hand, when the PIN diode 30 is reverse-biased, the PIN diode 30 is equivalent to several tens of fF.
And has a function of separating the signal line 10 and the ground line 20. As a result, the high-frequency signal input to the signal line is transmitted to the output terminal. This is a switch-on state.

Next, the connection between the PIN diode 30 and the coplanar signal line 10 or the ground line 20 will be described. According to the chip photograph of the entire switch MMIC shown in the above-mentioned document, the PIN diode 30 is disposed below the coplanar signal line 10 in the center in the line width direction. The N-type ohmic electrode corresponding to the cathode of the PIN diode 30 is connected to ground lines 20 located on both sides of the signal line 10 by ground wiring.

A plan view of the PIN diode 30 including a part of the portion that cannot be directly observed from the chip photograph, a coplanar line, a PIN diode arrangement position and a connection structure thereof observed from the chip photograph are shown. FIG. 6 shows a simplified diagram in combination with the plan view.

The PIN diode 30 is considered to have the following planar structure in light of the above-mentioned sectional structure. For convenience of explanation, the description will be made from the P-type ohmic electrode corresponding to the uppermost portion of the sectional structure along the path of the direct current at the time of forward bias. The P-type ohmic electrode is connected to the signal line 10, and the center of the P-type ohmic electrode is arranged on the center line of the signal line. P-type ohmic electrode 36
Is surrounded by a contour line of the P-type semiconductor 33. This contour is common to the contour of the I-type semiconductor 32. According to the literature, this dimension is 6 μm × 6 μm or 6 μm × 10
μm. An outline of the N-type semiconductor 31 exists so as to surround the outline. An N-type ohmic electrode 37 is arranged between the outline and the outline of the I-type semiconductor 32. The ground wiring 34 connects the N-type ohmic electrode 37 to the ground line 20.

FIG. 6 shows the case where the N-type ohmic electrode 37 is arranged along the two long sides of the PIN diode 30, but there may be a case where the N-type ohmic electrode is arranged along the four sides. . Even if there is a difference between the guesswork and the actuality in this portion, the plane area of the N-type semiconductor 31 is constant, so that it is not essential in the description of the conventional example for the present invention.

The capacitance component at the time of reverse bias is an I-type semiconductor 3
In addition to the capacitance determined by the dielectric constant, area, and layer thickness of No. 2, the signal line 10 and the N-type semiconductor 31, the N-type ohmic electrode 37 facing the signal line 10, and the ground wiring connected to the ground line 20 from the N-type ohmic electrode 37. 34, and a parasitic capacitance formed by the above. As the capacitance of the PIN diode 30 at the time of reverse bias is smaller, the signal component leaking to the ground line via the capacitance can be reduced, so that the transmittance of the high-frequency signal increases. In this way, the high frequency signal is turned on and off.

Further, as another conventional example, there is an example in which a Schottky diode is used as a semiconductor element and a detector is configured in combination with a coplanar line. IEEE Transaction
onMicrowave Theory and Techniques, vol.46, No5, May
Yung hong Wu et al., 1998, Microwave P
tSi-Si Schottky-Barrier-Detector Diode Fabrication
Using an Implanted Active Layer on High-Resistivi
ty Silicon Substrate is that.

In this example, an N-type conduction region is formed on a high-resistance silicon substrate by an ion implantation technique, a PtSi is placed on the N-type conduction region as a Schottky metal to form a Schottky diode structure, and the structure is connected to a coplanar line. This is an example in which a high-frequency detection circuit is configured. According to this document, as shown in FIG. 8, a signal line 10 and a ground line 20 are used as a connection form between a coplanar line and a Schottky diode.
The Schottky diode 35 is arranged in the gap between the two.

[0015]

However, in the high-frequency switch circuit of the first example, the N-type semiconductor 31, the N-type ohmic electrode 37, and the ground wiring 34 connecting the N-type ohmic electrode 37 to the ground line 20 are composed of a signal line. 10
It is a structure facing. Therefore, when a high frequency is transmitted when the switch is turned on, the capacitance component at the time of reverse bias, which is harmful to increase the transmittance, is increased as follows. That is, in addition to the essentially unavoidable effective element capacitance determined by the dielectric constant, area and layer thickness of the I-type semiconductor, the opposing area between the signal line 10 and the conductive area outside the effective element area is limited. There is a proportional coupling capacity. There is a problem that this coupling capacity prevents low-loss transmission of high-frequency signals.

The arrangement of the Schottky diode in the high-frequency detection circuit of the second example is certainly effective in eliminating such an area where the signal line 10 and the semiconductor element face each other, but the electromagnetic field distribution of the coplanar line is eliminated. In consideration of this, the electric field is most concentrated in the gap between the signal line 10 and the ground line 20, and arranging the semiconductor element there inadvertently modulates part of the characteristic impedance of the transmission line. In addition, there is a problem that unnecessary reflection occurs due to discontinuity of characteristic impedance.

Further, for the following reasons, the second
As described in the example, there is a problem that the semiconductor element cannot be arranged in the gap between the signal line 10 and the ground line 20 of the coplanar line. The transmission line needs to realize a desired characteristic impedance in circuit design. In the case of a coplanar line, the characteristic impedance is determined by approximately two factors. One element is the width of the signal line 10 and the other element is the signal line 10 and the ground line 2.
This is a gap with zero. Signal line 10 and ground line 2
In order to arrange a semiconductor element in the gap with 0, the width of the semiconductor element must be smaller than the width of the gap, but this condition is always satisfied after securing the characteristic impedance required for circuit design. Not in translation. In that case, as in the first example, a semiconductor element must be arranged below the signal line 10.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to prevent unnecessary leakage and reflection of signals in a high-frequency circuit in which a semiconductor element is connected to a coplanar line. It is a structure.

[0019]

According to a first aspect of the present invention, there is provided a high-frequency circuit which is manufactured on a semiconductor substrate and includes a signal line and a ground on the same plane. A coplanar line composed of tracks,
In a high-frequency circuit having a semiconductor element having at least two terminals connected between a signal line and a ground line of the coplanar line, and the semiconductor element is arranged with an overlap under the signal line, the semiconductor element is , Which is smaller than the signal line width and located at the side end below the signal line, one of the two terminals is connected to the signal line located above it, and the other terminal is most connected to the ground line. It is characterized by being connected by a ground wiring at a close position.

According to a second aspect of the present invention, in the high frequency circuit according to the first aspect, the semiconductor element is divided into a plurality of parts by an element isolation structure, and both side end portions under the signal line. , And are connected by ground wiring at positions closest to the ground lines.

According to a third aspect of the present invention, in the high frequency circuit according to the second aspect, each of the divided semiconductor elements is arranged at a symmetrical position with respect to the center line of the signal line, and A pair of semiconductor elements having the same shape is formed.

According to a fourth aspect of the present invention, in the high frequency circuit, the semiconductor substrate is insulative, and the semiconductor element has at least a first conductive semiconductor layer connected to a signal line and a second conductive semiconductor layer bonded to the semiconductor substrate.
A conductive semiconductor layer, the second conductive semiconductor layer has an exposed surface on which other semiconductor layers are not formed,
The exposed surface and the ground line are connected by a ground line.

According to a fifth aspect of the present invention, in the high frequency circuit, the semiconductor elements are arranged in such a manner that the outer edge of the signal line passes through the plane area of the second conductive semiconductor layer.

According to a sixth aspect of the present invention, in the high frequency circuit, the semiconductor element comprises:
It is a PIN or NIP type diode having an I-type semiconductor layer between the first conductive semiconductor layer and the second conductive semiconductor layer.

According to a seventh aspect of the present invention, in the high frequency circuit, the ground wiring is formed on an exposed surface of the second conductive semiconductor layer or on a semiconductor substrate outside an electrode formed on the exposed surface in a region below the signal line. Are not formed.

In the above configuration, the terminals are used as input terminals and output terminals for signals of the semiconductor device. When the semiconductor element has a stacked structure of semiconductor layers, it means the uppermost layer to which a signal is input and the lowermost layer to which a signal is output. or,
When a metal electrode is formed on the upper surface of the uppermost layer or on the exposed surface of the lowermost layer, it also means the metal electrode. The meaning of the exposed surface of the second conductive semiconductor layer means the surface on which the first conductive semiconductor layer and other semiconductor layers are not stacked on the second conductive semiconductor layer. Therefore, even if a metal electrode is formed on that surface or covered with a protective film,
It is an exposed surface. The planar region of the second conductive semiconductor layer is a region in a cross section parallel to the substrate.

[0027]

The semiconductor device has a coplanar line composed of a signal line and a ground line on the same plane, and at least two terminals connected between the signal line and the ground line of the coplanar line. In a high-frequency circuit in which the semiconductor element is arranged under the signal line with an overlap, generally, a semiconductor having conductivity on the side electrically connected to the ground line, an ohmic electrode having an electrical contact with the semiconductor, and The ground wiring from there to the ground line has a structure opposing the signal line, and a coupling capacitance proportional to the area of the opposition is generated.

According to the high-frequency circuit of the first aspect, the semiconductor element is disposed at a side end portion below the signal line. One terminal of the semiconductor element is connected to a signal line immediately above, and the other terminal is connected to a ground line at a position closest to the ground line by a ground wiring.

According to the present invention, the area of the ground wiring can be reduced by simply moving the semiconductor element disposed below the signal line and at the center in the line width direction to the side end portion below the signal line. The facing area can be reduced, the coupling capacitance in proportion to the area facing the signal line is reduced, and a high-frequency circuit is provided in which unnecessary leakage and reflection are reduced as compared with the related art.

Further, according to the high frequency circuit of the present invention, the semiconductor element is separated into a plurality by the element isolation structure, and is disposed at both ends below the signal line.
Therefore, the ground wiring in the region where the semiconductor element is not formed in the central portion under the signal line can be removed. As a result, the area of the ground wiring can be reduced, so that the area facing the signal line can be reduced, and the coupling capacitance can be reduced. Can be reduced.

Here, considering the electromagnetic field distribution of a high-frequency signal propagating through a coplanar line that has no connection in the middle of the line, the electromagnetic field distribution is symmetrical about the center line of the signal line in the width direction of the signal line. The line is symmetric. If a semiconductor element is disposed at one end of the signal line, the symmetry of the distribution of the electromagnetic field of the high frequency propagating through the transmission line may be broken, causing unnecessary reflection, and the propagation mode may be disturbed. According to the high-frequency circuit of the second aspect, even when the effective area of the semiconductor element is constant before and after the division, the semiconductor element is merely disposed at one side end of the signal line. In addition, since they are arranged at both ends, the disturbance of the electromagnetic field distribution can be further reduced.

According to the high frequency circuit of the third aspect, each of the divided semiconductor elements is arranged at a position symmetrical with respect to the center line of the signal line, and forms a semiconductor pair having the same shape as each other. ing. Accordingly, the facing area can be reduced, the coupling capacitance and unnecessary leakage and reflection can be reduced as compared with the related art, and the symmetry of the electromagnetic field distribution of the high frequency propagating through the transmission line is not disturbed at all.

In the high-frequency circuit according to the fourth aspect, the semiconductor element is a semiconductor element laminated on an insulating substrate, and at least the uppermost first conductive semiconductor layer and the lowermost second conductive semiconductor layer. A semiconductor layer. The lowermost second conductive semiconductor layer has an exposed surface on which no other semiconductor layer is formed in order to connect to the ground line. The exposed surface and the ground line are connected by a ground line. Therefore, the ground wiring exists almost on the exposed surface of the second conductive semiconductor layer, and is not formed on the insulating substrate on which the second conductive semiconductor layer is not formed. As a result, if the plane area of the second conductive semiconductor layer is fixed, the area of the ground wiring facing the signal line can be reduced, and the coupling capacitance can be reduced.

In the high-frequency circuit according to the fifth aspect, the semiconductor elements are arranged in such a manner that the outer edge of the signal line passes through the plane area of the second conductive semiconductor layer. That is, the ground wiring can be connected to the exposed surface of the second conductive semiconductor layer without directly bonding to the insulating substrate in a region below the signal line. Therefore, since the conductive region does not expand, the coupling capacity can be reduced. Further, by providing a part of the planar region of the second conductive semiconductor layer outside the signal line, the area facing the signal line is reduced by the area provided outside the signal line, and the coupling capacitance is reduced. Can be.

In the high frequency circuit according to claim 6, the semiconductor element is a PIN or NIP diode having an I-type semiconductor layer between the first conductive semiconductor layer and the second conductive semiconductor layer. Thus, a high-frequency switch circuit, a detection circuit, and the like can be easily realized.

In the high frequency circuit according to the seventh aspect, the ground wiring is formed on the exposed surface of the second conductive semiconductor or on the semiconductor substrate outside the electrode formed on the exposed surface in the region below the signal line. Is not formed. Therefore, the opposing area does not become larger than the planar region of the second conductive semiconductor below the signal line, so that the coupling capacitance can be reduced.

[0037]

Embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to the following examples. (First Embodiment) FIG. 1 shows an example in which a high-frequency switch circuit is constructed by combining the present invention with a coplanar line using a PIN diode as a semiconductor element. The figure is a top view in which a part of the switch circuit is cut out. The characteristic impedance of the coplanar line is designed to be 50Ω. The effective area of the PIN diode, that is, the area of the I-type semiconductor layer is 100 square μm in total.

This circuit is disposed on a coplanar line, ie, a signal line 110 formed on a semi-insulating GaAs substrate, a ground line 120 formed in parallel on both sides thereof, and on both ends of the signal line. The P-type ohmic electrode 136 as one terminal is connected to the signal line 110 located on the upper side, and the N-type ohmic electrode 137 as the other terminal is closest to the ground line 120 via the ground wiring 134. And PIN diodes 130a and 130b, which are semiconductor elements connected at the specified positions.

Two PIN diodes 130a, 130
b has a plane structure that is completely axisymmetric about the center line of the signal line 110, and has the same cross-sectional structure. Therefore, the electrical characteristics are also completely the same, and they are also characterized in that they are disposed at both side ends of the signal line 110 at symmetrical positions.

FIG. 2 is a schematic diagram showing the relationship between the PIN diode 130a, the signal line 110, and the ground line 120a. The figure is a sectional structural view. In the case of the present embodiment, the PIN diode 130a is formed on a semi-insulating GaAs substrate by an epitaxial crystal growth technique, and the N-type GaAs layers 131a and I which are the second conductive semiconductor layers are arranged in order from the bottom.
Type GaAs layer 132a, P serving as a first conductive semiconductor layer
GaAs layer 133a. In order to enable electrical connection with metal, P-type GaAs layer 133a has
Ohmic electrode 136a is also provided with N-type GaAs layer 1
On the surface on which the I-type GaAs layer 132a and the P-type GaAs layer 133a are not formed, ie, the N-type GaAs
An N-type ohmic electrode 137 is formed on the exposed surface of the s layer 131a.
a is formed. The P-type ohmic electrode 136a
The N-type ohmic electrode 137a is connected to the signal line 110 immediately above, while being connected to the ground line 120a via the ground wiring 134a. The other PI
Similarly to the N diode 130b, the N diode 130b has the signal line 11
0 and the ground line 120b. Note that the exposed semiconductor surface is completely passivated by the insulating film 138.

This structure is manufactured by a so-called semiconductor planar processing technique such as an epitaxial growth technique, a photolithography technique, a semiconductor etching technique, an insulating film forming technique, an electrode forming technique, and a gold plating technique. Signal line 110
By applying a predetermined direct current bias between the ground and the ground lines 120a and 120b, the PIN diode 13
0a and 130b are simultaneously forward-biased or reverse-biased.

When the PIN diodes 130a and 130b are simultaneously forward-biased, an equivalent circuit in which two diodes are connected in parallel is represented by a series connection of a resistance component of 3.25Ω and an induction component of 2.5pH. This is an extremely small impedance compared to the characteristic impedance of the coplanar line of 50Ω. Therefore, the high-frequency signal transmitted so far is reflected here and hardly propagates beyond it. This is the switch-off state.

On the other hand, PIN diodes 130a and 130b
Are simultaneously reverse-biased, an equivalent circuit in which two diodes are connected in parallel has a capacitance component of 40 fF. Since this capacitance is a very small value, its impedance is smaller than the characteristic impedance of the coplanar line of 50Ω.
It corresponds to an extremely large impedance. Therefore, when viewed from the coplanar line, the high-frequency signal is propagated in a state similar to a case where no connection is made in the middle of the line. This is a switch-on state. However, in detail, even if the capacitance value is small, the signal line 11 can be connected through the capacitance.
Signal leakage has occurred from 0 to the ground line 120,
This degree becomes more significant as the capacity is larger.

In this embodiment, the effective area, that is, P-type Ga
Plane sectional area of As layer (I-type GaAs layer) 100 square μm
Is divided into two PIN diodes, that is, P-type GaAs
Layer (I-type GaAs layer) having a plane sectional area of 50 square μm
The PIN diodes 130a and 130b are arranged at both ends of the signal line 110. In the conventional method, that is, when one PIN diode having the same effective area of 100 square μm is arranged in the center of the signal line 110, the equivalent circuit at the time of reverse bias is a capacitance component of 44fF. In the example, the capacity is reduced by about 10%.

The capacitance of the PIN diode 130 at the time of reverse bias includes the capacitance determined by the dielectric constant, the area, and the layer thickness of the I-type semiconductor 132, the signal line 110, the N-type semiconductor 131 opposed thereto, and the N-type ohmic electrode 137. , And the ground wiring 13 which is connected to the ground line 20 therefrom
4 is added. I-type semiconductor 13
The capacitance determined by the dielectric constant, area and layer thickness of No. 2 is theoretically constant as long as the effective area of the PIN diode 130 is kept constant. Compared with the conventional method, the capacitance of the present embodiment can be reduced because of the N-type ohmic electrode 137 and the ground wiring 13 connected therefrom to the ground line 20.
4 and, in particular, the signal line 110
It is considered that the main factor is to reduce the parasitic capacitance formed by the ground wiring 134 and the ground wiring 134 opposed thereto. That is, as shown in FIG. 1, by dividing the element and arranging it at the side end of the signal line 110, no element is formed at the center of the signal line 110, and the signal line 110 is connected to the substrate. There is a part directly facing. Although the area of this portion is equal to the case where one element is arranged at the center without being divided, in the present invention, since the ground wiring 134 is not necessarily formed in that portion, the area facing the signal line 110 is reduced. As a result, the coupling capacity decreases.

Further, as is apparent from FIG.
Ground line 1 for 10 outer edge lines 111 and 112
The N-type GaAs layers 131a, 131a,
A part of the plane area of 31b is overhanging. As a result,
The ground wirings 134a and 134b are not directly connected to the insulating substrate under the signal line 110, but are N-type GaAs.
N-type ohmic electrode 137 on s layers 131a and 131b
a, 137b. Therefore, the coupling capacity can be reduced. Further, the N-type GaAs layers 131a and 131b as the second conductive semiconductor layers below the signal line 110 can be reduced. This result can also reduce the coupling capacity.

When a high-frequency signal is input into a transmission line, the electromagnetic field distribution of the high-frequency signal is generally formed symmetrically with respect to the center line of the transmission line. In this embodiment, the PI
The N diodes 130a and 130b are arranged below the both ends of the signal line 110 at positions that are line-symmetric with respect to the center line of the signal line 110.
Since the characteristics of 30a and 130b are completely equivalent, the symmetry of the electromagnetic field distribution of the high-frequency signal is not disturbed in any bias state. Therefore, a good high-frequency switch circuit can be obtained without a decrease in transmission characteristics due to disturbance of the electromagnetic field distribution, that is, an increase in insertion loss at the time of ON and a decrease in isolation at the time of OFF.

FIG. 3 is a characteristic comparison diagram of a conventional high-frequency switch circuit using a PIN diode having an effective area of 100 square μm and a high-frequency switch circuit according to the present embodiment using two PIN diodes having an effective area of 50 square μm. . This is the result of measuring the equivalent circuit constant of each PIN diode and the transmission characteristics of the high-frequency switch circuit, that is, the insertion loss at the time of ON and the isolation at the time of OFF, using a network analyzer when a 76.5 GHz high-frequency signal line is input. It is.

The resistance components R at the time of forward bias are both 3.2.
5Ω, the induction component L at the time of forward bias is
In the present embodiment, the pH is 2.5, and it can be seen that there is almost no difference between the conventional example and the present embodiment at the time of forward bias. Actually, when the isolation at the time of off was compared as the switch characteristic at the time of forward bias, the same level of isolation as 19 dB was obtained in each case.

The capacitance component C at the time of reverse bias is 4
In contrast to 4 fF, the present embodiment is 40 fF, and a capacity reduction of about 10% is realized as described above. Comparing the on-state insertion loss as the switch characteristics at the time of reverse bias, the present example showed an improvement of 0.9 dB and 0.2 dB compared to 1.1 dB in the conventional example.

As described above, PINs having the same effective area
Even though the diode is used, the PIN diode is divided, and the PIN diodes are arranged at both side ends under the signal line so as to be line-symmetric with respect to the center of the signal line, without deteriorating the isolation characteristics. ,
A high-frequency switch circuit with improved insertion loss characteristics can be realized.

(Second Embodiment) FIG. 4 shows a modification of the high-frequency switch circuit of the present invention. The figure is a top view in which a part of the switch circuit is cut out. The characteristic impedance of the coplanar line is designed to be 50Ω. Also PIN
The effective area of the diode is 100 μm square. Also,
Parts having functions equivalent to those of the first embodiment are denoted by the same symbols.

The present embodiment is different from the first embodiment in that the first embodiment
Instead of the PIN diodes 130a and 130b in the embodiment, one PIN diode 13 having an effective area obtained by adding the effective areas of these two PIN diodes 13
0 is adopted, and it is arranged at one side end under the signal line 110.

As a result, the switch characteristics of this embodiment are as follows.
The value is close to that of the first embodiment (FIG. 3). However, since the symmetry of the electromagnetic field distribution of the high-frequency signal propagating through the transmission line is broken, the characteristics at the time of switch-on are improved as compared with the conventional system, but are inferior to those of the first embodiment. However, in the present embodiment, since the long side of the PIN diode 130 is arranged along the edge of the signal line 110, the area of the N-type GaAs layer 131 extending outside the signal line 110 increases. N-type GaAs facing the signal line 110
The area of the s layer 131 is reduced, which has the effect of reducing the reverse bias capacitance.

In all the above-described embodiments, P
The IN diodes 130a and 130b or the PIN diode 130 are sequentially formed on a GaAs substrate by an N-type semiconductor and an I-type semiconductor.
Although a type semiconductor and a P-type semiconductor were formed, the order may be reversed. At this time, the polarity of the voltage applied to the PIN diode may also be inverted.

In all the above-described embodiments,
Although a PIN diode, which is one of the vertical semiconductor elements, is used as the semiconductor element, any vertical semiconductor element may be used as long as it is a high-frequency signal semiconductor element having at least two terminals.
A horizontal semiconductor element may be used. For example, PN diode, Schottky diode, HBT, FET, HEMT
And the like.

Further, in all of the above-described embodiments, a high-frequency switch is employed as a high-frequency circuit. However, in a high-frequency circuit in which a semiconductor element is formed between a signal line of a coplanar line and a ground line, the signal line and the semiconductor element are connected. The type of the circuit is not limited as long as it is in accordance with the gist of the present invention for reducing the coupling capacitance. In addition to the high-frequency switch, a high-frequency detector may be used.

[0058]

[Brief description of the drawings]

FIG. 1 is a top view of a high-frequency circuit according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a high-frequency circuit according to the first embodiment of the present invention.

FIG. 3 is a characteristic comparison diagram between the conventional example and the first embodiment.

FIG. 4 is a top view of a high-frequency circuit according to a second embodiment.

FIG. 5 is a cross-sectional view of a conventional high-frequency circuit PIN diode.

FIG. 6 is a plan view of a conventional high-frequency circuit.

FIG. 7 is a circuit diagram of a unit switch.

FIG. 8 is a top view of a conventional high-frequency circuit.

[Explanation of symbols]

 110 signal line 120, 120a, b ground line 131, 131a, b N-type GaAs layer 137, 137a, b N-type ohmic electrode 132, 132a, b I-type GaAs layer 133, 132a, b P-type GaAs layer 134, 134a, b Ground wiring 136, 136a, b P-type ohmic electrode 137, 137a, b N-type ohmic electrode 138 Insulating film _// ^/ B

Claims (7)

(57) [Claims] 1. A high-frequency circuit manufactured on a semiconductor substrate, wherein the coplanar line includes a signal line and a ground line on the same plane, and is connected between the signal line and the ground line of the coplanar line. In a high-frequency circuit having a semiconductor element having at least two terminals, and the semiconductor element is arranged under the signal line so as to overlap, the semiconductor element is smaller than the signal line width, and the semiconductor element has a lower side than the signal line. At the end, one of the two terminals is connected to the signal line located thereabove, and the other terminal is connected to the ground line at a position closest to the ground line by ground wiring. A high frequency circuit characterized by: 2. The semiconductor device according to claim 1, wherein said semiconductor element is divided into a plurality of parts by an element isolation structure, and is located at both side ends under said signal line, and is located at a position closest to said ground line by a ground wiring. The high-frequency circuit according to claim 1, wherein the high-frequency circuit is connected. 3. The semiconductor device according to claim 1, wherein each of the divided semiconductor devices is arranged at a position symmetrical with respect to a center line of the signal line, and forms a pair of semiconductor devices having the same shape as each other. Item 3. The high-frequency circuit according to Item 2. 4. The semiconductor substrate is insulative, and the semiconductor element has at least a first conductive semiconductor layer connected to the signal line and a second conductive semiconductor layer bonded to the semiconductor substrate. The second conductive semiconductor layer has an exposed surface on which no other semiconductor layer is formed, and the exposed surface and the ground line are connected by the ground wiring. Claims 1 to 3
The high-frequency circuit according to any one of the above. 5. The semiconductor device according to claim 4, wherein the semiconductor elements are arranged in such a relationship that an outer edge of the signal line passes through a plane area of the second conductive semiconductor layer. High frequency circuit. 6. A semiconductor device according to claim 1, wherein said semiconductor element is a PIN or NIP diode having an I-type semiconductor layer between said first conductive semiconductor layer and said second conductive semiconductor layer. The high-frequency circuit according to any one of claims 4 to 5. 7. The ground wiring is formed on an exposed surface of the second conductive semiconductor layer or on the semiconductor substrate outside an electrode formed on the exposed surface in a region below the signal line. 7. The high-frequency circuit according to claim 4, wherein the high-frequency circuit is not operated.