JP3328486B2 - Delta-sigma modulation type analog / digital conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in analog-to-digital conversion of audio signals and the like. In particular, it is possible to change the sampling frequency and to provide a delta-sigma modulation type analog / digital converter having an integrating circuit. The present invention relates to a digital conversion circuit.

[0002]

FIG. 7 shows a typical prior art analog / digital converter.
FIG. 2 is a block diagram illustrating an electrical configuration of the digital conversion circuit 1. The analog / digital conversion circuit 1 includes an integration circuit 2
, An adder 3, a quantizer 4, and a digital / analog converter 5 are a delta-sigma modulation type analog / digital conversion circuit.

The integrating circuit 2 includes cascaded seventh-order integrators m1, m2,..., M7, and feedback circuits m11, m1.
2, m13 and a feedback resistor r0. The first-order integrator m1 includes an input resistor r1 and a differential amplifier a1.
And a capacitor c1 which is a time constant element. The analog audio signal from the input terminal 6 is input to the inverting input terminal of the differential amplifier a1 via the input resistor r1. The non-inverting input terminal of the differential amplifier a1 is grounded. The output from the differential amplifier a1 is output to the adder 3, and is input to the inverting input terminal via the capacitor c1 and is negatively fed back.

[0004] The remaining integrators m2 to m7 also
1, and the reference numerals of the corresponding parts are the same alphabetical characters with the addition of the subscript corresponding to the order of each of the integrators m2 to m7. Thus, for example, the second
In the next integrator m2, the output from the integrator m1 is input via the input resistor r2, and the output is input to the adder 3 and also to the next-order integrator m3.

The outputs from the integrators m1 to m7 are input to the adder 3 and added to each other as described above, and then input to the quantizer 4. The quantizer 4 derives an output of “1” from the output terminal 7 when the output from the adder 3 is 0 or more, and derives an output of “0” when the output is less than 0. Output added value from ~ m7 is 1
Bit quantization is performed. The output of the quantization result by the quantizer 4 is converted into an analog value by the digital / analog converter 5, and then is negatively fed back to the input side via the feedback resistor r0.

On the other hand, a feedback circuit m11 is provided in association with the second-order integrator m2 and the third-order integrator m3. That is, the output from the integrator m2 is integrated and inverted by the integrator m3, further forward-rotated by the feedback circuit m11, input to the inverting input terminal of the differential amplifier a2 of the integrator m2, and negatively fed back. .

The feedback circuit m11 includes a differential amplifier a11,
It is provided with three resistors r11 to r13.
The output from the differential amplifier a3 is input to the inverting input terminal of the differential amplifier a11 via the input resistor r11. The non-inverting input terminal of the differential amplifier a11 is grounded. The output of the differential amplifier a11 is the output resistance r
13 and input to the inverting input terminal of the differential amplifier a2 via the feedback resistor r12.
1 is negatively fed back to the inverting input terminal.

Similarly, a feedback circuit m12 is provided in association with the fourth-order integrator m4 and the fifth-order integrator m5, and a sixth-order integrator m6 and a seventh-order integrator m7 are provided. Is provided with a feedback circuit m13. The feedback circuit m
12 includes a differential amplifier a12 and resistors r21 to r23, and the feedback circuit m13 includes a differential amplifier a12.
13 and resistors r31 to r33.

By the partial negative feedback loop of each of the feedback circuits m11, m12, and m13, each of the feedback circuits m11, m12, and m13 near the upper limit of the used frequency band in the quantization noise distribution.
A dip occurs in the frequency individually corresponding to each of m12 and m13, whereby the level of the quantization noise is set to a desired level, for example, -100 (dB) or less, up to the upper limit of the use frequency band, for example, 20 (kHz). Zero point control is realized.

[0010]

SUMMARY OF THE INVENTION A delta-sigma modulation type analog / digital conversion circuit 1 constructed as described above.
In, for example, when oversampling the sampling frequency Fs by N times in order to expand the use frequency band in the production of a sound source or the like, the overall quantization noise level is reduced by almost 30 LogN (dB), that is, For example, if N = 2, the quantization noise straight line of 6 (dB / oct) and the noise energy per each frequency are reduced by 3 (dB), so that it can be reduced by about 9 (dB).

However, the integration curve representing the relationship between the integration value and the integration time has not changed, and
The frequency at which the zero point control is performed does not change, and the distribution frequency of the quantization noise does not change. Therefore, even if the sampling frequency Fs is increased, the frequency band to be used cannot be expanded at a desired S / N.
As described above, there is a problem that the use frequency band corresponding to the use, that is, the sampling frequency Fs cannot be obtained.

An object of the present invention is to provide a delta-sigma modulation type analog / digital conversion circuit capable of obtaining a frequency band corresponding to a desired sampling frequency.

[0013]

Means for Solving the Problems] delta-sigma modulation type analog / digital conversion circuit according to a first aspect of the invention, cascaded
Product with connected integrator, feedback circuit and feedback resistor
Divider, adder, quantizer and digital / analog converter
Output from each of the integrators is input to the adder
Are added to each other and then input to the quantizer,
Further, the output of the quantization result by the quantizer is
Converted to analog value by digital / analog converter
Later, when negative feedback is applied to the input side via the feedback resistor,
In addition, due to the partial feedback loop of each feedback circuit,
This causes a dip in the quantization noise characteristics of the
By the upper limit of the frequency band used, the quantization noise
In a delta-sigma modulation type analog / digital conversion circuit that performs zero-point control in which the level of the integrator is equal to or less than a desired value, when sampling is performed with the sampling frequency changed to N times, the input resistance and feedback capacitance of the integrator are reduced.
Select at least one according to multiple N of sampling
, The time constant of each of the integrators is reduced to 1 /
In the N, the frequency of performing the zero point control, characterized in this <br/> and to N times.

According to the above arrangement, for example, when oversampling is performed, the quantization noise distribution is shifted to a higher frequency side by the oversampling, and the quantization noise energy per unit frequency band is reduced. The frequency at which the zero point control is performed can be increased by making the integration curve of the integrator steep, and the desired S
/ N can be secured and the frequency band to be used can be expanded.

[0015] delta-sigma modulation type analog / digital conversion circuit according to a second aspect of the invention, cascaded product
Integrator and adder with divider, feedback circuit and feedback resistor
Device, quantizer and digital / analog converter
The outputs from the integrators are input to the adders and mutually
After being added, it is input to the quantizer,
The output of the quantization result by the quantizer is
After being converted to an analog value by a log converter, the feedback
Negative feedback is provided to the input side via a resistor.
Quantization of high frequency components by partial feedback loop by circuit
This causes a dip in the noise characteristic, which
Desired level of the quantization noise up to the upper limit of the wavenumber band
In the delta-sigma modulation type analog / digital conversion circuit which performs the zero point control which is equal to or less than the value of, when sampling is performed by changing the sampling frequency to N times, the gain of the integrator constituting the integration circuit is set to 1 / N. this is
And by the frequency of performing the zero point control, characterized in this <br/> and to N times.

According to the above configuration, it is possible to easily obtain an integration curve corresponding to the sampling frequency and obtain a desired use frequency band by adjusting the gain without changing the time constant element of the integrator. .

Furthermore, a delta-sigma modulation type analog / digital conversion circuit according to a third aspect of the present invention is cascaded.
Circuit with integrated integrator, feedback circuit and feedback resistor
, Adder, quantizer, digital / analog converter
The output from each of the integrators is input to the adder
After being added to each other, they are input to the quantizer and further
The output of the result of quantization by the quantizer is
After being converted to an analog value by the
While being negatively fed back to the input side via the feedback resistor,
Due to the partial feedback loop of each feedback circuit, high frequency components
Causes a dip in the quantization noise characteristic of the
Up to the upper limit of the used frequency band.
In a delta-sigma modulation type analog / digital conversion circuit that performs zero-point control in which the bell is equal to or less than a desired value, when sampling is performed with the sampling frequency changed to N times, the input resistance and feedback capacitance of the integrator are reduced.
And one of them selectively according to the multiple N of sampling.
By changing the gain of the integrator with switched, and the 1 / N the time constant of the integrator, the zero point system
It is characterized in that the control frequency is increased N times .

According to the above configuration, for example, when oversampling is performed, the time constant of the time constant element of the integrator constituting the integration circuit is reduced, and the gain of the integrator is reduced. Also in this case, it is possible to obtain a use frequency band corresponding to the sampling frequency.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
The following is a description based on FIGS. 1 to 4.

FIG. 1 is a block diagram showing an electrical configuration of an analog / digital conversion circuit 11 according to one embodiment of the present invention. The analog / digital conversion circuit 11 is a delta-sigma modulation type analog / digital conversion circuit including an integrating circuit 12, an adder 13, a quantizer 14, and a digital / analog converter 15. .

The integrating circuit 12 includes cascaded seventh-order integrators M1, M2,..., M7, and feedback circuits M11, M1.
2, M13 and a feedback resistor R0. The first-order integrator M1 includes an input resistor R1 and a differential amplifier A1.
And a time constant element T1. The analog audio signal from the input terminal 16 is input to the inverting input terminal of the differential amplifier A1 via the input resistor R1. The non-inverting input terminal of the differential amplifier A1 is grounded. The output from the differential amplifier A1 is output to the adder 13, and is input to the inverting input terminal via the time constant element T1 and is negatively fed back.

FIG. 2 is an electric circuit diagram showing a specific configuration of the time constant element T1. The time constant element T1 has a plurality of n feedback capacitors C1, C2,..., Cn arranged in parallel with each other and having one end commonly connected to the output of the differential amplifier A1.
And a switching element SW having individual contacts individually connected to the other ends of the feedback capacitors C1 to Cn and a common contact connected to the inverting input terminal of the differential amplifier A1. The switching element SW corresponds to the level of the control signal applied to the control terminal 18,
It selectively conducts to each individual contact. Each of the feedback capacitors C1 to C1
For example, Cn is formed such that the feedback capacitor C1 has a larger capacitance on the feedback capacitor Cn side than the feedback capacitor Cn and has multiples N1 (= 1), N2 and N2 of oversampling as described later.
, Nn, C1 · N1 = C2 · N2 = ... = Cn · Nn.

Therefore, the standard sampling frequency F
For example, for a feedback capacitance C1 corresponding to s, N2 = 2
Is equal to C1 / 2. Similarly, the capacitance of the feedback capacitance Cn corresponding to Nn-times oversampling is C1 / Nn. Thereby, the slope of the integration curve of the integrator M1 becomes N times corresponding to the sampling frequency N · Fs.

The remaining integrators M2 to M7 are also provided by the integrator M
1, and the reference numerals of the corresponding parts are the same alphabetical characters with the addition of a subscript corresponding to the order of each of the integrators M2 to M7. Thus, for example, the second
In the next integrator M2, the output from the integrator M1 is input via the input resistor R2, and the output is input to the adder 13 and also to the next-order integrator M3. The time constant elements T2 to T7 have the same configuration as the time constant element T1. The switching elements SW in each of the time constant elements T1 to T7 are controlled in response to a control signal from the control terminal 18 so as to be interlocked with each other to conduct to an individual contact corresponding to the control signal. .

The outputs from the integrators M1 to M7 are input to the adder 13 and added to each other as described above, and then input to the quantizer 14. In the quantizer 14, the adder 1
When the output from 3 is greater than or equal to 0, the output of "1" is derived from the output terminal 17, and when the output is less than 0, the output of "0" is derived. Thus, the output added value from each of the integrators M1 to M7 is One bit quantization is performed. Also, this quantizer 1
4 is converted to an analog value by the digital / analog converter 15 and then output to the feedback resistor R.
It is negatively fed back to the input side via 0.

On the other hand, a feedback circuit M11 is provided in association with the second-order integrator M2 and the third-order integrator M3. That is, the output from the integrator M2 is integrated and inverted by the integrator M3, further forward-rotated by the feedback circuit M11, then input to the inverting input terminal of the differential amplifier A2 of the integrator M2 and negatively fed back. .

The feedback circuit M11 includes a differential amplifier A11,
It is provided with three resistors R11 to R13.
The output from the differential amplifier A3 is input to the inverting input terminal of the differential amplifier A11 via the input resistor R11. The non-inverting input terminal of the differential amplifier A11 is grounded. The output of the differential amplifier A11 is the output resistance R
13 and input to the inverting input terminal of the differential amplifier A2 via the feedback resistor R12.
1 is negatively fed back to the inverting input terminal.

Similarly, a feedback circuit M12 is provided in association with the fourth-order integrator M4 and the fifth-order integrator M5, and a sixth-order integrator M6 and a seventh-order integrator M7 are provided. Is provided with a feedback circuit M13. The feedback circuit M
12 includes a differential amplifier A12 and resistors R21 to R23, and the feedback circuit M13 includes a differential amplifier A12.
13 and resistors R31 to R33.

When a sine wave as shown in FIG. 3A is input from the input terminal 16, the outputs from the integrators M1 to M7 are as shown in FIGS. 3B to 3H, respectively. To
The higher the degree, the lower the degree, and the output from the adder 13 becomes as shown in FIG. As a result, the output from the quantizer 14 to the output terminal 17 is as shown in FIG.
(J), the input signal shown in FIG. 3A is converted into 1-bit digital data by delta-sigma modulation.

In the analog / digital conversion circuit 11 configured as described above, the standard sampling frequency F
Assuming that s is, for example, 44.1 (kHz), the quantization noise characteristic in a state where the partial feedback is not performed by the feedback circuits M11 to M13 is as shown in FIG.
Therefore, as shown by reference numeral α in FIG. 4A, the desired S / N ratio is higher than 9 kHz.
-100 (dB) cannot be secured. For this reason, as shown in FIG. 4B, the partial feedback loop by each of the feedback circuits M11 to M13 causes a dip as shown by the reference numeral β in the quantization noise characteristic of the high-frequency component. Frequency band to be used, for example, 22
(KHz), the quantization noise is suppressed to -100 (dB) or less.

In the analog / digital conversion circuit 11 of the present invention, as shown in FIG.
The feedback capacitors C1 to Cn of T7 are selectively switched and used according to the multiple N of oversampling. Therefore, the time constant of each of the integrators M1 to M7 becomes 1 / N when the sampling frequency Fs is oversampled by N times, and the zero point frequency by the partial feedback loop in each feedback circuit M11 to M13 also becomes N times. , The upper limit of the frequency band used at the normal sampling frequency Fs is Fh
When the zero point control as described above is used, the high frequency limit frequency is set to N ·
It can be expanded to Fh.

In FIG. 4C, assuming that N = 2, the sampling frequency Fs is 88.times.2 which is twice the value of 44.1 (kHz).
9 shows quantization noise characteristics when oversampling is performed at 2 (kHz). As is clear from FIG. 4C, the time constant of each of the integrators M1 to M7 is １ ／, so that the zero point frequency is doubled.

In this way, it is possible to obtain a frequency band to be used corresponding to a sampling frequency according to a purpose such as sound source production, and to improve the convenience in transmitting and recording digital signals.

As another embodiment of the present invention, as shown by an integrator Ma in FIG.
7, the time constant elements T1 to T7 are realized by a fixed feedback capacitance C. In place of this, the input resistors R1 to R7, which are another element for determining the time constant, are connected in parallel to each other. It may be realized by the resistors Z1 to Zn and the switching element SW which selectively uses them. The same effect can be obtained by changing the feedback capacitances C1 to Cn and the input resistances Z1 to Zn in combination with each other.

Further, as shown by an integrator Mb in FIG. 6, the integrator is constituted by an integrating stage Mc and a gain adjusting stage Md provided in front of the integrating stage Mc.
The gain g in the gain adjustment stage Md may be set to 1 / N. In this case, it is possible to easily cope with an arbitrary multiple N by continuously changing it without performing complicated time constant element switching. Further, the gain adjustment and the time constant adjustment may be used together.

It is needless to say that the present invention can be used for performing downsampling where N <1. Further, the order of the integrator is not limited to the seventh order.

[0037]

As described above, in the delta-sigma modulation type analog / digital conversion circuit according to the first aspect of the present invention, when sampling is performed with the sampling frequency changed to N times, the input resistance and feedback of the integrator are returned. Small capacity
Select at least one of them according to the multiple N of sampling
, The time constant of each of the integrators is set to 1 / N
To make the frequency for performing the zero point control N times.

Therefore, the integration curve of the integrator can be made to correspond to a desired sampling frequency, and a desired use frequency band can be obtained.

In the delta-sigma modulation type analog / digital conversion circuit according to the second aspect of the present invention, when the sampling frequency is changed to N times and sampling is performed, the gain of the integrator constituting the integration circuit is increased. To 1 /
By setting N, the frequency at which the zero point control is performed is set to N
Double it.

Therefore, without changing the time constant element of the integrator, it is possible to easily obtain an integration curve corresponding to the sampling frequency and obtain a desired use frequency band by adjusting the gain.

Further, in the delta-sigma modulation type analog / digital conversion circuit according to the third aspect of the present invention, when the sampling frequency is changed to N times and the sampling is performed, the input resistance of the integrator and the feedback Content
At least one of the quantities corresponds to a multiple N of the sampling
With selectively switched by changing the gain of the integrator, and the time constant of the integrator and 1 / N Te, before
The frequency for performing the zero point control is increased by N times.

Therefore, for example, when performing oversampling, the time constant of the time constant element of the integrator constituting the integration circuit is reduced, and the gain for the integrator is reduced. Also in this case, it is possible to obtain a use frequency band corresponding to the sampling frequency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of an analog / digital conversion circuit according to an embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing a specific configuration of a time constant element in an integrator in the analog / digital conversion circuit.

FIG. 3 is a waveform chart of each part for explaining a conversion operation of the analog / digital conversion circuit.

FIG. 4 is a graph for explaining a change in quantization noise distribution due to zero point control in a feedback circuit.

FIG. 5 is an electric circuit diagram of an integrator according to another embodiment of the present invention.

FIG. 6 is an electric circuit diagram of an integrator according to still another embodiment of the present invention.

FIG. 7 is a block diagram illustrating an electrical configuration of a typical conventional analog / digital conversion circuit.

[Explanation of symbols]

 Reference Signs List 11 analog / digital conversion circuit 12 integration circuit 13 adder 14 quantizer 15 digital / analog converter 18 control terminal C1 to Cn feedback capacitance M1 to M7 integrator M11 to M13 feedback circuit Ma integrator Mb integrator R1 to R7 input Resistance (time constant element) SW switching element T1 to T7 time constant element

Claims (3)

(57) [Claims] A cascaded integrator, feedback circuit and feedback circuit.
Integrator with feedback resistance, adder, quantizer and digital
/ Analog converter, and the output from each of the integrators is
After being input to the adder and added to each other, the quantum
Input to the quantizer and further quantized by the quantizer.
The output of the result is analyzed by the digital / analog converter.
After being converted to a feedback value, a negative
The feedback is performed and the partial feedback loop
The quantization noise characteristics of the high frequency components
To the upper limit of the frequency band used.
Zero point system to keep the quantization noise level below the desired value
In a delta-sigma modulation type analog / digital conversion circuit that performs control, when sampling is performed with the sampling frequency changed to N times, the input resistance and feedback capacitance of the integrator are reduced.
At least one is selected according to the multiple N of sampling.
By selectively switching, the time constant of each of the integrators is set to 1
/ N, the frequency at which the zero point control is performed is multiplied by N times. A delta-sigma modulation type analog / digital conversion circuit. 2. A cascaded integrator, a feedback circuit and a feedback circuit.
Integrator with feedback resistance, adder, quantizer and digital
/ Analog converter, and the output from each of the integrators is
After being input to the adder and added to each other, the quantum
Input to the quantizer and further quantized by the quantizer.
The output of the result is analyzed by the digital / analog converter.
After being converted to a feedback value, a negative
The feedback is performed and the partial feedback loop
The quantization noise characteristics of the high frequency components
To the upper limit of the frequency band used.
Zero point system to keep the quantization noise level below the desired value
In the delta-sigma modulation type analog / digital conversion circuit for controlling, when sampling is performed by changing the sampling frequency to N times, the gain of the integrator constituting the integration circuit is set to 1 / N , whereby the zero point is reduced. Control frequency
A delta-sigma modulation type analog / digital conversion circuit characterized in that the number is multiplied by N. 3. A cascaded integrator, feedback circuit and feedback circuit.
Integrator with feedback resistance, adder, quantizer and digital
/ Analog converter, and the output from each of the integrators is
After being input to the adder and added to each other, the quantum
Input to the quantizer and further quantized by the quantizer.
The output of the result is analyzed by the digital / analog converter.
After being converted to a feedback value, a negative
The feedback is performed and the partial feedback loop
The quantization noise characteristics of the high frequency components
To the upper limit of the frequency band used.
Zero point system to keep the quantization noise level below the desired value
In a delta-sigma modulation type analog / digital conversion circuit that performs control, when sampling is performed with the sampling frequency changed to N times, the input resistance and feedback capacitance of the integrator are reduced.
At least one is selected according to the multiple N of sampling.
By changing the gain of the integrator with switched on択的, as a 1 / N the time constant of the integrator, the Ze
A delta-sigma modulation type analog / digital conversion circuit characterized in that the frequency for performing point control is increased N times .