JP3323893B2 - Semiconductor manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an integrated circuit structure,
A polycrystalline silicon film serving as the silicon gate material is relates to the way of forming the gate line shape aim.

[0002]

2. Description of the Related Art In the formation of an integrated circuit structure, in recent years, as the degree of integration of elements has been increased, the step of the elements has become larger. The step shape of the cross section of the element is designed depending on the function to be added to the semiconductor device to be manufactured. However, the distance between the three-dimensional shape and the amount of incident light reflected from the polycrystalline silicon film used in the photolithography process is very small. There is a high dependency on In other words, a slight difference in element shape greatly changes the amount of reflected light, adversely affects the solidification behavior of the resist film, and ultimately significantly changes the shape of the gate wiring.

[0003] As a method for suppressing halation, an antireflection film or the like has been used, but the number of steps is increased, which is not preferable in operation. Further, in a batch CVD (chemical vapor deposition) furnace for depositing a polycrystalline silicon film, an operation for controlling a gas flow and a substrate temperature to keep a deposition rate constant is performed, so that different histories are obtained for each silicon substrate. Often have. In addition, the deposition rate fluctuates daily and monthly, and the optical thickness, which is the product of the geometrical thickness of the polycrystalline silicon deposited film and the refractive index of the film, also changes daily. Was.

[0004]

The conventional method of manufacturing a semiconductor device is constituted as described above. When the optical film thickness of a polycrystalline silicon film varies in a deposition CVD furnace, it is difficult to carry out photolithography. There has been a problem that the shape of the gate is greatly deformed, and the electrical characteristics are significantly deteriorated. The present invention has been made in order to solve the above-described problems, and it is intended that the variation in film thickness in a deposition furnace for processing several tens to several hundreds of sheets per batch does not affect a lithography process which is a subsequent process. Of semiconductors aimed at
A manufacturing method is provided .

[0005]

Means for Solving the Problems The present invention relates to the following: ( 1 ) In the case of forming a polycrystalline silicon film to be a material of a silicon gate, after depositing monitor wafers installed at a plurality of positions in a batch furnace, A semiconductor manufacturing method characterized by selecting and using a wavelength of a light source for photolithography that minimizes the reflectance based on the measurement result, and minimizing the reflectance of the polycrystalline silicon film.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a cross section (field shield type element isolation) of a silicon device.
The lamp light (Hg lamp g-line) applied to the resist film in the photolithography step enters the oxide film and the polycrystalline silicon layer forming the transistor gate wiring, and is reflected on the surface of the next oxide film layer. When the reflected light intensity is high, the resist solidified portion deviates from the target rectangular structure and is deformed.

As a result, the shape of the transistor wiring is changed as shown in the figure by etching after lithography. The phenomenon that the reflectance changes occurs due to the difference in the optical path length until the incident light is reflected by the oxide film below the polycrystalline silicon film. FIG. 2 shows the change in the reflectance due to the difference in the thickness of the polycrystalline silicon film. For example, when the thickness range is set to B, the upper portion (T) and the center portion (C) in the batch furnace are set. ), The difference in reflectance at the bottom (B) is 40% to 60%
Will change to

In the method of forming a polycrystalline silicon film, the wavelength of incident light and the angle of incidence during photolithography (that is,
If the step shape of the semiconductor device at the time of the photolithography process is known, the reflected light intensity is optimal if the complex refractive index at the light source wavelength of the resist, oxide film and polycrystalline silicon film is known. Can be calculated.

[0009] The irradiation light wavelength is g-line of mercury lamp (435 nm).
Let us take the case where is used as an example. When the refractive index of the polycrystalline silicon film is approximated using the value of a silicon single crystal, the dependence of the energy reflectance on the film thickness is as shown in FIG. There is a difference of about 1.5 to 2 times between when the energy reflectance is maximum and when it is minimum. When the energy reflectivity is maximized, the amount of light reflected on the solidified resist portion in FIG. 1 is doubled, so that the shape of the solidified resist portion is greatly deformed by the light reflected from the side wall, and finally the electrical characteristics can be satisfied. Disappears.

As can be seen from FIG. 2, in photolithography using a mercury lamp g-line (435 nm), the thickness of the polycrystalline silicon film for minimizing the amount of reflected light is 170 nm and 21 nm.
It is around 5 nm. However, this value assumes that the refractive index of the film is equal to that of single crystal silicon. Here, assuming that the refractive index of the film is n, the above-mentioned optimal physical film thickness is n
_si / n times. If a film thickness that minimizes such reflectance is known, setting the target film thickness to this value enables control within a range of low reflectance fluctuation even if there is variation in the CVD furnace. For example, the thickness range A or C in FIG. 2 may be adopted. As described above, the film thickness that minimizes the reflectance has a plurality of solutions, but the optimum film thickness may be determined according to the operation speed, process conditions, and the like required for the semiconductor device.

On the other hand, the characteristics of the deposited film change due to the daily / monthly fluctuation of the polycrystalline silicon film deposition furnace. Specifically, there are a deposited film thickness, a deposition rate, a density, an impurity penetration, a particle size change, and the like. Changes in deposition rate, density, impurities, and particle size change the refractive index of the film.

The product of the deposited film thickness and the refractive index of the film is
By changing the optical path length of the reflected light, the amount of reflected light is changed. Therefore, the amount of reflected light can be suppressed to a low value by optimizing the process to a deposited film thickness that minimizes the reflectance.

Although the shape of the device is not a flat structure as described above, since the refractive index of the polycrystalline silicon film is 3 or more, the angle of incidence on the polycrystalline silicon film becomes quite close to the normal direction, and There is almost no angle dependence (see FIG. 3). Therefore, it is hardly affected by the step structure of the semiconductor device (see FIG. 1). Utilizing this feature, a silicon substrate with an oxide film having the same thickness as the semiconductor device before depositing the polycrystalline silicon is installed at the top of the polycrystalline silicon film deposition furnace, and the polycrystalline silicon film is deposited. During the deposition,
Light equal to the light source used for photolithography is incident on the sample surface. The deposition is stopped at a point where the reflectance becomes minimum from the time change of the reflectance of the film and is close to the required film thickness (FIG. 4). Thereby, CV for polycrystalline silicon film deposition
It is possible to eliminate the deformation of the silicon gate caused by the change in the furnace position of the D furnace and the daily / monthly variation.

Further, from the result of measuring the ultraviolet / visible spectrum using the polycrystalline silicon film / oxide film / silicon substrate installed at the uppermost part of the furnace, the wavelength of the incident light that minimizes the amount of reflected light can be determined. (FIG. 5). By transforming the determined wavelength value into a single color using a diffraction grating and a wavelength tunable laser such as a titanium sapphire laser or a dye laser and a white light source such as a halogen lamp, deformation of the silicon gate due to photolithography can be suppressed. .

[0015]

EXAMPLE A sample in which an oxide film (150 nm) was deposited on a silicon substrate in a polycrystalline silicon deposition furnace and a polycrystalline silicon film was deposited in a thickness of 200 nm was used as a sample. This sample has been confirmed to deform the silicon gate when g-line is used. The correlation between the thickness of the polycrystalline silicon film and the reflectance at the Hg lamp g-line was calculated, as shown in FIG. Therefore, the film thickness is set to the film thickness range B.
(Including 200 nm), the shape of the silicon gate was improved by setting the film thickness range to A or C. It was also confirmed that the shape of the silicon gate was not changed by aiming at the position where the reflectance was minimum even with respect to the difference in film thickness due to the difference in the furnace position.

A monitor wafer is placed at each of the upper, middle, and lower positions in a CVD furnace, and after a polycrystalline silicon film is deposited, the spectral reflection spectrum of the wafer is changed from 200 nm to 500 nm.
It measured in the range of. The result is shown in FIG. FIG. 5 simultaneously shows the spectrum results of the wafers at the upper, middle, and lower positions in the furnace, and a shift in the spectral reflection spectrum due to the variation in the film thickness in the furnace is observed.

Referring to FIG. 5, by using a tunable titanium sapphire laser to select a wavelength that minimizes the reflectance and using the same for photolithography, the reflection is performed by using this condition in the next batch and thereafter. The rate could be kept low.

[0018]

As described above, according to the present invention, in a miniaturized semiconductor device having a large step, it is possible to minimize the halation which is likely to occur at the time of photolithography and to control the silicon gate to a target shape. Make it possible.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a mechanism of deformation of a silicon gate shape.

FIG. 2 is a diagram showing a correlation between a polycrystalline silicon film thickness and a reflectance when a mercury lamp g-line (435 nm) is used.

FIG. 3 is a diagram showing a change in reflectance with a change in incident angle of incident light on a polycrystalline silicon film.

FIG. 4 is a diagram showing a change in reflectance when a sample surface is irradiated with an Hg lamp g-line at every deposition time of a polycrystalline silicon film.

FIG. 5 is a diagram showing a state of a shift of a spectral reflection spectrum due to a difference in a position in a CVD furnace.

──────────────────────────────────────────────────の Continued on the front page (72) Inventor Yoshinori Sato 1580 Yamamoto, Tateyama-shi, Chiba Prefecture Inside Nippon Steel Semiconductor Corporation (72) Inventor Hiroyuki Komatsuzaki 1580 Yamamoto, Tateyama-shi, Chiba Prefecture Inside Nippon Steel Semiconductor Corporation ( 72) Inventor Hajime Saito 1580 Yamamoto, Tateyama-shi, Chiba Prefecture Inside Nippon Steel Semiconductor Corporation (72) Inventor Katsuyuki Sato 1580 Yamamoto, Tateyama-shi, Chiba Prefecture Inside Nippon Steel Semiconductor Corporation (56) References JP5 JP-A-343314 (JP, A) JP-A-7-273008 (JP, A) JP-A-1-241125 (JP, A) JP-A 8-97158 (JP, A) JP-A-1-289271 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/205 C23C 16/52 H01L 21/027 H01L 21/336 H01L 29/78

Claims (1)

(57) [Claims] When forming a polycrystalline silicon film to be a material of a silicon gate, a monitor wafer placed at a plurality of positions in a batch furnace is deposited, and a photo spectroscopy that minimizes the reflectance is obtained from a result of spectral spectrum measurement. A semiconductor manufacturing method, wherein a wavelength of a lithography light source is selected and used to minimize the reflectance of a polycrystalline silicon film.