JP3323834B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and, more particularly, to an image processing apparatus for forming an image by performing processing such as shadowing and blanking from a color image.

[0002]

2. Description of the Related Art Various kinds of image processing such as shadowing are performed on images for the purpose of decoration.

In this case, a digital copying machine uses a frame memory, reads necessary points each time and performs image processing by a CPU, but this method is not suitable for real-time processing.

In a black-and-white copying machine, a plate making scanner is used.
Although shadowing processing for giving a shadow in the degree direction is performed, it is also required that a color copying machine performs shadowing processing for each color portion of an image in that color.

FIG. 59 is a view for explaining the principle of the shadowing process.
In the shadowing process, the moving image 601a, which is obtained by moving the image 601 downward to the right by 45 ° with respect to the image 601,
601b and 601c are formed. And the moving image 601
A part of the moving image 601b is a shadow of the image 601a, a part of the moving image 601b is a shadow of the image 601b, and a part of the moving image 601c is a shadow of the image 601b. This is an attachment process (FIG. 59 (a)).

On the other hand, the image 601 is moved downward by 45 ° to the right by, for example, a moving amount 3 corresponding to the moving amount of the moving image 601c to form a moving image 601c ′, and a part of the moving image 601c ′ is formed. Is the shadow of the image 601,
Combining 1 with the shadow 603 is a plane shadowing process (FIG. 59 (b)).

FIG. 60 is an explanatory diagram of a processing method in the stereoscopic shadowing processing. In this processing method, an image 604 shown in FIG.
Is decomposed into color components 604a, 604b, and 604c of Y (yellow), M (magenta), and C (cyan) (FIG. 60).
(B)) The shadows 605a, 605b, 6 ranging from the moving amount 1 to the moving amount 3 are added to the respective color components 604a, 604b, 604c.
05c is formed (FIG. 60C). And image 604
And the shadows 605a, 605b, and 605c are combined with priority at the place where the shadow and the original overlap (FIG. 60D).

FIG. 61 is an explanatory diagram of a processing method in the shadow addition processing. In this processing method, the image 604 shown in FIG. 6A is decomposed into color components 604a, 604b, and 604c (FIG. 61).
(B)), shadows 605a ', 605b', and 605c 'of the movement amount 3 are formed on the respective color components 604a, 604b, and 604c (FIG. 61 (c)). And an image 604 and a shadow 605
a ', 605b', and 605c 'are combined with priority on the original where the shadow and the original overlap (FIG. 61 (d)).

On the other hand, if the original image is thinned or fattened,
In recent years, there has been an increasing demand for image processing for forming a processed image by hollowing out.

In a black-and-white copying machine, data is already written in a frame memory, and an original image is thinned by a CPU.
2. Description of the Related Art An image processing apparatus that performs image processing for increasing the thickness or performing hollowing has been put to practical use. These image processing apparatuses for black-and-white copying machines need to be provided with a frame memory and a CPU, which not only complicates the structure but also is not suitable for real-time processing.

Further, in this type of image processing apparatus for a color image, there is a problem in the color processing when the centering processing is performed as described below.

FIG. 62 is an explanatory diagram of a color image blanking process. In the hollowing process, first, a color image 701 including a C (cyan) component 701a, an M (magenta) component 701b, and a Y (yellow) component 701c is converted into a C component 701a and an M component 701c as shown in FIG. 701b
And Y component 701c. Next, FIG.
As shown in (d), a hollowing process using a thinning process is performed to obtain a hollowed C component 702a, an M component 702b, and a Y component 702c.
By combining the 2a, M component 702b and Y component 702c, a hollow image 702 is obtained.

In this case, the C component 1 of the color image 1
The a / M component 1b and the Y component 1c are each subjected to a centering process to form a centered image 2 and there is no problem in color. FIG. 63 is an explanatory diagram of another hollowing-out process of a color image. A color image is formed by a C component 701a, a C + Y (green) component 701d, and a Y component 701c. In this case, when color imaging is decomposed into color components, FIG.
As shown in FIG. 7, the signal is decomposed into a C component 701a ′ and a Y component 701c ′.

Therefore, as shown in FIG. 3C, a hollowing process using a thinning process is performed to remove the hollowed C component 7.
02a 'and the Y component 702c' are obtained, and these are shown in FIG.
Are combined to obtain a hollowed out image 702 '.
In the inside vent processed image 702 ', the arm 703 b arm portion 703a becomes a Y portion is a C section.

[0015]

By the way, in the above-described shading processing, the color components 604a, 604b, 6
Shadows 605a ', 605b', and 605c 'on 04c
Are formed in a position corresponding to the movement amount 3 in the lower right direction at an angle of 45 ° in the corresponding color, and a desired shadowing process is performed.

However, in the three-dimensional shadowing process described above, FIG.
As shown in (d), an overlapping portion 606 of the shadow 605b and the shadow 605c and an overlapping portion 607 of the shadow 605a and the shadow 605b occur, and the colors of the overlapping portions 606 and 607 interfere with each other. (On color sensation) Discomfort occurs.

The processed image obtained by subjecting the above-described color image 601 'to the above-described hollowing process is the same as that of the arm 60.
Color inconsistency occurs in the portions 3a and 603b, causing a sense of visual discomfort.

In view of the above, the present applicant is configured to add a sub-image to a basic image corresponding to a color original image and form a color image by performing a color conversion process on the basic image and the sub-image at the time of shadowing. A color image processing device has already been proposed.
Hereinafter, a color image processing apparatus according to this proposal will be described.

FIG. 64 is a block diagram showing the overall configuration of the color image processing apparatus according to the present invention. Reference numeral 801 denotes an image which reads a color original image as an original and outputs color data of three colors separated. An image reading unit having a sensor, 802 is an image processing unit, and 803 is an image recording unit.

FIG. 65 is a block diagram showing the configuration of the image processing unit shown in FIG. 64. Reference numerals 804a, 804b, and 804c denote line memories, 805 denotes an image processing unit, 806 denotes a color processing unit, and 807 denotes a selector.

As shown in FIG. 65, three-color data obtained by color separation of a color original image by the image sensor of the image reading unit 801 shown in FIG. 64 is binarized based on a threshold value. The color data is input to each line memory 804a, 804b, 804c for each color.
Also, these line memories 804a, 804b, 80
An image processing unit 805 is connected to the output terminal of 4c.

Color image information is reproduced by mixing three primary colors. In an image system using additive color mixing such as a television, the primary colors are red (R), green (G), and blue (B).
In subtractive color mixing such as photography and printing, the primary color is cyan (C),
Magenta (M) and yellow (Y).

A color processing unit 806 is connected to the image processing unit 805, and a selector 807 is connected to the color processing unit 806. To the selector 807, in addition to the signal from the coloring processing unit 806, color data of three colors is input, and the image data obtained from the selector 807 is input to the image recording unit 803.
Has been entered.

In this conventional example, the image processing unit 805 performs image processing for adding a color shadow portion as a sub-image to a basic image corresponding to the color original image read by the image reading unit 801. I have. In addition, the coloring processing unit 806 performs coloring processing on the basic image and the sub-image in the seven-color mode or the designated color mode. A color image is finally formed and recorded on the image recording unit 803 by the image data output from the selector 807.

In the color conversion process and the shadow portion formation process for the basic image, when colors overlap, the same process is output as it is, and the color conversion process for the basic image is preferentially performed in different processes. It is configured as follows.

FIG. 66 is a block diagram of a line memory used in the conventional example , where 808a to 808 (n-1) are registers, 809 is a circuit board, D0in to D (n-1) in are data inputs, and D0out. D (n-1) out is a data output, CLK is a clock, RDCLK is a read clock, WRCLK
Is a write clock, WE is a write enable input, R
E is a read enable input, LSYNC is a synchronization signal, R
STW is reset write input, RSTR is reset write
Read input and Data are input data. As shown in FIG. 66, the 1-bit input data is
The clock is delayed to make the data input D0in, and the data output D0in
0out is delayed by one clock by the register 808b to be input data D1in. A similar connection is made to the input data D (n-1) i
By repeating the process up to n, the output of the line memory is shifted by 45 degrees with respect to the input data and taken out.

FIG. 67 is a circuit diagram showing a main configuration of an image processing section of a color image processing apparatus according to this conventional example.
35a, 835b, and 835c are selectors, 810 is a register, 811, 812, 813, 814, and 815 are ORs
Circuits, 816, 836, 837, 838 are AND circuits,
817 is an inverting circuit.

As shown in the figure, OUTPUT in FIG.
, Selectors 835a, 835b, 835c are provided, the output terminal of register 810 is connected to the selection terminals of selectors 835a, 835b, 835c, and control data is input to register 810 by write strobe signal LTO. Have been.

The output terminals of the selectors 835a, 835b, 835c are connected to the input terminal of an OR circuit 812,
An output terminal of the circuit 812 is connected to one input terminal of the AND circuit 816. The output terminal of the OR circuit 811 to which the input data of each color is input is connected to the other input terminal of the AND circuit 816 via the inversion circuit 817. Also, the output signal of the selector 835a and the inverting circuit 81
7, an AND circuit 837 to which the output signal of the selector 835b and the output signal of the inverting circuit 817 are input, and an output signal of the selector 835c and an output signal of the inverting circuit 817. AND
A circuit 838 is provided.

Further, three OR circuits 813, 814, 8
The OR circuit 813 receives yellow (Y) (or blue (B)) input data and the output signal of the AND circuit 836, and the OR circuit 814 receives magenta (M) (or green (G)) input data. The data and the output signal of the AND circuit 837 are input to the OR circuit 815, and the input data of cyan (C) (or red (R)) and the output signal of the AND circuit 838 are input to the OR circuit 815.

FIG. 68 is a circuit diagram showing a configuration of a main part of the coloring processing unit, which includes 818a, 818b, 818c, and 818.
d, 818e, 818f, 818g are registers, 820
a, 820b, 820c, 820d, 820e, 820
f is a selector, 821a, 812b, 812c are selectors, 822, 823, 824, 825, 826, 827
Is an OR circuit, and 828 is a NOR circuit.

As shown in FIG. 68, registers 818a to 818g are connected to the CPU bus,
The output terminal of the selector 18a is connected to the selector 820a to the selector 820.
f is connected to the A terminal. The output terminals of the registers 818b to 818g are connected to the B terminals of the selectors 820a to 820f, respectively.
a and the output terminal of the selector 820b are connected to the selector 821.
The terminal A is connected to the terminal A and the terminal B, respectively.

Similarly, the output terminals of the selector 820c and the selector 820d are connected to the A terminal and the B terminal of the selector 821b, respectively, and the output terminals of the selector 820e and the selector 820f are connected to the A terminal of the selector 821c.
Terminal and the B terminal.

The control signal from the register 818a and the control signal shown in FIG.
The output terminal of the OR circuit 823 to which the output signal of the OR circuit 813 is input is connected to the selection terminal of the selector 820a.
An output terminal of the OR circuit 822 to which the output signal of the circuit 23 is input is connected to a selection terminal of the selector 820b.

The control signal from the register 818a and FIG.
The output terminals of the OR circuit 825 and the OR circuit 824 to which the output signal of the seventh OR circuit 814 is input are connected to the selection terminal of the selector 220c and the selection terminal of the selector 220d, respectively. Similarly, the OR circuit 827 and the OR circuit 826, to which the control signal from the register 818a and the output signal of the OR circuit 815 in FIG. 67 are input, are connected to the selection terminal of the selector 820e and the selector 820f, respectively.
Is connected to the selection terminal.

The output terminal of the OR circuit 811 in FIG. 67 is connected to the selection terminals of the selectors 821a, 821b, 821c and one input terminal of the NOR circuit 828, and the output terminal of the AND circuit 816 in FIG. 828
Is connected to the other input terminal.

To the registers 818b, 818d, and 818f, conversion color data for performing the above-described basic image color conversion processing (processing 1) is set and input by the write strobe signals LT1, LT3, and LT5, respectively. , And the registers 818e and 818g, the converted color data corresponding to the above-described sub-image processing (processing 2) is set and input by the write strobe signals LT2, LT4, and LT6, respectively.

Control data is set and input to the register 818a by the write strobe signal LT0.
8a outputs a control signal to perform an operation corresponding to 7-color mode and color conversion of a designated color, "0" data at the time of YMC subtractive color mixture at high density, and "1" data at the time of BGR additive color mixture. It is configured.

Next, the operation of this conventional example will be described.

When the image sensor of the image reading unit 801 reads a color original image as an original, a YMC system or a BG
The color data separated into the three primary colors of the R system is binarized based on the threshold value, and the respective line memories 804
a, 804b, and 804c are stored for n-1 lines.

In a color conversion process (process 1) for forming an image on a basic image corresponding to a color image of a document, color data of three primary colors is directly extracted via an OR circuit 811 and processed. This processing 1 is performed when any one of Y (or B), M (or G), and C (or R) color data is detected.

When this processing 1 is performed, the output signal of the inverting circuit 17 becomes "0", so that the AND circuits 816, 83
The output signals 6,837,838 become "0", and the additional formation processing (processing 2) of the sub-image (shadow part) is not performed. The process 2 is performed by extracting output data from the above-described line memories 804a, 804b, and 804c by shifting the input data by 45 degrees when the process 1 is not performed.

In that case, the write strobe signal LT
According to the output signal of the register 810 controlled by O, any one line of the selectors 835a, 835b, 835c is selected, and the process 2 is performed.

In the above processing 1 and processing 2, O
Through the R circuits 813, 814, and 815, Y
(Or B) data, M (or G) data, C
(Or R) data is the OR circuit 822, 8 in FIG.
23, OR circuits 824, 825, OR circuits 826, 82
7, respectively.

In the high density state where B, G, and R are all detected, the OR circuit 811 and the OR circuit 8 shown in FIG.
The output signal of No. 12 becomes "0".

In the state where the processing 1 is performed, the logical value of the signal of the selection terminal of the selectors 821a, 821b and 821c in FIG.
b and 821c select and take in the input from the A terminal. At this time, the OR circuits 813, 814, and FIG.
When the output signal of 815 is 1, the selectors 820a to 820f take in the input from the B terminal.

Therefore, in the process 1, the selectors 821a, 821b, 821b, 821b, 821b, 821b, 821b, 821b,
Color data is obtained from 821c.

Similarly, in the state where the processing 2 is being performed, the selectors 821a, 821b, and 821c take in the input from the B terminal, so that the write strobe signal LT
2, LT4, and LT6, color data is obtained from the selectors 821a, 821b, and 821c based on the converted color data.

These color data are stored in the image recording unit 8 shown in FIG.
03, and the image recording unit 803 forms a color image of the basic image and the sub-image (shadow portion) to which the respective conversion colors are added.

When the designated color is selected by the control data LT0, the control signal from the register 818a, OR
Circuits 822, 824, 826 or OR circuits 823, 8
By setting the inputs of 25 and 827 to “1”, the designated color is colored instead of the seven-color mode. Further, the aforementioned O
Output signals of R circuit 811 and OR circuit 812 are “0”
Then, a control signal for performing processing corresponding to "0" data at the time of YMC subtractive color mixture and "1" data at the time of BGR additive color mixture is output from the register 818a, and becomes a selection signal of the selector 807 in FIG. When stopped, color data of the document is output. A select signal indicating the operation state of the processing 1 or the processing 2 is output from the NOR circuit 828.
Is output to indicate the operation time and the stop time.

FIG. 69 is a view for explaining the operation of this conventional example, in which 830 is a color original image, 831 is a color image formed in a seven-color mode, 832 is a color image formed in a designated color mode, and 833 is a basic image. Image, 834 is a shadow part (sub-image)
It is.

As shown in the figure, the character of color R1 and the color G1
Are connected at the ends. In the color original image 830 of the color R1 + G1 at the connection portion, the character of the color R2 and the character of the color G2 are connected at an end. In addition, the basic image 833 of the connection portion at the color R2 + G2, the character of the color R3, and the character of the color G3 are connected at the end. As a result, an image is formed on the color image 831 having the shadow portion 834 of the color R3 + G3 at the connection portion.

Further, in the image formation in the designated color mode, the same color original image 830 is formed by connecting the character of the color R4 and the character of the color G4 at the end, and the basic image 8 of the color R4 + G4 at the connection portion.
33 and a shaded portion 834 of the designated color P
32 is formed.

As described above, according to this example, one of the color conversion processing (processing 1) for forming the basic image and the addition forming processing (processing 2) for the shadow portion (sub-image) is performed in the color superimposition processing. , And the color image is formed by adding a shadow portion to the color image.

In this example, the configuration of the apparatus is simple and can be easily operated, and colors are selected in a seven-color mode or a designated color mode. For example, processing 1 is a bright seven-color mode, and processing 2 is a dark seven-color mode. Thus, a color image of a desired color can be formed.

In the above example, a case has been described in which a shadow portion is additionally formed as a sub-image on a basic image. However, a base pattern can be additionally formed on a basic image, for example. Further, in the designated color mode, the case where the shadow portion is formed with the designated color has been described. However, for example, the basic image and the shadow portion may be formed with different designated colors.

As described above, processing can be performed so as not to cause color inconsistency in shadowing, but other processing has been desired.

The present invention has been made in view of such a technical background, and a major object of the present invention is to provide a color original when performing image processing on a color original and performing image processing such as shadowing and hollowing. Is to provide an image processing apparatus that can appropriately perform the image processing.

Another object of the present invention is to provide another image processing apparatus capable of adding a color-consistent shadow of each color component to a color image in a predetermined direction.

Still another object is to provide an image processing apparatus capable of producing a hollow image without color inconsistency.

Still another object of the present invention is to provide an image processing apparatus capable of performing a blanking and a shadowing process in a superimposed manner without causing color inconsistency.

[0062]

An object of the present invention is to provide an image processing apparatus for performing color image processing, comprising: separating means for separating an input color image into color components; A hollowing-out processing means for performing hollowing-out processing using thickening data and thinning-out data, and an image for each color component subjected to hollowing-out processing by the hollowing-out means corresponding to a shift amount with respect to a color image to be inputted. Drool
A combining means for combining at a position shifted by the amount, and referring to the color of the input color image with respect to the image combined by the combining means , for each color component.
This is achieved by a first means comprising a coloring means for coloring the image with the same color .

[0063]

[0064]

[0065]

In the first means, an input color image is decomposed for each color component, and fattening data is obtained for each decomposed color component.
Using the thinning data, perform the centering process, and apply the centered image for each color component to the input color image.
The images are combined at a position shifted by a shift amount corresponding to the shift amount , and the synthesized image is colored with the same color as the input color image for each color division component with reference to the color of the input color image. /> As a result, a processed image without color inconsistency can be obtained.

[0066]

[0067]

[0068]

[0069]

[0070]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is an explanatory diagram of the image processing in the first embodiment.
Are the same as those shown in the block diagram shown in FIG. 2, and the same reference numerals are given to the respective units which can be regarded as the same, and the duplicate description will be omitted.

In the figure, line memories 114R, 114G, 11 for R (red), G (green), and B (blue) are provided for the image processing unit 113.
4B and R, G, and B colored portions 115R and 115, respectively.
G and 115B are connected.

The image processing section 113 receives the binary data read by the image reading section and binarized by the binarizing means with reference to the threshold value, and is input to the line memories 114R and 114R.
Data is taken in from 4G and 114B.

In the embodiment, a shadowing process for forming a shadow corresponding to each color on a color image 45 degrees to the lower right is performed. The image processing unit 113 performs the shadowing process. The processing data from the image processing unit 113 is stored in the line memories 114R, 114G, 114B and the coloring units 115R,
115G, 115B, and binary data of R, G, B are also input to these coloring sections 115R, 115G, 115B.

As described above, the coloring process is performed on the processed data and the binary data, and the image data is overwritten, and the shadowing process on the image is performed.

FIG. 2 is an explanatory diagram of a line memory according to the embodiment. As a memory device, NEC μPD42505C is used.
Is used. This memory device has 5048 words x
8-bit First In First Out
(FIFO) structure, and (n + 1) bi one line before
It holds t data.

FIGS. 3 to 5 show image processing circuits corresponding to respective colors of the embodiment.

Since the image processing circuit for each color has the same configuration except for the input terminal position of the binary data for each color, the image processing circuit for R shown in FIG. 3 will be described below. In the embodiment, a system for handling complementary color components is used for all of the R, G, and B systems.

In FIG. 3, the shadow selector 150 includes a shadowed sub-data register 160 and an all-zero data register 1.
70 and the output of the decrement arithmetic unit 171 are input, and the output of the shadow selector 150 is input to the delay register 173. The CPU bus is input to the shadow width register 160, and the pulse LTO is input to its clock terminal. The output of the delay register 173 is input to the line memory 114R, and the reference clock CLK is input to the clock terminal of the delay register 173. On the other hand, the aforementioned decrement operation unit 17
1 and the shadow detection comparator 172 have the line memory 114R
The output of the decrement operation unit 171 is input to one of the AND circuits 120, and the shadow detection comparator 172 outputs
Each of them is inputted to one of the D circuits 121. The NOR circuit 122 receives binary data B, G, and R via inverting circuits 123B, 123G, and 123R, respectively, and outputs the output of the NOR circuit 122 to the AND circuit 12.
1 and input to the other of the AND circuit 120.

The output terminal of the AND circuit 120 is
Connected to the S1 terminal of the shadow selector 150, the binary data R
Is input to the S2 terminal of the shadow selector 150 via the inverting circuit 123R.

In the image processing circuit for G shown in FIG.
Instead of the binary data R in FIG. 3, binary data G is input to the S2 terminal of the shadow selector 150 via the inverting circuit 123G, and the other configuration is the same as that in FIG.

In the image processing circuit for B shown in FIG.
Instead of the binary data R of FIG. 3, binary data B is input to the S2 terminal of the shadow selector 150 via the inverting circuit 123B, and the configuration of other parts is the same as that of FIG.

FIG. 6 shows a color combining circuit according to the embodiment, in which 160C and 161 are data registers and 162
Is a control register, 170C is a color conversion selector, 171C
Is a shaded selector, and 172C is a processing selector.

As shown in FIG.
C, 161 and the input terminal of the control register 162
The PU bus is connected, and the data registers 160C and 161 are connected.
The strobe signals LT0, LT1, and LT2 are input to pulse terminals of the control register 162, respectively. The output terminals of the data registers 160C and 161 are respectively a color conversion selector 170C and a shaded selector 171C.
, And the output terminal of the color conversion selector 170C is connected to the data terminal of the shadow selector 171C.
The output terminal of the shaded selector 171C is the processing selector 172.
It is connected to the input terminal of C. Color conversion selector 170
Image data is input to C and the data terminal of the processing selector 172.

The control register 162 is connected to one input terminal of the AND circuit 125, the mode selector 173C and the processing selector 172C, and the output terminal of the OR circuit 126 is connected to the other input terminal of the AND circuit 125. I have. Further, the mode selector 173C is connected to the processing selector 172C, and the output terminal of the OR circuit 127 is connected to the shaded selector 171C.

The output signals of the inverting circuits 123R, 123G, 123B and the output signal of the AND circuit 121 of the image processing circuit shown in FIGS. 3 to 5 are respectively selected by the OR circuits 126, 127 and the mode selector 173C. Is entered. The signal MASK2X input to the mode selector 173C is a signal corresponding to each color.

Next, the operation of the embodiment will be described.

In the image processing circuit for R shown in FIG. 3, the value of the shadow width is set in the shadow width data register 160 to fetch the binary data R, G, and B, and the previous line is read from the line memory 114R. Data is taken in. When the binary data R is "L", the inversion circuit 123R
Is "H", the signal MASK1R is "H", the signal of the terminal S1 of the shadow selector 150 is "L",
The signal at the terminal S2 becomes "H". Therefore, the shadow selector 150 selects the data from the shadow width data register 160, the data is delayed by one clock in the delay register 173, and is input to the line memory R, and after one line, the data is transferred to the line memory R (114R). , The data shifted by 45 ° to the lower right is obtained. At this time,
The logical value of the signal output to the coloring composition circuit is MASK1R
Becomes "H" and MASK2R becomes "L". Binary data R
Is "H", B is "H", and G is "H", the data of the line memory 114R is decremented by 1 by the decrement calculator 171. If the data of the line memory 114R is other than 0, the data is Is output to the line memory 114R via the shadow selector 150 and the delay register 173.

When the data in the line memory 114R is 0, the data in the all-zero data register 170 is output to the line memory 114R via the shadow selector 150 and the delay register 173.

At this time, if the data of the line memory R is other than 0, the output signal of the shadow detection comparator 172 becomes “H”, and in this case, the NOR circuit 122 Is high, the signal MASK2R is high. When the data in the line memory R is 0, the signal MASK2R becomes "L".
Becomes Further, since the output signal of the inverting circuit 123R becomes "L", the signal MASK1R in this case becomes "L".

When the binary data is other than the above two cases, 0 data is output to the line memory R because a color component other than R exists. In this case, the signal MA
The signal SK1R becomes "L" and the signal MASK2R also becomes "L".

Such processing is similarly repeated for the color components G and B.

FIG. 7 is an explanatory diagram of the shadowing process according to the embodiment.
Y (yellow), M by the shadowing process already described
For each of the (magenta) and C (cyan) color components, a shadow 130a is formed in the Y color component 104a, a shadow 130b is formed in the M color component 104b, and a shadow 130c is formed in the C color component 104c. The state of the line memory at this time is shown in FIG.
It looks like a shadow.

In FIG. 6, data registers 160C,
The color data is set in 161 and the control register 162 causes the color conversion selector 170C to select the image data or the color data from the data register 160C.
In response to this, the process of the mode selector 173C is changed by the control register 162. In addition, whether or not the entire circuit is operated is selected by the control line of the processing selector 172C. When the circuit OFF state is set by the processing selector 172C, image data is output via the processing selector 172C.

When the circuit is ON, the color conversion selector 170
C is a signal MASK2R for the colored R selected by the image data.
Is "H", the erase data (all 1) is output. When the signal MASK2R is “L” and the signal MASK2R is “L”,
When 2G is “H”, the data of the data register 161 is output.

When the signals MASK2R and MASK2G are "L" and the signal MASK2B is "H", the data of the data register 161 is output. Also, the signal M
ASK2R, signal MASK2G and signal MASK2B
Is "L", image data is output.

When the circuit is ON, the color conversion selector 170
C is a signal MASK2 in the colored R selected by the color data.
Except when R, signal MASK2G and signal MASK2B are all “L”, the above-described color conversion selector 170
This is the same as when C selects image data. further,
When the signal MASK1R is “H”, the signals MASK2B and M
When ASK2RG and signal MASK2RB are at "L", erase data (all 1) is output. When the signal MASK1R is at "L", the signal MASK1G is at "H", and the signals MASK2R, MASK2G and MASK2B are at "L", the data register 1
60C data is output.

In this case, the signals MASK1R,
When the signal MASK1G is "L", the signal MASK1B is "H", and the signals MASK2R, MASK2G and MASK2B are "L", the data register 1
60C data is output. Then, the signal MASK1
R, signal MASK1G and signal MASK1B are "L"
And the signals MASK2R, MASK2G and M
When ASK2B is "L", image data is output.

The mode selector 173C also has a function of restoring the complementary color component.

FIGS. 8 to 10 are explanatory diagrams of image processing in the embodiment. FIG. 9 shows a case where the color conversion selector 170C selects image data with respect to the original image shown in FIG. 8, and original data is output to portions other than the color data. FIG. 10 shows a case where the color conversion selector 170C selects color data.

As described above, according to the embodiment, the interference of the colors of the shadows is prevented, and the shadows of the colors corresponding to the respective color components are formed on the image.
Image processing added in the lower right 45 ° direction can be performed in real time.

Although the embodiment has been described with respect to the case where the shadowing process is performed in the lower right direction of the image at 45 °, the present invention is not limited to the embodiment, and may be applied in the lower right direction of the image or in other directions. Shadowing can be performed at other angles.

As described above, according to the above-described embodiment, an image to which a color corresponding to each color component is added to a color image without any color interference in a predetermined direction of each color component and without a sense of color discomfort. Processing can be performed in real time.

[Second Embodiment] Next, a second embodiment will be described.

In the second embodiment as well, the schematic configuration of the image processing apparatus is the same as that shown in FIG. 64, and the same components are denoted by the same reference characters, and redundant description will be omitted.

FIG. 11 is a block diagram showing the structure of the image reading unit 801 and the image processing unit 802. As shown in FIG. 11, the image reading unit 801 has a line memory 208R to which binary data of each color is input. , 208G, and 208B are connected to an image processing circuit 209 of the image processing unit 802, and the image processing circuit 209 has coloring circuits 210R and 210R.
10G and 210B are connected.

FIG. 3 shows the line memories 208R and 208.
G, 208B (generally indicated by reference numeral 208) is a terminal connection diagram showing a configuration of a NEC μP as a memory device.
D42505C is used. As shown in the figure,
Binary data obtained by binarizing image data (line memory 20
In the case of 8R, the binary data R) is used as a complementary color component, 1-bit input data is input to the terminal D0in, and the output signal of the terminal D0out is input to the terminal D1in. Such a connection is made to terminal D
By repeating the process up to n-1, the output signal from the line memory 8 includes (n-1) lines of data.

By providing such a line memory 208 for each of the colors R, G, and B, multivalued image data of a color image is read.

FIG. 13 shows a control register used in the image processing circuit 209. The control register 290 outputs a setting signal W for setting the amount of thinning or thickening of data.
P and mode selectors 256, 257 (to be described later) (FIG. 1)
4) The select signal MP is output.

FIGS. 14 to 16 show details of the image processing circuit 209 for each color red (R), green (G), and blue (B).
42 is a shift register, 250 and 253 are thinning amount selectors, 251 and 254 are thickening amount selectors, and 252 and 2
55 is a shift amount selector, and 256 and 257 are mode selectors.

Note that since the image processing circuit configuration itself is the same for each of these colors, the following description will be made exemplifying red (R).

The line memory 208R (208G, 208
The data from B) is m (2m +
1) AND circuits 211a, 211b... The output terminals of these AND circuits are connected to the input terminals of the contraction amount selector 250, and the output terminals of the contraction amount selector 250 are connected to the input terminals of the shift register 240.

The output of the shift register 240 is (2m +
1) AND circuits 212a, 212b... The output terminals of these AND circuits are connected to the input terminals of the contraction amount selector 253. The output terminals of the contraction amount selector 253 are connected to the output terminals of the AND circuit 214 via the mode selectors 256, 257 and the inversion circuit 213. Connected to one input terminal.

Similarly, the line memory 208R (20
8G, 208B) are input to (2n + 1) OR circuits 215a, 215b,..., Where n is the amount to be fattened. The output terminals of these OR circuits are connected to the input terminals of the fat amount selector 251, and the output terminals of the fat amount selector 251 are connected to the input terminals of the shift register 241.

The output terminal of the shift register 241 is (2n
+1) OR circuits 216a, 216b... The output terminals of these OR circuits are connected to the input terminals of the fat amount selector 254, and the fat amount selector 25
4 is connected to the other input terminal of the AND circuit 214.

The line memory 208R (208G, 208
The data from B) is input to the input terminal of the shift amount selector 252, and the shift register 252 is connected to the shift amount selector 252. Furthermore, shift register 2
The output terminal of the shift amount selector 255 is connected to the input terminal of the shift amount selector 255, and the output terminal of the shift amount selector 255 is connected to the mode selectors 256 and 257.

Setting signal WP of control register 290 described above
Are thinning amount selectors 250 and 253, thickening amount selectors 251 and 254, and shift amount selectors 252 and 25.
5 and the select signal MP is supplied to the mode selector 25.
6 and 257, and the mode selectors 256 and 257 store the corrected blank data in NMASKR (NMASKG, NM
ASKB) is input.

The thinning amount selector 250 selects an arbitrary line from the thinning data, sets the thinning amount in the line direction (sub-scanning direction), and sets the thinning amount selector 253.
Thus, any one line of the thinning data is selected, and the thinning amount in the main scanning direction is set. Also, an arbitrary one line of the fat data is selected by the fat amount selector 251 and the fat amount in the line direction (sub-scanning direction) is set, and the fat amount selector 254 sets the fat amount of the fat data. An arbitrary one line is selected, and a thickening amount in the main scanning direction is set. Since a shift occurs in the binary data during such processing, the shift amount selector 252 and the shift register 24
The shift generated in the binary data is corrected by the 2 and shift amount selector 205.

In this manner, the thinning amount selector 253
Is obtained as an output signal, and is selected by the mode selectors 256 and 257 and output to the coloring circuit.
Also, fat data is obtained as an output signal of the fat amount selector 254, and the logical product of the fat data and the thinned data inverted by the AND circuit 214 is obtained.
R (WMASKG, WMASKB) is obtained. Then, as the output signal of the shift amount selector 255, the shift correction data SMASKR (SMASKG, SMASKB)
Is obtained.

FIG. 17 shows a correction circuit. The hollow signals WMASKR, WMASKG, WMASKB of each color are input to the OR circuit 220, and the output signal of the OR circuit 220 and the deviation correction data SMASKR, SMASKG, SMA of each color.
The logical product with the SKB is determined by AND circuits 221R, 221G,
NMAS obtained and corrected in 221B
KR, NMASKG, NMAKB are obtained.

FIGS. 18A and 18B are explanatory diagrams of thinned data, thickened data, shift correction data, and hollow data. FIG. 18A shows original image data, and FIGS. , Thickening data, deviation correction data, and hollow data.

FIG. 19 shows a coloring circuit.
C and 241C are data registers, 242C is a control register, 250C is a color conversion selector, 251C is a contour selector, 252C is a process selection selector, 253C and 254C.
Is a mode selector.

As shown in FIG. 19, the CPU bus is connected to the input terminals of data registers 240C and 241C and the input terminal of control register 242C.
The color data is the write strobe signal L at 0C and 241C.
The control data is set by the write strobe signal LT2 in the control register 242C.

The output terminal of the data register 240C has
The color conversion selector 250C is connected, and the color conversion selector 2
A contour selector 251C is connected to the output terminal of the data register 24C.
1C is connected to the output terminal, and the output terminal of the contour selector 251C is connected to the processing selection selector 252C.

The output terminals of the control register 142C are a color conversion selector 250C, mode selectors 253C and 254C.
And the processing selection selector 252C, and the output terminals of the mode selectors 253C and 254C are connected to the contour selector 2
51C and the process selection selector 252C.
The mode selectors 253C and 254C are provided with the inverted mode selectors 256 and 257 for each color.
Are output, and the control register 242C controls whether the color conversion selector 250C selects image data or color data, and also controls the change of the processing of the mode selectors 253C and 254C. Is performed.

The data input signal to the processing selection selector 252C is all 1 (positive) all 0 in the erase area.
In response to (negative), the control line determines whether to operate the entire circuit or not.

When the circuit is turned off, the processing selection selector 252C selects image data. When the circuit is on, the processing selection selector 252C responds to ON and OFF of the mode selectors 253C and 254, and Data is selected as shown in FIG.

Table 1 Mode selector 253C Mode selector 254C Selection data ON ON Color conversion selector ON OFF Data of 250C Erase data OFF ON Data register OFF OFF Data of 241C Erase data Also, the processing contents of the mode selector 253C are the color conversion selector 250C When the color conversion selector 250C outputs the color data of the data register 240C, the output of the mode selector 253C becomes MASK1X. When the color conversion selector 250C outputs image data, the output of the mode selector 253C becomes MASK1R,
The logical sum of three inputs MASK1G and MASK1B.

Similarly, the processing contents of the mode selector 254C differ depending on the output of the color conversion selector 250C.
When the color conversion selector 250C outputs the color data of the data register 240C, the output of the mode selector 254C becomes the output of the NOR circuit that receives MASK1X and MASK2X. When the color conversion selector 250C outputs the image data, the output of the mode selector 254C becomes (MASK1R OR MASK1G OR MASK
1B) A logical operation expression represented by OR / MASK2X is obtained. (Note that / is used here as an inversion code.) The mode selector 25
At 4C, the complementary color component is restored.

FIG. 20 is an explanatory diagram of the image processing in the second embodiment. As described above, the image data of the image 230 of the original is read in FIG. 11A, and each color component, that is, the C component 230 is read as shown in FIG.
a, an M component 230b and a Y component 230c. And, as shown in FIG.
C component 231a, M
After forming a component 231b and a Y component 231c, and combining these components as shown in FIG. 4 (d), coloring is performed by referring to the color of FIG. 4 (a) as shown in FIG. 4 (e). I do.

FIG. 21 is an explanatory diagram of another image processing in this embodiment. In FIG. 21A, the image data of the image 230 is read, and as shown in FIG.
And the Y component 230c. Next, as shown in FIG. 3C, each component is subjected to a hollowing process using thickening and thinning to form a C component 231a and a Y component 231c, and as shown in FIG. After these components are synthesized as described above, coloring is performed with reference to the colors shown in FIG.

FIG. 22 is an explanatory diagram of the processed image formed in this embodiment. In contrast to the original image 235 shown in FIG. 22A, when the processed image 236 shown in FIG. The output of conversion selector 250C is image data and signal MA
SK1X is a thinning signal, and signal MASK2X is a hollow signal. When the processed image 237 shown in FIG. 9C is created, the output of the color conversion selector 250C is color data.
The signal MASK1X is a thinning signal, and the signal MASK2X is one of a hollow signal and a shift correction signal. When the processed image 238 shown in FIG. 9D is created, the output of the color conversion selector 250C is image data and the signal MASK1X
And the signal MASK2X are both thinned signals.
When the processed image 239 shown in FIG. 9E is created, the output of the color conversion selector 250C is color data and the signal MASK1
Both X and the signal MASK2X are hollow signals.

In FIGS. 22 (b) and 22 (d), an image which is not binarized is also output to the binarized image area of each color, and becomes the data of the image 235 of FIG. 22 (a).

Here, the colors of the centering-processed image and the thinning-processed image are selected from seven colors of R, G, B, C, M, Y, and BK, and seven colors can be colored.

As described above, in the second embodiment, the inconsistency in color when the centering process and the thinning process are performed independently for each color is described.
The problem can be solved by performing the fattening process and the hollowing-out synthesizing process of each color component.

Further, according to the second embodiment, the blanking process of a color original (character logo) is performed in color units (Y, M, C, B).
K, R, G, B).

[Third Embodiment] FIG. 23 is a block diagram showing a configuration of an image reading unit and an image processing unit according to a third embodiment. In FIG. 23, the same parts as those in FIG. ing.

FIG. 24 is a terminal connection diagram showing the structure of a first line memory in the third embodiment. An NEC μPD42505C is used as a memory device, and binary data R, G, B obtained by binarizing image data are used. Then, 1-bit input data is input to the terminal D0in by setting the components other than the white component to "H".

This first line memory is used as the line memory 208K of FIG. 23, and the connections and operations between the other terminals are the same as those of the line memory already described with reference to FIG.

FIG. 25 is a terminal connection diagram showing the configuration of a second line memory according to this embodiment. An NEC μPD42505C is used as a memory device, and binary data R obtained by binarizing image data (for the line memory 208R). ) Are input as 1-bit input data. This second line memory is a line memory 208R,
The connections and operations between the other terminals are the same as those of the line memory already described with reference to FIG.

FIG. 26 shows an image processing circuit in this embodiment, and the same parts as those in FIG. 14 described above are denoted by the same reference numerals.

As shown in FIG. 26, in this image processing circuit, a thickening amount processing circuit portion is removed from the circuit of FIG. 14, and a shift amount selector 25 for each color binary data R, G, B.
5a, 253a and 254a are provided. The shift register 245 is connected to the shift amount selector 255a, and the output terminal of the shift register 245 is connected to the shift amount selector 256. Shift amount selector 253a
Is connected to the shift register 243, the shift amount selector 258 is connected to the output terminal of the shift register 253, the shift amount selector 254a is connected to the shift register 244, and the shift amount selector 259 is connected to the output of the shift register 244. Terminal is connected.

The output terminal of the thinning amount selector 253 as in FIG. 14 is connected to one input terminal of the AND circuit 214 via the inverting circuit 213, and the output terminal of the shift amount selector 255 as in FIG. It is connected to the other input terminal of the circuit 214.

The output terminal of the shift amount selector 256 is AN
One input terminal of the D circuits 240 and 241 and the output terminal of the shift amount selector 258 are connected to the AND circuits 242 and 24, respectively.
3 is further provided with a shift amount selector 259.
Are connected to one input terminals of AND circuits 244 and 245, respectively.

The output terminal of the contraction amount selector 253 is connected to the other input terminal of the AND circuits 240, 242, 244, and the output terminal of the AND circuit 214 is connected to the AND circuit 241, 241.
243 and 245 are respectively connected to the other input terminals.

The output terminal of the shift amount selector 256 and AN
The output terminals of the D circuits 240 and 241 are connected to the mode selector 26.
0, the output terminal of the shift amount selector 258 and A
The output terminals of the ND circuits 242 and 243 are the mode selector 2
The output terminal of the shift amount selector 259 and the output terminals of the AND circuits 244 and 245 are connected to the mode selector 262.

The control register 290 includes shift amount selectors 255a, 253a, 254a, 252, a thinning amount selector 250, shift amount selectors 256, 258,
259, thinning amount selector 253, shift amount selector 2
55, and are connected to the mode selectors 260, 261, and 262.

The other parts of the configuration of the third embodiment are the same as those of the second embodiment already described.

In FIG. 26, shift amount selector 25
6, 258, 259 output signals SMASKR, SMAS
KG, SMAKB deviation correction data, AND circuit 24
0, 242, 244 output signals HMASKR, HMAS
KG, HMAKB are thinned data, AND circuit 24
1, 243, 245 output signals WMASKR, WMAS
KG and WMASKB are hollow data.

Also in the third embodiment, image processing is performed in the same manner as described with reference to FIG.

FIGS. 27 (a) and 27 (b) are explanatory diagrams of thinning data, hollow data and shift correction data in the third embodiment. FIG. 27 (a) shows original image data, and FIGS. These are data, hollow data, and deviation correction data.

In the third embodiment, FIG.
Coloring is performed by the same coloring circuit as in the second embodiment described in FIG.

The coloring operation according to the third embodiment is performed in exactly the same manner as the coloring operation according to the second embodiment described above, and a duplicate description will be omitted.

FIG. 28 is an explanatory diagram of image processing in this embodiment. In FIG. 28A, image data of an original image 35 is read, and in FIG. 28B, binarization mask processing is performed. In (c), the blanking process is performed, and in (d) of FIG.
Coloring is performed with reference to the color of.

FIGS. 29 (a) to 29 (e) are explanatory views of the processed image formed in the embodiment. The processing shown in FIG. 29 (b) is performed on the original image 250 shown in FIG. 29 (a). When the image 251 is created, image data is output from the color conversion selector 250C in FIG. 19, the signal MASK1X is a narrowing signal, and the signal MASK1X is a hollow signal. Figure (c)
When the processed image 252 shown in FIG.
The output of 50C is color data, the signal MASK1X is a thinning signal, and the signal MASK2X is either a hollow signal or a shift correction signal.

When the processed image 253 shown in FIG. 29D is created, the output of the color conversion selector 250C is image data, and both the signals MASK1X and MASK2X are thinning signals. When the processed image 254 shown in FIG. 29E is created, the output of the color conversion selector 250C is color data, and both the signals MASK1X and MASK2X are hollow signals.

In FIGS. 29 (b) and 29 (d), a non-binarized image is also output to the binarized image area of each color, and becomes the data of the image 250 in FIG. 29 (a).

Here, the colors of the centered image and the thinned image are selected to be seven colors of R, G, B, C, M, Y, and BK, and seven colors can be colored.

As described above, in the third embodiment, the inconsistency in color when the centering process and the thinning process are performed independently for each color is described.
The problem can be solved by performing the blanking process after the binarizing process of the image with white and other colors.

According to the third embodiment, the blanking process of the original image can be easily performed, and the process is performed with reference to each color.
The frame processing and the medium filling processing (FIG. 29B) can be performed without deteriorating the gradation of characters and the like.

FIG. 30 is a circuit diagram showing another image processing circuit according to the third embodiment, which is set so that an output of a NAND gate is generated when there is no RGB output of Fifo. This eliminates the need for a line memory for white.
With this image processing circuit, it is possible to realize a modification of the third embodiment having the image reading unit and the image processing unit shown in FIG. 11, the line memory shown in FIG. 25, and the coloring circuit shown in FIG. is there. According to this modification, the capacity of the line memory can be reduced to 3/4.

As described above in detail, according to the second and third embodiments, the color inconsistency in the processed image obtained by performing the blanking process and the thinning process independently for each color is solved. Thus, it is possible to form a processed image having no unnaturalness in color from the original image.

[Fourth Embodiment] The fourth embodiment differs from the above-described second or third embodiment only in the way of processing, and therefore, the specific circuit configuration will be described. Is omitted. In this embodiment, as described as the invention according to the applicant's proposal, the hollowing-out process and the shadowing process are basically performed by forming a sub-image, and the order of each process is further changed. It is intended to obtain a different effect on the image formed by the change.

That is, in the first to third embodiments,
In each of the image processing of shadowing and hollowing, color inconsistency is not generated in the formed image. On the other hand, in the present embodiment, the image data input as shown in FIG.
After this processing is finished, shadowing is performed by the shadowing processing unit 302 and output as processed data, or the input image data is shadowed by the shadowing processing unit 302 as shown in FIG. After that, the blanking processing section 301
Performs a blanking process and outputs processed data.

More specifically, when the blanking process is performed first as shown in FIG. 31, the color components of the original image 330 shown in FIG. ,
Yellow (Y) 330a, yellow (Y) + magenta (M) component 33
0b and a magenta (M) component 330c, and are hollowed out in the same manner as in the processing of the second embodiment shown in FIGS. 20 and 21 (hollow-out color mode), and the color shown in FIG. Referring to the Y component 331a and the (Y + M) component 331b
And the M component 331c (FIG. 9B). In this case, if the processing shown in FIG. 69 described above, that is, the processing of adding shadows, is performed, the shadow portions become symbols 332a, 332b, and 332c, respectively (FIG. 69C). When the processing shown in FIG. 7 from FIG. 7B is performed, in other words, when the processing of adding a three-dimensional shadow is performed, the shadow portions are indicated by reference numerals 333a, 333b, and 333c, respectively (FIG. ).

On the other hand, in the same manner as the processing shown in FIG. 28 of the third embodiment from FIG. Y component 33
1a, the (Y + M) component 331b and the M component 331c are colored (FIG. 9E). Also in this case, when the above-described shadow shading process is performed, the shadows are denoted by reference numerals 334a, 334b,
334c (FIG. 3F). In addition, when the above-described three-dimensional shadowing process is performed from FIG. (E), the shadows are indicated by reference numerals 335a, 335b, and 335c (FIG. (G)). Note that, in these series of processes, reference numeral 3
The portions 31a, 331b, and 331c are colored by color data of Y, (Y + M) and M at the time of the blanking process, respectively, and reference numerals 332a, 333a, 334a, 335a,
332b, 333b, 334b, 335b, 3
The portions 32c, 333c, 334c, and 335c are colored by Y, (Y + M), and M color data, respectively, during the shadowing process.

On the other hand, when the shadowing process is first performed as shown in FIG. 32, the respective color components and Y component of the original image 340 shown in FIG. 340a, (Y + M) component 340b and M component 34
0a, and the above-mentioned shadow shading process is performed, the shadow portions are respectively referred to as the Y component 341 with reference to the color shown in FIG.
a, (Y + M) component 341b and M component 341c are colored (FIG. 9B). Then, when performing the blanking process in the blanking color mode described above, the blanking is performed,
Reference numerals 342a and 342 in which the original image and the shadow portion are colored
B, 342c, as shown in FIG. 3 (c), are contour areas for each of the colors Y, (Y + M), and M. Also, FIG.
When the image is hollowed out in the above-described hollowed-out white mode from the state in which the shadow is applied, the outline of the entire image remains, and the original image portions 340a, 340b, and 34 in FIG.
The portions 343a, 343b, and 343c corresponding to 0c and the shadow portions 341a, 341b, and 341c are colored Y, (Y + M), and M, respectively, with reference to each color of the original image 340.

On the other hand, when the above-described stereoscopic shadowing process is performed on the original image 340, the shadow portions are converted from the Y component 344a and the (Y + M) component 34 from the color shown in FIG.
4b and the M component 344c are colored (FIG. 9E). When the centering process is performed in the centering color mode described above, the centering is performed, and Y, (Y + M), and M are indicated by reference numerals 345a, 345b, and 345c in which the original image and the shadow portion are colored. An outline area is provided for each color (FIG. 9F). Further, when the image is hollowed out in the above-described hollow white mode from the state where the three-dimensional shadow is applied as shown in FIG. 3E, the outline of the entire image remains, and the original image portions 340a and 340b of FIG. , 340c and shadow 344
a, 344b, 344c corresponding to portions 346a, 34
6b and 346c are colored Y, (Y + M), and M, respectively, with reference to each color of the original image 340. Note that in these series of processes, reference numerals 341a, 341b, 341
The part c and the parts 344a, 344b, 344c are colored by the color data of Y, (Y + M) and M during the shadowing process, respectively, and the parts 342a, 343a,
335a, 336a, 342b, 343b, 345
b, 346b, 342c, 343c, 345c, 3
In the portion 46c, Y, (Y + M) and M
Is colored according to the color data.

As described above, for the original images 330 and 340, the processing order of the separate hollowing processing of the hollow color mode and the hollow white mode, and the processing order of the shadowing processing of the plane shadowing and the three-dimensional shadowing respectively. 33B, 33C, 33D, 33E, and 33E when combined with the processing mode.
(F), (g), FIGS. 34 (b), (c), (d),
As shown in (e), (f), and (g), different images are obtained. The selection of these images, in other words, the selection of image processing, is performed as shown in the block diagram of FIG.
Or the fifth five selectors 351, 352, 353,
The processing is performed by selecting the order and processing of the hollowing processing unit (circuit) 301 and the shadowing processing unit (circuit) 302 by 354 and 355 and processing the image data.

In this case, the first selector 351 selects the input of the hollowing process, the second selector 352 selects the output of the hollowing process, the third selector 353 selects the input of the shadowing process, and the fourth selector 353 selects the input of the shadowing process. The selector 354 is used for selecting the output of the shadow processing, and the fifth selector 355 is used for selecting the output of the processing. As a result, FIGS.
The processed image can be obtained by selecting the hollowing-out processing by the first selector 351 with respect to the input image data and selecting the fifth selector 355 by the second selector 352 and outputting the processed data. it can. Similarly, for the processed images in FIGS. 33 (c), (d), (f), and (g), the first selector 351 selects the blanking process,
This can be obtained by selecting shadowing processing by the second selector 352 and the third selector 353 and selecting the fifth selector 355 by the fourth selector 354 to output processing data. FIG.
For the processed images of (b) and (e), the third selector 353 selects the shadowing process for the image data, and the fourth selector 354 selects the fifth selector 355 to output the processed data. Can be obtained by
34 (c), (d), (f), and (g), the third selector 353 selects shadowing processing, and the fourth selector 354 selects the first selector 35.
1 can be obtained by selecting the blanking process by the first selector 351 and selecting the fifth selector 355 by the second selector 352.

Next, a description will be given of an operation method when these processes are actually performed.

These image processes are executed by selecting a menu on the operation / display unit of the copying machine. FIG.
It is a principal part enlarged plan view of the part related to menu selection of a display part. This menu is a so-called touch panel type in which transparent switch elements that are switched by lightly pressing are arranged in a matrix on the upper surface of the display surface. The menu includes a color processing key 361 and a create key 36, as shown on an initial screen 360 in FIG.
2, a move key 363, a Book erase key 364, a color selection key 365, and a scaling key 366 are set.

The structure of this menu will be described with reference to FIG. First, when the create key 362 is pressed from the initial screen 360 (FIG. 14A), a screen is displayed in which two keys, ie, a hollow key 367 and a shadow key 368, are displayed (FIG. 14B). FIG. 38 is an enlarged view of this. When the hollow key 367 is pressed from this state, FIG.
When the screen shown in FIG. 39) is pressed and the shadow key 368 is pressed, the screen shown in FIG.
The screen shown in FIG. 7D (enlarged view-FIG. 40) is displayed.

Here, on the screens shown in FIGS. 37 (c) and 39 (FIG. 39), the hollow shape is selected by the shape selection key 381, the width is selected by the width selection key 382, and the color is standardized by the color selection key 383. Select color and # key 369
When is pressed, the screen changes to a screen as shown in FIG. 37 (e) (enlarged view-FIG. 41). Note that the standard colors referred to here are such that the reddish color is light red, and the yellowish color is light yellow, so that the shadow is a color close to the original image of R, G, B, C, M, Y, K. It is something that I put on. Further, when the shape and width of the hollow area are selected by the shape selection key 381 and the width selection key 382, respectively, the designated color is selected by the color selection key 383, and the # key 369 is pressed.
(F) The screen changes to the one shown in (enlarged view-FIG. 42).
Here, the designated color means that all the shadows (sub-images) have the same color as described above with reference to FIG. For this designated color, the data of MASK2X of the mode selector 173C is ignored in FIG. 6, and when outputting the shadow data, the data of the data register 161 is output unconditionally to output the shadow data of any data. Becomes possible.

Screen 3 shown in FIG. 37 (f) and FIG. 42
At 60, a hollow color designation key 370 and a density setting key 371 for setting the color density appear. Then, when a hollow color is designated by the color designation key 370, the density is determined by the density setting key 371, and the # key 369 is pressed, the screen changes to that shown in FIG. 37 (g) (enlarged view-FIG. 43). In this screen, Figure 37
The mode selected in (c) is inverted between black and white, and FIG.
Displays the specified color. Then, if there is no change in this color, the user presses the create key 362, and FIG.
The screen changes to (enlarged view-FIG. 44). If the user wants to change it, he presses the # key 369 to return to FIG.

When the screen 360 is set to the standard color mode and the designated color mode as described above, the centering process is confirmed. That is, when there is no change in the hollow portions, when the create key 362 is pressed, the screen of FIG. 37 (e) becomes the screen of FIG. 37 (i) (enlarged view-FIG. 45), and the screen of FIG. j) (enlarged view-FIG. 46).
The details of the hollowing out process are displayed. To change the blanking, the user presses the # key 369 to call up the screen shown in FIG. 37B, and repeats the same operation to set a desired blanking condition.

When the shadowing screen 360 is called in FIG. 37 (d) to perform shadowing processing, the shadowing shape is selected by the shape selection key 372 on the screen of FIG. 37 (enlarged view-FIG. 40). Then, the width of the shadow is selected by the width selection key 373. Then, when the standard color is selected with the color selection key 374 and the # key 369 is pressed, the screen changes to that shown in FIG. 37 (k) (enlarged view-FIG. 47). On the other hand, select the designated color and # key 3
Pressing 69 changes the screen to that shown in FIG. 37 (l) (enlarged view-FIG. 48). On this screen 360, the color of the shadow is selected by the color selection key 370.
When the density of the color is selected by the density selection key 371, the screen changes to that shown in FIG. 37 (m) (enlarged view-FIG. 49). On this screen, the mode selected in FIG. 37 (l) is inverted between black and white, and the color specified on the screen in FIG. 37 (f) is displayed. When there is no change in the color of the shadow by this display, the create key 362 is depressed and the display shown in FIG.
(Enlarged view-FIG. 50) is called.

After the screen of FIG. 37 (k) and the screen of FIG. 37 (n) are obtained in this way, if there is no change in the selected image processing, the respective create key 362 is pressed. (O) (enlarged view-FIG. 51) from the screen, and (p) (enlarged view-
The screen changes to that shown in FIG. 52). Thus, in the case of FIG. (O) (FIG. 51), the standard color is 5 m in this example.
m is performed, and in the case of (p) (FIG. 52) in the figure, a 3 mm solid shadow is performed with the designated color. On the other hand, when a change is required, when the # key 369 is pressed, the screen shown in FIG. 37B is called, and a selection can be made again from the menu on this screen.

The menu structure shown in FIG. 37 is for the case where the hollowing or shadowing is executed alone, but the case where the hollowing and shadowing are combined as shown in FIGS. 33 and 34 described above. Is further processed by a menu as shown in FIGS. 53 and 54. That is, FIG. 53 shows a case in which hollowing is performed after shadowing is performed. In this example, the same screen as FIG.
(A) is displayed. When the create key 362 is pressed from this screen, FIG. 53 (b) (same as FIG. 37 (k))
Screen appears, and here is the key part 3 with a hollow display
When the user presses 91, the screen shown in FIG. 53C (same as FIG. 37C) appears, and further hollowing is selected for the shaded image. When, for example, a color mode is selected by the mode selection key 381 on this screen, the screen shown in FIG. 53D (enlarged view-FIG. 55) is called up. If this image setting is acceptable, the create key 362 is pressed, and the contents of the image processing are confirmed as shown in FIG. 53 (e) (enlarged view-FIG. 56).
To change the image processing settings, the user presses the # key 369 to return to the previous screen, redo the settings, and subsequently perform the same operation. Thus, the image processing as described with reference to FIG. 34 is performed.

On the other hand, FIG. 54 shows a menu screen in which shadowing is performed after hollowing out. In this menu, for example, in the color mode of FIG. 54 (a) (same as FIG. 37 (i)), from the state where the width is set to be hollowed out while leaving 1 mm in width, the create key 362 is pressed to
The screen of (b) (same as FIG. 37 (e)) is called, and a key portion 382 for selecting shadowing is pressed. As a result, shadowing is selected in the state where the above-mentioned hollowing is set, and the screen changes to FIG. 54 (c) (the same as FIG. 37 (d)). Therefore, the selection is made by pressing the key portion of the shadowing mode selection. In this case, a 5 mm wide standard color is selected as a shadow, and the screen changes as shown in FIG. 54 (d) (enlarged view-FIG. 57). If there is no change, if the create key 362 is pressed, the set processing contents are displayed as shown in FIG. 54 (e) (enlarged view-FIG. 58), and the contents of the image processing are confirmed. To change image processing settings, use the # key 3
Press 69 to return to the previous screen, redo the settings, and subsequently perform the same operation. Thus, the image processing as described with reference to FIG. 33 is performed.

In the above description, the shadowing mode (plain shadow or three-dimensional shadow), color mode (standard color or designated color), hollow mode (hollow color mode or hollow white mode), hollow mode and shadow mode Although only specific widths are illustrated for each of the widths, it is needless to say that these can be arbitrarily combined and various image processing can be executed.

[0182]

[Effect of the Invention] As apparent from the foregoing description, according to the present invention, mosquitoes performs image processing with respect to color document, the color development when performing image processing such as shading and hollowed properly It can be carried out.

[0183]

[0184]

[0185]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of image processing for explaining a first embodiment;

FIG. 2 is a terminal connection diagram of a line memory.

FIG. 3 is a circuit diagram illustrating an image processing circuit corresponding to an R color.

FIG. 4 is a circuit diagram showing an image processing circuit corresponding to G color.

FIG. 5 is a circuit diagram showing an image processing circuit corresponding to B color.

FIG. 6 is a circuit diagram showing a coloring synthesis circuit.

FIG. 7 is an explanatory diagram of a shadowing process.

FIG. 8 is an explanatory diagram of image processing for shadowing.

FIG. 9 is an explanatory diagram of image processing for shadowing.

FIG. 10 is an explanatory diagram of image processing of shadowing.

FIG. 11 is a block diagram schematically illustrating an image reading unit and an image processing unit for explaining a second embodiment;

FIG. 12 is a terminal connection diagram of the line memory.

FIG. 13 is an explanatory diagram of a control register of the image processing circuit.

FIG. 14 is a circuit diagram illustrating an R color image processing circuit.

FIG. 15 is a circuit diagram illustrating an image processing circuit for G color.

FIG. 16 is a circuit diagram showing an image processing circuit for B color.

FIG. 17 is a circuit diagram illustrating a correction circuit.

FIG. 18 is an explanatory diagram of thinning data, thickening data, shift correction data, and hollow data.

FIG. 19 is a circuit diagram showing a coloring circuit.

FIG. 20 is an explanatory diagram of image processing.

FIG. 21 is an explanatory diagram of image processing.

FIG. 22 is an explanatory diagram in a case where image processing is performed using a letter A as an original image.

FIG. 23 is a block diagram schematically illustrating an image reading unit and an image processing unit for explaining a third embodiment;

FIG. 24 is a terminal connection diagram of the line memory.

FIG. 25 is a terminal connection diagram of the line memory.

FIG. 26 is a circuit diagram illustrating an image processing circuit.

FIG. 27 is an explanatory diagram of thinning data, hollow data, and deviation correction data.

FIG. 28 is an explanatory diagram of image processing.

FIG. 29 is an explanatory diagram in a case where image processing is performed using a letter A as an original image.

FIG. 30 is a circuit diagram showing another image processing circuit according to the second embodiment.

FIG. 31 is a block diagram showing an outline of a circuit in a case where shadowing processing is performed next to hollow processing for explaining the fourth embodiment;

FIG. 32 is a block diagram showing an outline of a circuit in the case where a hollowing process is performed after the shadowing process.

FIG. 33 is an explanatory diagram illustrating a processed image when image processing is performed by the circuit in FIG. 31;

FIG. 34 is an explanatory diagram illustrating a processed image when image processing is performed by the circuit in FIG. 32;

FIG. 35 is a block diagram illustrating an example of a circuit that arbitrarily performs a hollowing process and a shadowing process.

FIG. 36 is a plan view showing a menu display.

FIG. 37 is an explanatory diagram showing a menu structure.

FIG. 38 is a diagram showing a display state of a menu screen.

FIG. 39 is a diagram showing a display state of a menu screen.

FIG. 40 is a diagram showing a display state of a menu screen.

FIG. 41 is a diagram showing a display state of a menu screen.

FIG. 42 is a diagram showing a display state of a menu screen.

FIG. 43 is a diagram showing a display state of a menu screen.

FIG. 44 is a diagram showing a display state of a menu screen.

FIG. 45 is a diagram showing a display state of a menu screen.

FIG. 46 is a diagram illustrating a display state of a menu screen.

FIG. 47 is a diagram showing a display state of a menu screen.

FIG. 48 is a diagram showing a display state of a menu screen.

FIG. 49 is a diagram illustrating a display state of a menu screen.

FIG. 50 is a diagram illustrating a display state of a menu screen.

FIG. 51 is a diagram illustrating a display state of a menu screen.

FIG. 52 is a diagram illustrating a display state of a menu screen.

FIG. 53 is an explanatory diagram showing a state of switching a menu screen.

FIG. 54 is an explanatory diagram showing how a menu screen is switched.

FIG. 55 is a diagram showing a display state of a menu screen.

FIG. 56 is a diagram showing a display state of a menu screen.

FIG. 57 is a diagram showing a display state of a menu screen.

FIG. 58 is a diagram illustrating a display state of a menu screen.

FIG. 59 is an explanatory diagram showing the principle of a shadowing process for explaining a conventional example.

FIG. 60 is an explanatory diagram showing a processing method of a stereoscopic shadowing process.

FIG. 61 is an explanatory diagram showing a processing method of a shadow shading process;

FIG. 62 is an explanatory diagram showing a processing method of a conventional blanking process.

FIG. 63 is an explanatory diagram showing a processing method of a conventional blanking process.

FIG. 64 is a block diagram schematically showing the overall image processing.

FIG. 65 is a block diagram schematically showing an image processing unit.

FIG. 66 is a terminal connection diagram of a line memory.

FIG. 67 is a block diagram illustrating a main part of an image processing unit.

FIG. 68 is a block diagram illustrating a main part of a coloring processing unit.

FIG. 69 is an explanatory diagram of an image forming operation in image processing of shadowing for explaining a conventional example.

[Explanation of symbols]

113 image processing unit, 114R, 114G, 115B, 208R, 208G,
208B Line memory 115R, 115G, 115B Coloring section, 150 shadow selector, 160 shadow width data register, 160C, 160 shadow width data register, 162 control register, 170 all-zero data register, 170C color conversion selector, 171 decrement operation unit , 171C shadow selector, 172 shadow detection comparator, 172C processing selector, 173 delay register, 173C mode selector, 209 image processing circuit, 210R, 210G, 210B coloring circuit, 240, 241, 242, 243, 244, 245 shift Register, 240C, 241C data register, 242C, 290 control register, 250, 253 thinning amount selector, 250C color conversion selector 251, 254 thickening amount selector, 251C contour Collector, 252 and 255 shift amount selector, 252C process selection selector, 252,253a, 254a, 255,255a, 25
6, 258, 259 shift amount selector, 253C, 254C, 256, 257, 260, 26
1,262 Mode selector. 301 hollow processing section, 302 shadow processing section, 351, 352, 353, 354, 355 selector, 801 image reading section, 802 image processing section, 803 image recording section

Claims (1)

(57) [Claims] 1. An image processing apparatus for performing color image processing, comprising: a decomposing unit for decomposing an input color image for each color component; thickening data and thinning data for each color component decomposed by the decomposing unit. A hollowing-out processing means for performing hollowing-out processing by using an image for each color component subjected to the hollowing-out processing by the hollowing-out means .
Combining means for combining at a position shifted by a corresponding shift amount, and referring to the color of the input color image with respect to the image combined by the combining means, inputting each color segment component.
And a coloring means for coloring with the same color as the force color image .