JP3323698B2 - Mobile station and detection method for CDMA mobile communication system - Google Patents

Abstract

PURPOSE: To reduce the operation speed of a detection circuit part of a mobile station by performing averaging of the phase error, delay of reception data, and phase correction processing in a symbol rate unit. CONSTITUTION: An accumulator 41 converts a phase error signal 22, which is outputted from a pilot signal inverse spread circuit part 21 at a chip rate, to a phase error signal 22' of a symbol rate and supplies it to an averaging circuit part 43. An accumulator 44 converts a data signal group 12, which is outputted from a data inverse spread circuit part 42 at the chip rate, to a data signal group 14 of the symbol rate and supplies it to a data delay circuit 48. A phase correction circuit part 49 corrects the value of a data signal group 16, which is outputted from the delay circuit part 48 at the symbol rate, in accordance with a phase correction signal 24 outputted from the averaging circuit part 43. By this constitution, the operation speed or the circuit part required for phase correction is reduced, and the power consumption of the mobile station is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile communication system, and more particularly to a CDMA (Code Division Multiple A) system for demodulating data using a pilot signal inserted into a downlink.
ccess) A mobile station of a mobile communication system and a detection method in the mobile station.

[0002]

2. Description of the Related Art Conventionally, as a detection (demodulation) method, a PLL is used.
A synchronous detection method using a (Phase Locked Loop) circuit and a delay detection (differential detection) method are known.

In the synchronous detection system, the carrier frequency and the phase shift in the carrier band between the transmitter and the receiver are determined by the P
Compensation is performed by the LL circuit. In a mobile communication system to which the synchronous detection method is applied, there is a problem that in a state where a mobile device moves and fading or the like occurs (dynamic characteristics), the PLL circuit cannot follow the mobile device, and the error rate characteristic is significantly deteriorated.

On the other hand, in the differential detection method, the transmitter converts data into a phase difference of a transmission signal by differential encoding and transmits the data, and the receiver performs differential decoding to perform signal decoding. Data demodulation without obtaining absolute phase. According to this method, it is not necessary to match the frequency and the absolute phase of the carrier wave between the transmitter and the receiver, but there is a phenomenon that the error rate characteristic is deteriorated even when the mobile device is stationary (static characteristics).

[0005] As one of the detection methods in which the error rate characteristic does not deteriorate in any of the static characteristic and the dynamic characteristic, for example, "CD"
A Study on MA Mobile Station Demodulation Method ", IEICE Spring Conference, A-5 Spread Spectrum, A-268, p.
p. 1-270 (1994) proposes a data demodulation method using a pilot signal inserted into a downlink (channel).

FIG. 2 shows a process of modulation and demodulation of a signal performed between a base station 51 and a mobile station 52 in a conventional CDMA mobile communication system using a pilot signal inserted into a downlink.

The base station 51 converts a transmission signal (data signal) addressed to each mobile station into a two-series data signal (I, Q) 50 by a serial / parallel conversion circuit or an encoding circuit. Are input to multipliers 501A and 501B, respectively, and spread codes 54 for data signals (PN- _ID , PN
_-QD ).

[0008] The spread code (PN _{-ID, PN-QD)} in, for example, used code of 128-chip length having a 128-fold rate of the symbol rate of the transmission data, thereby, the sign of the transmission data ( Bit) “1” or “0” is converted into a code pattern consisting of 128 chips or a code pattern obtained by inverting the phase of the code pattern.

The data signal I spread by the spreading code 54,
Q is quadrature modulated by multipliers 502A and 502B, for example, quadrature phase modulation (QPSK).
After applying aseShift Keying), the sum is added by the adder 503 and transmitted as a radio wave of the radio frequency band 55 from the antenna. FIG. 10A shows the relationship between the combination of the signal I and Q values (“1” or “0”) in QPSK and the signal space.

In order to simultaneously communicate with a plurality of mobile stations, the base station assigns a unique data signal spreading code to each mobile station and forms a plurality of signal channels. For example, the channel X, the data signals I (X), Q (X) is the channel X unique spreading codes PN _-ID (X), is spread with _PN-QD (X), the channel Y, the data signals I (Y), Q
(Y) is a spreading code PN unique to channel Y
_-ID (Y), is spread with PN _-QD (Y).

The base station 51 transmits a pilot signal as a reference signal when each mobile station 52 demodulates a data signal, in addition to the data signals of the plurality of channels. The pilot signal is composed of two series of signals I (P) and Q (P) having a fixed bit pattern (continuous pattern of bits “1”).
Is spread with a spreading code PN- _IP , PN- _QP unique to a pilot signal channel having a chip pattern different from the spreading code 54 for the data signal, and then quadrature-modulated in the same manner as the data signal. It is transmitted in the radio frequency band 55.

FIG. 2 shows a quadrature modulation circuit for one signal channel for simplicity.
In the transmission circuit, signals of a plurality of channels (data signal channel and pilot signal channel), each of which has been spectrum-spread with its own spreading code, are multiplexed for each of the I signal component and the Q signal component, and then multiplied for orthogonal modulation. Input to the devices 502A and 502B.

In each mobile station 52, the signal received from the antenna is input to multipliers 504A and 504B,
Quadrature detection is performed by the local oscillation frequency output from 0. The output signal from the detection circuit is LPF (Low Pass Filtration).
ter) The harmonic components are removed by 56A and 56B,
The received signal (I ′, Q ′) becomes 1.

A transmitter 510 for quadrature modulation at a base station
And quadrature detection (demodulation) oscillator 520 in each mobile station
Operate asynchronously with each other, the received signal (I ′, Q ′) 1 after the detection includes an error in the signal value due to a phase shift (or frequency mismatch) with the modulation side. ing. That is, the quadrature detection by the oscillator 520 is a temporary detection, and the received signal (I ′, Q ′) 1 needs signal processing for removing a phase error (hereinafter, referred to as phase correction).

FIG. 3 is a diagram for removing a signal value error caused by a phase shift from a received signal (I ′, Q ′) 1 to reproduce the same data signal (I, Q) as the data signal transmitted by the base station. 1 shows a configuration of a conventional mobile station detection circuit.

Reference numeral 21 denotes a pilot signal despreading circuit for despreading the received signal 1 with a pilot code spreading code 26 to generate a phase error signal (Δcosφ, Δsinφ) 22 which changes according to the phase shift angle; Is the phase error signal (Δcosφ, Δsinφ) output from the despreading circuit section 21
22 is averaged over a plurality of chip periods, so that a correction signal (COS
φ, SINφ) 24 is shown. 25 is a pilot signal spreading code (PN- _IP , P
_N-QP) 26 and the data spread code to be supplied to the data despreading circuit 32 to be described later (PN _-ID, PN _-QD) 27
Is a spreading code generation circuit section for generating. The data spread code (PN _-ID, PN _-QD) has a specific code pattern on a signal channel.

Reference numeral 28 denotes a data delay circuit for delaying the reception signal 1 by a time corresponding to the time required for averaging the phase error signals (Δcosφ, Δsinφ) in the averaging circuit 23; A phase correction circuit unit 32 for correcting the phase of the received signal 29 output from the delay circuit unit 28, and a data despreading unit 32 for despreading the phase-corrected received signal 31 using the data spreading code 27 The circuit section 34 is an accumulator for converting the chip rate data signal 33 output from the despreading circuit section 32 into demodulated data (I, Q) having a symbol rate.

Here, referring to FIG. 10B, paying attention to a pilot signal in which signal (I, Q) is always transmitted with a value of (1, 1), a transmission signal from a base station is transmitted. And the relationship between the received signal 1 at the mobile station will be described.

The pilot signal P transmitted by the base station at a value (I = 1, Q = 1) located in the first quadrant of the IQ signal space
1 is a signal having values of I = i ′ and Q = q ′ in the I′-Q ′ signal space of the mobile station when the phase shift angle is φ.
When the phase shift angle φ exceeds π / 2, the pilot signal P1 is located in a quadrant other than the first quadrant (second quadrant to fourth quadrant) in the I′-Q ′ signal space of the mobile station. Since the signal is received as a signal, the value becomes completely different from the transmission signal of the base station.

In the mobile station, the pilot signal P1 is
As indicated by a point P2, on the assumption that the signal has a value of i = q in the first quadrant of the I'-Q 'signal space, the value of the I and Q components of the received pilot signal is ,
A phase shift amount (angle φ) between the I′-Q ′ signal space and the IQ signal space is detected.

In FIG. 3, a pilot signal despreading circuit 21 despreads the quadrature detection signal 1 (I ′, Q ′) with a pilot signal spreading code 26. At this time, the signal component I ′ of the input signal 1 is multiplied by the multipliers 210A and 211A.
The signal component Q ′ is input to multipliers 210B and 211B, and the multipliers 210A and 210B are provided with the PN- _IP of the spreading code 26 for the I component of the pilot signal.
11A and 211B are provided with a spreading code 26PN- _QP for the Q component of the pilot signal.
B is added by an adder 212A, and a multiplier 210B,
The output of 211A is subtracted by a subtractor 212B.

Due to the above-mentioned phase shift, the I and Q components of the transmission pilot signal are mixed with each other in the output signals I 'and Q' from the detection circuit. In the spreading circuit, the signal I ′ is despread with spreading codes PN- _IP and PN- _QP to obtain Ii and Iq components of the pilot signal, and the received signal Q ′ is spread with the spreading codes PN- _IP and PN- _QP . By despreading, Qi and Qq components of the pilot signal are obtained. Further, the Ii component and the Qq component are added by the adder 212A, whereby the phase error signal Δcosφ proportional to COSφ is obtained.
Is obtained, and the Iq component is subtracted from the Qi component by the subtractor 212B, whereby a phase error signal Δsinφ proportional to SINφ is obtained.

The averaging circuit section 23 outputs a phase error signal (Δcos
φ, Δsinφ) 22 to obtain a phase correction signal (SINφ, COSφ) 24 from which noise has been removed.
Generate

The averaging circuit section 23 includes, for example, two analog cascaded one-chip delay gates (Dc) 230 for shifting the phase error signals Δcosφ and Δsinφ, as shown in FIG. It comprises a value shift register (serial-parallel converter) and adders 235 and 236 for adding the input signal of the shift register and the output signal from each delay gate.

128 one-chip delay gates (Dc) 2
By connecting 30 in series, a delay gate Ds equivalent to one symbol is formed. In this example, each shift register has three symbol delay gates 2 connected in series.
31, 232 and 233, and the phase error signal Δc
For each of osφ and Δsinφ, values of 128 × 3 chips continuous on the time axis are added by the adders 235 and 236, so that the phase correction signals (COSφ, SINφ) 24 from which noise has been removed by averaging are added.
Is to be obtained.

The data delay circuit section 28 includes, for example, two analog value shift registers (delay circuits) each including a plurality of one-chip delay gates Dc280 connected in cascade, as shown in FIG. The number of delay chip stages N required in the averaging circuit unit 23 (N = 128 × 3 in the above example)
And the number M of delay chips in the data delay circuit section 28, a relationship of M = (N-1) / 2 is established. This is for correcting a phase error by a phase correction value obtained from a group of pilot signals located before and after the target data signal by a predetermined number of chips.

In this example, since M = 191.5,
The number M of delay chip stages of the shift register is “191” or “192”. Ds281 is a one-symbol equivalent delay gate unit formed by connecting 128 one-chip delay gates Dc280. In order to set the total number of delay chip stages to "191" or "192", the delay gate unit 281 includes: A half-symbol delay gate unit Ds' 282 comprising 63-stage or 64-stage one-chip delay gates Dc280 is connected.

As shown in FIG. 6, for example, the phase correction circuit 30 converts the I 'and Q' components of the delay data 29 output from the data delay circuit 28 into multipliers 301A, 301B,
02A and 302B, COSφ and SIN of the correction signal 24
After multiplication by φ, adder 303A and subtractor 30
By performing addition and subtraction in 3B, an error in the data signal value due to the phase shift is corrected. As a result, the target data signal (I, Q) 35 in the data despreading circuit unit 32
Can be demodulated.

[0029]

As described above, in the detection circuit in the conventional CDMA mobile communication system, the averaging process of the phase error detected from the pilot signal and the delay and phase correction of the received signal are performed by using the spreading code. Since the operation is performed at the chip rate, it is necessary to operate a circuit section for performing these processes with a high-speed clock, and as a result, there is a problem that components of the detection circuit are expensive and power consumption is increased.

An object of the present invention is to provide a mobile station and a detection method for a CDMA mobile communication system that can execute a phase correction process with a low-speed clock and reduce power consumption.

[0031]

In order to achieve the above object, in a mobile station according to the present invention, a phase error signal output at a chip rate of a spreading code from a pilot signal despreading circuit section and a data signal despreading circuit are provided. After converting the data signal output at the chip rate of the spread code from the unit to the symbol rate of the transmission data, the phase correction of the data signal is performed by the correction signal generated from the phase error signal. Features.

In this case, the phase correction signals (COSφ, SI
Nφ), the phase error signals (Δcosφ, Δsinφ) converted to the symbol rate are serial-parallel converted by a relatively low-speed shift register that performs a shift operation at the symbol rate, and the phase error signals for a plurality of symbols are averaged by an adder. It can be obtained by

Further, in the conventional apparatus, after correcting the phase of the received signal, the I and Q components of the data signal are extracted by despreading with the data signal spreading code. After the I and Q components of the received signal obtained by the above are despread by a data signal despreading circuit, the transmission rate of the data signal group output from the despreading circuit is converted into a symbol rate, and the phase is passed through a delay circuit. Input to the correction circuit section.

[0034]

According to the above arrangement, the processes for averaging the phase error signal, delaying the data signal, and correcting the phase are performed at the symbol rate, so that these circuit portions can be operated with a low-speed clock. It is possible to reduce power consumption.

[0035]

FIG. 1 is a block diagram showing the configuration of a detection circuit for a CDMA mobile communication system according to the present invention.
3 are applied to the same circuit elements to facilitate comparison with the conventional system shown in FIG.

In FIG. 1, reference numeral 21 denotes a signal (Δcosφ, Δsinφ) indicating the phase error by despreading the quadrature-detected reception signal (I ′, Q ′) 1 with a pilot signal spreading code.
A pilot signal despreading circuit section 41 that outputs 22;
The phase error signal 22 output at the chip rate from the despreading circuit section 21 is converted into a symbol rate signal (Δcos
An accumulator 43 for converting the phase error signals Δcosφ ′, Δsi
For nφ ′, an averaging circuit for calculating an averaged value for a plurality of symbol periods and outputting it as a phase correction signal 24, 25 is a spreading code generating circuit for generating a spreading code, and 26 is a pilot signal spreading code ( PN- _IP , PN
_-QP ) and 27 are data signal spreading codes (PN- _ID , PN
_-QD ), 42 is a data despreading circuit unit for despreading the received signal with the data spreading code 27, and 44 is the transmission rate of the data signal 12 despread by the despreading circuit unit 42 from the chip rate An accumulator 48 for converting to a symbol rate is a data signal 1 having a symbol rate.
A data delay circuit section 49 for delaying the phase error signal 4 by a time corresponding to the time required for averaging the phase error signal, 49 corrects the phase error included in the reception data output from the data delay circuit section 48 by the phase correction signal 24. The phase correction circuit section 35 for performing the phase correction is the phase-corrected demodulated data (I, Q).

The pilot signal despreading circuit 21 converts the received signal (I ', Q') 1 into a pilot code spreading code (P
N- _IP , PN- _QP ) 26. In this case, both of the received signals I ′ and Q ′ are converted into I and Q components (PN
_-IP, despreads respectively _PN-QP), the adder 212A as shown, added with subtractor 212B, by performing subtraction, value dependent on the phase shift angle phi (phase error) Derutashioesufai, Δsinφ is obtained. Phase error signal 22 output at the chip rate from despreading circuit 21
Are integrated by the accumulator 41 for each symbol period (128 chip periods) and converted into symbol-rate phase error signals (Δcosφ ′, Δsinφ ′) 22 ′, and then supplied to the averaging circuit unit 43.

The averaging circuit section 43 includes a phase error signal Δcos φ ′, Δsin φ ′ input during a plurality of symbol periods.
Are respectively averaged to generate phase correction signals (SINφ, COSφ) 24 of the received data. One example of the configuration of the averaging circuit unit 43 is shown in FIG.

Ds (430) is an analog gate having a delay time of one symbol. In this example, in order to remove noise from the phase error signals Δcosφ ′ and Δsinφ ′, the phase error signal Δcos input at the symbol rate is used.
φ ′ and Δsin φ ′ are input to shift registers SR-A and SR-B each having a two-stage symbol delay gate 430, and a phase error of three symbols consisting of the input signal of the shift register and the output signal of each delay gate The signals are added by adders 431 and 432, respectively. Each of the above adders 4
31 and 432 are phase error signals Δcosφ ′, Δsin
φ ′ is averaged and this is phase-corrected (COSφ and SI
Nφ). Note that the shift register SR-
A and SR-B need not be composed of a large number of chip delay gates operating at a high chip rate as in the prior art shown in FIG. 4, and a low-speed delay gate operating at a symbol rate can be applied.

In the data despreading circuit 42, the received signal I 'is sent to the multipliers 420A and 421A, and the received signal Q'
Is input to the multipliers 420B and 421B,
0A and _420B are supplied with the data spreading code PN-ID, and the multipliers 421A and 421B are supplied with the data spreading code P-ID.
By supplying N- _QD , four-system data signals 12 despread are obtained. These despread data signals 12 are converted from a chip rate to a symbol rate by four accumulators 44 (44A to 44B ') provided corresponding to multipliers 420A to 421B. The data signal 14 at the symbol rate is delayed by the data delay circuit 48 by a predetermined time determined by the required averaging time in the averaging circuit 43, and then supplied to the phase correction circuit 49.

FIG. 8 shows an example of the configuration of the data delay circuit section 48.

Since a relationship of M = (N-1) / 2 is established between the number N of symbols required for averaging the phase error and the number M of delay symbols required in the delay circuit section 48, FIG. As shown in (2), when a two-symbol shift register is used in the averaging circuit unit 43 (N = 2), the data delay circuit unit 4
8, the required number of delay symbols is M = 1. in this case,
As shown in FIG. 8, the data delay circuit section 48 may delay each accumulator output by a one-stage symbol delay gate (Ds) 480 (480A to 480B ') operating at a symbol period.

The phase correction circuit section 49 corrects the value of the data signal 16 output from the delay circuit section 48 at the symbol rate in accordance with the phase correction signal 24, thereby removing the data signal I, Convert to Q

FIG. 9 shows an example of the configuration of the phase correction circuit section 17.

Of the delayed data signal 16, the I component signal is output from multipliers 490A and 490A ', and the Q component signal is output from multipliers 490B and 490B'.
Sφ and SINφ, and the multiplication result is added to adder 1
As shown in FIG. 9, the data signal (I, Q) 35 whose phase has been corrected is obtained by adding and subtracting 90A and the subtractor 491B as shown in FIG. Therefore, by processing these data signals 35 by a decoding circuit (not shown),
Data transmitted from the base station can be demodulated.

According to the present embodiment, the pulse trains 12 and 22 at the chip rate obtained by despreading the received signal with the spreading codes for the pilot signal and the data signal are converted into the pulse trains at the symbol rate, and then phase corrected. Therefore, the operation clock of the circuit portion required for the phase correction can be reduced in speed.

In the embodiment, an example has been described in which the phase error signal is averaged by three symbols. However, when the number of symbols to be averaged is increased to 5, 7, or 9 symbols, the data delay unit The number of connection stages of the symbol delay gates may be set to 2, 3, and 4, respectively.

In the circuit configuration shown in FIG. 1, the functions of the averaging circuit section 43, the data delay circuit section 48, and the phase correction circuit section 49 may be realized by software using a digital signal processor. In this case, since the digital signal processor only needs to process the input signal of the symbol rate, the number of executions of the program for the phase correction can be greatly reduced.

[0049]

As is apparent from the above description, according to the present invention, chip-rate signals 12 and 2 obtained by despreading with spreading codes for pilot signals and data signals.
Since 2 is converted to the symbol rate and then the phase is corrected, the operation of the circuit portion required for the phase correction can be slowed down, and the power consumption of the mobile station of the CDMA mobile communication system can be suppressed. When the phase correction is executed by software, the frequency of execution can be suppressed, and the overhead of the signal processor can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a detection circuit of a mobile station in a CDMA mobile communication system according to the present invention.

FIG. 2 is a diagram showing a quadrature modulation circuit in a base station and a quadrature detection circuit in a mobile station.

FIG. 3 is a block diagram showing an example of a conventional technique of a detection circuit of a mobile station in a CDMA mobile communication system.

FIG. 4 is a diagram illustrating a configuration of a phase error signal averaging circuit unit 23 according to the related art.

FIG. 5 is a diagram showing a configuration of a data delay circuit unit 28 according to the related art.

FIG. 6 is a diagram showing a configuration of a phase correction circuit unit 30 according to the related art.

FIG. 7 shows a phase error signal averaging circuit section 4 according to the present invention.
FIG.

FIG. 8 is a diagram showing an example of a configuration of a data delay circuit unit 48 according to the present invention.

FIG. 9 shows a configuration 1 of the phase correction circuit unit 49 according to the present invention.
The figure which shows an example.

10A is a signal space diagram of QPSK, and FIG. 10B is a diagram for explaining a phase error.

[Explanation of symbols]

1: received data, 21: pilot signal despreading circuit section,
34, 41, 44 ... accumulators, 23, 43 ... averaging circuit unit, 24 ... phase control signal, 25 ... spreading code generation unit, 26 ... spreading code for pilot signal, 27 ... spreading code for data signal, 28, 48 ... Data delay circuit section, 30,
49: phase correction circuit section, 32, 42: data despreading circuit section, 35: demodulated data, 51: base station, 52: mobile station,
55: radio frequency band, 56: low-pass filter, 23
0, 280... Chip delay gates, 231, 281, 48
0: Symbol delay gate, 235, 236, 431, 4
32 ... adder, 282 ... half symbol delay gate.

Continuation of the front page (56) References JP-A-6-90219 (JP, A) JP-A-7-250008 (JP, A) JP-A-6-90221 (JP, A) Naoya Kobayashi (two outsiders), A Study of Quasi-Synchronous Detection and Demodulation for CDMA Mobile Communication System, Proc. Of the 1994 IEICE Spring Conference, March 10, 1994, 1. Fundamentals and Boundaries, 1-271, A-269 Eiji Murai (2 other members), A study on CDMA mobile station demodulation method, Proceedings of the 1994 IEICE Spring Conference, March 10, 1994, 1. Fundamentals and Boundaries, 1-270, A-268 Yasuo Ogoshi (2 others), A study on synchronous detection in CDMA mobile communications, Proc. Of the 1994 IEICE Autumn Conference, September 5, 1994, 1. Communication 1,306, B-306 (58) Fields surveyed (Int. Cl. ⁷ , DB name) H04J 13/00-13/06 H04B 1/69-1/713

Claims (7)

(57) [Claims] 1. A CDMA system in which a base station performs spread-spectrum multiplexing of a pilot signal and I and Q components of transmission data with respective spreading codes, and then performs quadrature modulation and transmits the CDMA.
(CodeDivision Multiple Access) A mobile station for a mobile communication system, comprising: a quadrature detection circuit (504, 520) for separating a received signal into an I component multiplexed signal and a Q component multiplexed signal; The demultiplexed signal and the Q component multiplexed signal are despread using spreading codes specific to the I and Q components of the pilot signal, respectively, and the amount of phase shift between the quadrature detection circuit and the quadrature modulation circuit provided in the base station. A first despreading circuit (21) for generating first and second phase error signals having values corresponding to the following, and processing the phase error signal supplied from the first despreading circuit, A circuit (41, 43) for generating first and second phase correction signals having a symbol rate of transmission data; and I and I of a data channel to receive the I-component multiplexed signal and the Q-component multiplexed signal, respectively. Component and the Q component A second despreading circuit (42) for despreading using a code to output a set of data signals, and transmitting the transmission rate of the data signal group output from the second despreading circuit to the transmission A rate conversion circuit (44) for converting the data rate into a symbol rate; and correcting the value of each data signal converted to the symbol rate in accordance with the first and second phase correction signals, thereby obtaining a phase error. And a phase correction circuit (48, 49) for generating an I-component data signal and a Q-component data signal that do not include a signal. The circuit for generating the correction signal is supplied from the first despreading circuit. A rate conversion circuit (41) for converting a transmission rate of the first and second phase error signals into a symbol rate of the data signal; and a first and second phase error signals supplied from the rate conversion circuit. Each predetermined period By averaging the inner, first pair of averaging circuits for generating a second phase correction signal: mobile station; and a (43 SR-A, SR-B). 2. A pre-SL phase correction circuit, a delay circuit (48) for delaying the data signal group has been converted to the symbol rate by a predetermined time determined by a signal delay time in the upper Symbol averaging circuit, the The signal value of the data signal group supplied from the delay circuit is corrected according to the first and second phase correction signals, and the I component data signal and the Q component data signal are generated from the corrected data signal group. The mobile station according to claim 1, further comprising an arithmetic circuit (49). 3. A serial-to-parallel converter (SR-A, SR-A) for outputting a phase error signal of a plurality of symbol periods received in time series from the rate converter in parallel with each of the pair of averaging circuits. and SR-B), a plurality of phase error signal output from the serial-parallel conversion circuit, having a means (235, 236) for producing a phase correction signal with the averaged value in the plurality of symbols period The mobile station according to claim 1 , wherein: (4) The delay circuit (44) is connected to the serial / parallel conversion circuit.
Of a plurality of phase error signals output in parallel from the
The data signal corresponding to that located at the center is calculated
Delaying the data signal so as to supply it to the circuit.
3. The mobile station according to claim 2, wherein: 5. A CDMA system in which a base station performs spread-spectrum multiplexing of a pilot signal and I and Q components of transmission data using respective unique spreading codes, and then orthogonally modulates and transmits.
(CodeDivision Multiple Access) A mobile station for a mobile communication system, comprising: a quadrature detection circuit for separating a received signal into an I component multiplexed signal and a Q component multiplexed signal by quadrature detection; the Q component multiplexed signal and despread with the spreading code specific to the I and Q components of their respective pilot signals and the phase shift between the quadrature modulation circuit the quadrature detection circuit and the base station comprises A first despreading circuit (21) for generating first and second phase error signals having a value corresponding to the quantity, and first and second phases supplied from the first despreading circuit. first rate converter (22), each of the I component multiplexed signal and the Q component multiplexed signal to be the their respective received data to convert the transmission rate of the error signal to the symbol rate of the transmission data Specific to channel I and Q components A second despreading circuit (42) for despreading using a spreading code of (i) and outputting a set of data signals, and a transmission rate of the data signal group output from the second despreading circuit. A second rate converter (44) for converting the transmission data into a symbol rate of the transmission data; and a first and a second phase error signals supplied from the first rate converter are averaged within a predetermined period, respectively. Averaging means (43) for generating first and second phase correction signals by converting the first and second phase correction signals based on the first and second phase correction signals. having by correcting the signal values of the data signal group supplied, the signal processing apparatus for generating an I component data signal and the Q component data signals not containing the phase error and (43,48,49) from A mobile station characterized by the following. Wherein said signal processing unit, delay means for causing the data signal group supplied from said second rate converter is delayed by a predetermined time determined by a signal delay time of the averaging means (48) 6. The mobile station according to claim 5 , wherein each signal value of the data signal group delayed by the delay unit is corrected according to the first and second phase correction signals. 7. A CDMA (Code Division Multiple Acquisition) for orthogonally modulating and transmitting pilot data and transmission data multiplexed by spread spectrum from a base station to a mobile station.
cess) A detection method for a mobile station in a mobile communication system, and separating the I component multiplexed signal and the Q component multiplexed signal by quadrature detection a reception signal, the I component multiplexed signal and the Q-component Despreading the multiplexed signal using a spreading code specific to each of the I and Q components of the pilot signal, and generating first and second phase error signals from a signal obtained by the despreading; Despreading the I-component multiplexed signal and the Q-component multiplexed signal using spreading codes specific to the I and Q components of the data channel to be received, respectively, to generate a set of data signal groups; Processing the first and second phase error signals to generate first and second phase error signals having a transmission data symbol rate; and first and second having the transmission data symbol rates. Rank
Averaging the phase error signals within a predetermined period
Generating first and second phase correction signals
If, converting the transmission rate of the data signal group into the symbol rate of the transmission data, the data signal group converted to the symbol rate,
Predetermined time determined by the signal delay time by the above averaging
Delaying the signal values of the delayed data signal group by the first and second data signals .
And a step of generating an I component data signal and a Q component data signal that do not include a phase error from the corrected data signal group.