JP3319711B2 - Layout structure of barrel shifter with decode circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a barrel shifter used for data processing of a microprocessor or the like, and more particularly, to a high-speed operation thereof.

[0002]

2. Description of the Related Art In recent years, automation of semiconductor integrated circuit design has been advanced in order to shorten the design period. Among them, a barrel shifter capable of realizing a shift operation of an arbitrary amount of bits in one operation has a bit slice structure, that is, a mask layout symmetrical on a bit-by-bit basis, in order to speed up data processing and reduce the chip area. Is widely used.

[0003] Hereinafter, a barrel shifter based on a conventional data path design will be described.

FIG. 6 shows a configuration example of a barrel shifter in a conventional data path. In FIG. 1, a register file 20 includes a register A that stores 4-bit data A (3) to A (0) as bit-shifted data in advance, and 2-bit data as a control signal that specifies a bit shift amount.
It has a register B that stores B (1) and B (0) in advance.

[0005] Four flip-flops FFA3, FFA2, FFA
1, 4-bit data A (3) to A (0) read from the register A are input to FFA0. Further, 2-bit data B (1) and B (0) read from the register B are input to the two flip-flops FFB1 and FFB0. The output value of each flip-flop is updated by a clock signal CLK.

The decode circuits DEC1 and DEC0 decode the outputs C1 and C0 of the two flip-flops FFB1 and FFB0, respectively, and output the decoded bit shift amounts of the binary numbers from the output terminals C and NC.

The 1-bit shift unit 21 outputs the outputs of the four flip-flops FFA3 to FFA0 to their input terminals D (3) to D (3).
Receive at (0). The 2-bit shift unit 22 receives outputs from the output terminals X1 (3) to X1 (0) of the 1-bit shift unit 21 at its input terminals D (3) to D (0). The decoding circuits DEC0, DE
The bit shift amount of C1 is determined by the 1-bit shift units 21 and 2
Each of the bit shift units 22 is controlled. The one-bit shift unit 21 receives an input terminal D based on the received bit shift amount.
(3) to shift data received by D (0) by 1 bit or not. The 2-bit shift unit 22 shifts the data received at the input terminals D (3) to D (0) by 2 bits or does not shift the bit based on the received bit shift amount. Outputs from the output terminals X2 (3) to X2 (0) of the 2-bit shift unit 22 are output results of the barrel shifter. As described above, the data read from the register A is bit-shifted by the shift amount indicated by the lower two bits of the register B.

FIG. 7 shows a layout diagram of the bit shifter of FIG. In FIG. 7, the register file 20, the four flip-flops FFA3 to FFA0, the 1-bit shift unit 21, and the 2-bit shift unit 22 are symmetrically laid out in bit units to form a bit slice structure. A bit data path is configured.

FIG. 7 shows decoding circuits DEC0 and DEC1.
Are laid out on the left side of the 1-bit shift unit 21 and the 2-bit shift unit 22, respectively, in the figure, and the two flip-flops FFB1 and FFB0 are further provided with the decode circuits DEC0 and DEC1.
Are laid out on the left side of FIG. That is, the decoding circuits DEC0 and DEC1 and two flip-flops FFB
1 and FFB0 are both laid out outside the 4-bit data path.

As described above, in the barrel shifter according to the conventional data path design, the bit slice structure having a symmetrical mask layout in units of bits corresponds to the register file 2.
0, only the flip-flops FFA3 to FFA0 to which the bit-shifted data is input, the flip-flops FFB1, FFB0, including only the 1-bit shift unit 21 and the 2-bit shift unit 22, and receiving the data specifying the bit shift amount. Generally, the decode circuits DEC0 and DEC1 are laid out outside the data path. For example, Japanese Unexamined Patent Publication No. 7-141146
In the publication as well, the decoding circuit is arranged outside the data path.

[0011]

However, in the conventional barrel shifter layout structure, as described above,
Flip-flop FF to which bit shift amount data is input
B1, FFB0 and decoding circuit DE for decoding this data
Since C0 and DEC1 are laid out outside the data path, it is necessary to propagate the bit shift amount data and the bit shift amount signal from the outside of the data bus to the inside or from the outside of the data path to the inside. As a result, the operating speed of the barrel shifter decreases. For example, in the layout structure of FIG. 7, the register file 20 and two flip-flops FF
Since the distance between B1 and FFB0 is long and the wiring length is long, the timing at which the input signals to the two flip-flops FFB1 and FFB0 are determined is delayed, and as a result, the operation speed of the barrel shifter decreases. There is.

[0012]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a barrel shifter with a decode circuit capable of effectively shortening the wiring length of a signal wiring for transmitting bit shift amount data, having a small wiring delay time and performing a high-speed shift operation. To provide.

[0013] To achieve the above object, the present invention provides:
When the bit number of the bit shift amount data is smaller than the bit number of the bit-shifted data, for example, when the bit-shifted data is 4 bits, 16 bits, or 32 bits,
Focusing on the fact that the bit shift amount data becomes 2 bits, 4 bits or less, and 5 bits or less, respectively, even if the number of bits of the bit shift amount data and the number of bits of the bit shift amount signal of the decoding circuit are summed up, In order to reduce the number of bits of the bit shift data to the number of bits or less, a configuration is adopted in which the flip-flops and the decoding circuits to which the bit shift amount data is input are arranged in the data path while being laid out in a horizontal line.

In other words, the layout structure of the barrel shifter with the decoding circuit according to the present invention has a data input section to which data composed of a plurality of bits is input, and a bit number smaller than the number of bits of the input data. And a control signal input unit for inputting a shift amount control signal, and comprising a smaller number of bits than the number of bits of the input data, receiving the shift amount control signal from the control signal input unit, A decoding circuit for converting the shift amount control signal into a binary bit shift amount, and a number of bits equal to the number of bits of the input data;
A bit shift amount of the decode circuit, and a bit shifter that receives input data of the data input unit and bit-shifts the input data by the bit shift amount, the layout structure of a barrel shifter with a decode circuit, wherein the control signal The input unit and the decoding circuit are laid out side by side in a row, and the control signal input unit;
The decoding circuit, the data input section, and the bit shifter are symmetrically laid out in bit units.

According to a second aspect of the present invention, in the layout structure of the barrel shifter with the decode circuit according to the first aspect, the decode circuit is laid out adjacent to a side of the control signal input section on the upper bit side. It is characterized by being performed.

According to a third aspect of the present invention, in the layout structure of the barrel shifter with the decoding circuit according to the first or second aspect, the control signal input section and the decoding circuit are located above the data input section. It is characterized by being laid out.

According to a fourth aspect of the present invention, in the layout structure of the barrel shifter with the decoding circuit according to the first or second aspect, the bit shifter includes a plurality of bits that can be shifted by a predetermined number of bits. The bit shift units are connected in series.

According to a fifth aspect of the present invention, in the layout structure of the barrel shifter with a decoding circuit according to the first or second aspect, there is provided a register file for inputting the plurality of bits of data to the data input section. The register file is symmetrically laid out in bit units together with the control signal input section, the decoding circuit, the data input section, and the bit shifter.

With the above arrangement, in the first to fifth aspects of the present invention, the control signal input section and the decode circuit are laid out in the data path, so that the bit shift amount data is input to the control signal input section. Therefore, the wiring length until the bit shift amount signal decoded by the decoding circuit is input to the bit shifter can be reduced as compared with the conventional case, so that the wiring load of the barrel shifter can be reduced, and therefore, the wiring delay time is short and the shift speed is high. An operating barrel shifter with a decoding circuit is obtained.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an overall configuration of a barrel shifter according to the present invention, and FIG. 2 shows a layout structure thereof. 1 and 2 illustrate a barrel shifter capable of shifting data composed of 4 bits by up to 3 bits.

In FIG. 1, a register file 1 stores 4-bit data A (3) to A (3) as bit-shifted data.
Register A for storing (0) in advance, and 2-bit data B (1) and B (0) as control signals for specifying the bit shift amount
Is stored in advance in the register B.

4 flip-flops (data input section)
4-bit data A (3) to A (0) read from the register A are input to FFA3, FFA2, FFA1, and FFA0.

The two flip-flops (control signal input units) FFB1 and FFB0 receive 2-bit data B (1) and B (0) read from the register B. 6 above
Each of the flip-flops updates the value of the data input to the input terminal D when the clock signal CLK rises to the H level, outputs the value from the output terminal Q, and outputs the value when the clock signal CLK does not change. Means that the output value of the output terminal Q retains the previous value.

The decoding circuits DEC1 and DEC0 decode the outputs C1 and C0 of the two flip-flops FFB1 and FFB0, respectively, and output the bit shift amounts of the binary numbers as output from the output terminals C and NC.

Reference numeral 2 denotes a bit shifter, which is formed by connecting a first bit shift unit 2a capable of shifting one bit and a second bit shift unit 2b capable of shifting two bits in series. The one-bit shift unit 2a outputs the outputs of the four flip-flops FFA3 to FFA0 to their input terminals D (3) to D (3) to DFA3.
Receive at (0). The two-bit shift unit 2b receives outputs from the output terminals X1 (3) to X1 (0) of the one-bit shift unit 2a at its input terminals D (3) to D (0). The bit shift amounts of the decode circuits DEC0 and DEC1 control the 1-bit shift unit 2a and the 2-bit shift unit 2b, respectively.
The 1-bit shift unit 2a shifts the data received at the input terminals D (3) to D (0) by 1 bit or does not shift the bit based on the received bit shift amount. The 2-bit shift unit 2b shifts the data received at the input terminals D (3) to D (0) by 2 bits or does not shift the bit based on the received bit shift amount. Outputs from the output terminals X2 (3) to X2 (0) of the 2-bit shift unit 2b are output results Y (3) to Y (0) of the barrel shifter. As described above, the register A
The data read out of the register B is bit-shifted by the shift amount indicated by the lower two bits of the register B.

The features of the present invention are as follows. That is,
The register file 1, 4 flip-flops FFA3
To FFA0 and the bit shifter 2 each handle 4-bit data and have a 4-bit width. The two flip-flops FFB1 and FFB0 and the decoding circuits DEC1 and DEC0 transmit 2-bit data as a bit shift amount. It has a 2 bit width. Therefore, in the layout diagram of FIG.
Flip-flops FFB1 and FFB0 are replaced by the lower 2 bits of the four flip-flops FFA3 to FFA0
By laying out at the position corresponding to FFA1 and FFA0, this 2
There is an empty area above the upper bit side of the four flip-flops FFB1 and FFB0, that is, above the upper two-bit flip-flops FFA4 and FFA3 of the four flip-flops FFA3 to FFA0. In addition, the decoding circuit DE
C1 and DEC0 are laid out and this decoding circuit DE
C1 and DEC0 and two flip-flops FFB1 and FFB0 are arranged side by side in the horizontal direction and adjacently arranged.

In FIG. 2, the decoding circuits DEC1, DEC0 and two flip-flops FFB are arranged in a line.
1. Above FFB0, the register file 1 is located. Further, the one-line decoding circuits DEC1 and DEC0 and the flip-flops FFB1 and FFB0 are located above the four flip-flops FFA3 to FFA0.
The bit shifter 2 is located below FFA3 to FFA0. 2, the register file 1, the two flip-flops FFB1, FFB0, the decode circuits DEC1, DEC0, and the four flip-flops FFA3 to FFA0.
The bit shifters 2 are symmetrically laid out on a bit-by-bit basis as shown by the broken lines in FIG.

FIG. 3 shows the internal structure of the decoding circuit DEC1. The internal configuration of the other decoding circuit DEC0 is the same as that of FIG. In the figure, a decode circuit DEC1 receives shift amount data received from a flip-flop FFB1 at an input terminal A, and transfers the shift amount data to two inverters INV1 and INV1.
Inverted sequentially by V2 and output from output terminal C,
The signals are sequentially inverted by three inverters INV1, INV3, INV4 and output from an inverted output terminal NC.

FIG. 4 shows the internal configuration of the 1-bit shift unit 2a. In the figure, the 1-bit shift unit 2a has the number (= 4) of selectors SEL1, SEL2, SEL3, and SEL4 equal to the number of bits (4 bits in the present embodiment) of the input data. Each selector has the same configuration, and each of the two 2
It has input NAND circuits 5 and 6 and one NAND circuit 7 arranged at the subsequent stage. In each selector, the output from the output terminal C of the decode circuit DEC0 is input to the NAND circuit 5 on the left side in the preceding figure, and when the output value of this terminal C is "1", that is, when a one-bit shift is requested. Select data input to the other input terminal of NAND circuit 5. Therefore, the selectors SEL2 to SEL2 for the second and subsequent bits
The L4 NAND circuit 5 has one bit lower data D (0) to
D (2) is input and the selector SEL1 corresponding to the first bit
The sign data S is input as the value of the first bit of the data after one bit shift. On the other hand, the output from the inverting output terminal NC of the decoding circuit DEC0 is input to the NAND circuit 6 on the right side in the figure at the preceding stage of each selector, and when the output value of this terminal NC is "1", that is, one bit shift is performed. When not required, the data input to the other input terminal of the NAND circuit 6, that is, the data D (0) to D (3) of the corresponding bit is selected.

FIG. 5 shows the internal configuration of the 2-bit shift unit 2b. In the figure, the 2-bit shift unit 2b
Like the bit shift unit 2a, it has four selectors SEL1, SEL2, SEL3, and SEL4 having the same configuration. The difference from the 1-bit shift unit 2a is that the selector SEL after the third bit
3. In the NAND circuit 5 of SEL4, two bits lower data D
(0) and D (1) are input to the NAND circuits 5 of the two selectors SEL1 and SEL2 corresponding to the first and second bits, respectively. The point is that the code data S is input as the value of the bit.

Therefore, in the present embodiment, the decoding circuits DEC1 and DEC0 and the two flip-flops FFB1 and FFB0 are arranged side by side in the horizontal direction and are adjacent to each other. Flip-flops FFA3-FF
A0 and the bit shifter 2 are symmetrically laid out on a bit basis, and the decoding circuits DEC1 and DEC0 and the flip-flops FFB1 and FFB0 that handle these bit shift amount data are arranged in the data bus. As described above, there is no need to take out the bit shift amount data outside the data path or into the data path. Therefore,
The length of the signal wiring for transmitting the bit shift amount data can be reduced as compared with the conventional case, and the signal propagation speed can be increased.
The speed of the shift operation of the barrel shifter can be increased.

In the 3-bit barrel shifter of the present embodiment, the output of the output terminal C of the decoding circuits DEC0 and DEC1 is
Assuming that the shift amounts of the 1-bit shift unit 2a and the 2-bit shift unit 2b are X0 (= 1) and X1 (= 2), the bit shift amount Y specified by the shift amount control signal is 0, A1.
Is expressed by the following equation 1 Y = A1 · X1 + A0 · X0 (1) For example, when the outputs A0 and A1 of the decode circuits DEC0 and DEC1 are A0 = 1 and A1 = 0, the bit shift amount Y
Is "1", Y = 2 when A0 = 0 and A1 = 1, and Y = 3 when A0 = 1 and A1 = 1. In general,
When the barrel shifter has n serially connected bit shift units, the bit shift amount Y is expressed by the following equation (2): Y = An-1 ・ Xn-1 + An-2 ・ Xn-2 +... + A1 ・ X1 + A0 ・ X0 (2) Is expressed. Therefore, in the present embodiment, a 3-bit barrel shifter has been described as an example. However, it is needless to say that the present invention can be similarly applied to an n-bit barrel shifter.

Next, the effects of the present embodiment will be described.
Considering the effect of the present embodiment in terms of the gate delay time, it is as follows. Assuming that the no-load delay is T0, the delay load dependency coefficient is Δt, and the output load capacitance is C, the gate delay value T
Can be approximated by the following equation 3. Further, assuming that a wiring load capacitance per unit wiring length is Δc, a wiring capacitance C for a wiring length L
Can be approximated by the following equation 4.

T = T0 + C · Δt (3) C = L · Δc (4) In the layout of FIG. 2, the width per bit of the data path portion is d, the height is h, and the flip-flop is The no-load delay T0 and the delay load-dependent coefficient Δt are denoted by T0f and Δt, respectively.
tf, a delay T0 at the time of no load of the decoder, and a delay load dependence coefficient Δt are T0d and Δtd, respectively. In the layout configuration of FIG. 2, when the bit width of bit-shifted data A is m bits and the bit width of shift amount data B is n bits,
The delay time Tc0 from the rising of the clock signal CLK to the determination of the bit shift amount signals C and NC to the 1-bit shift unit 2a is expressed by the following equation 5. On the other hand, FIG.
In the case of the layout configuration described above, the corresponding delay time Tc0 is expressed by the following equation 6, and the difference (Tc06-Tc01) between the delay times is expressed by the following equation 7.

Tc01 = T0f + n · d · Δtf · Δc + T0d + ((n + 1) h + m · d) · Δtd · Δc (5) Tc06 = T0f + (m · d + (n + 1) h) · Δtf · Δc + T0d + m · d · Δtd · Δc ... (6) Tc06-Tc01 = ((mn) · d · Δtf + (n + 1) h · (Δtf-Δtd)) · Δc ... (7) Normally, Δtf and Δtd are approximately the same size Δt, and the number of bits m is larger than the number of bits n, so that Tco6−Tc01> 0
Becomes For example, the following equation 8 Δtf = Δtd = Δt = 4 psec / fF Δc = 0.2 fF / μm m = 32, n = 5 d = h = 30 μm (8) The configuration is faster than the conventional layout of FIG. 2 by the time shown in the following equation 9.

Tc06−Tc01 = ((mn) · d · Δtf + (n + 1) h · (Δtf−Δtd)) · Δc = (mn) · d · Δt · Δc = 0.648nsec (9) In the case of 200MHz, 1Hz is 5nsec
Since this is a cycle, the time that can be increased is 15 times of one cycle.
%, And the effect of speeding up is great.

In this embodiment, the data to be shifted is 4 bits and the bit shift amount data is 2 bits.
The present invention is not limited to this. Further, the bit shifter 2 has been described as having a configuration in which the bit is shifted in one direction, but it is needless to say that the bit shifter 2 may be configured with a bidirectional bit shifter.

[0039]

As described above, according to the layout structure invention of the barrel shifter with the decoding circuit according to the first to fifth aspects, the input section of the bit shift amount control signal and the decoding circuit are laid out in the data path. Therefore, the signal wiring length from the input of the bit shift amount data to the control signal input section to the input of the bit shift amount signal decoded by the decoding circuit to the bit shifter can be reduced as compared with the conventional case, and the wiring load of the barrel shifter can be reduced. This makes it possible to obtain a barrel shifter with a decoding circuit that can shift at high speed with a short wiring delay time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a barrel shifter according to an embodiment of the present invention.

FIG. 2 is a diagram showing a layout of the barrel shifter.

FIG. 3 is a diagram showing an internal configuration of a decode circuit provided in the barrel shifter.

FIG. 4 is a diagram showing an internal configuration of a 1-bit shift unit of a bit shifter provided in the barrel shifter.

FIG. 5 is a diagram showing an internal configuration of a 2-bit shift unit of the bit shifter.

FIG. 6 is a block diagram showing the entire configuration of a conventional barrel shifter.

FIG. 7 is a diagram showing a layout of a conventional barrel shifter.

[Description of Signs] 1 register file 2 bit shifter 2a 1 bit shift unit 2b 2 bit shift unit FFA3 to FFA0 flip-flop (data input unit) FFB1, FFB0 flip-flop (control signal input unit) DEC1, DEC0 decode circuit SEL1 to SEL4 selector A (0) to A (3) Bit shift data B (0), B (1) Bit shift amount data

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 7/00 H01L 21/82

Claims (5)

(57) [Claims] 1. A data input unit to which data composed of a plurality of bits is inputted, and a control signal input unit comprising a bit number smaller than the bit number of the input data and inputting a shift amount control signal A decoding circuit configured with a smaller number of bits than the number of bits of the input data, receiving the shift amount control signal from the control signal input unit, and converting the shift amount control signal into a binary bit shift amount; A bit shifter configured to have a number of bits equal to the number of bits of the input data, receive a bit shift amount of the decoding circuit, and input data of the data input unit, and bit-shift the input data by the bit shift amount; A layout structure of a barrel shifter with a decoding circuit, comprising: the control signal input unit and the decoding circuit. A layout in which the control signal input section, the decode circuit, the data input section, and the bit shifter are symmetrically laid out in bit units, the layout being arranged in a row in the horizontal direction. Construction. 2. The layout structure of a barrel shifter with a decode circuit according to claim 1, wherein said decode circuit is laid out adjacent to a side of said control signal input section on the upper bit side. 3. The layout structure of a barrel shifter with a decode circuit according to claim 1, wherein the control signal input section and the decode circuit are laid out above the data input section. 4. The barrel shifter with a decoding circuit according to claim 1, wherein said bit shifter comprises a plurality of bit shift units capable of bit shifting by a predetermined number of bits connected in series. Layout structure. 5. A register file for inputting the plurality of bits of data to the data input unit, wherein the register file includes a bit unit together with the control signal input unit, the decoding circuit, the data input unit, and the bit shifter. 3. The layout structure of a barrel shifter with a decoding circuit according to claim 1, wherein the layout structure is symmetrical.