JP3316470B2 - Digital camera - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital camera, and more particularly to a digital camera for recording, for example, a photographed image signal on a recording medium.

[0002]

2. Description of the Related Art In a conventional digital camera, a subject image is photographed by an image sensor such as a CCD imager, and a photographed image signal is subjected to predetermined signal processing and then recorded on a recording medium by a CPU. Was. While such photographing processing is being performed, the operation of the shutter key has been invalidated.

[0003]

However, after the shutter key is operated and before the recording of the image signal is completed,
It takes a relatively long time. For this reason, in the related art in which the shutter button cannot be operated until recording is completed, there is a problem in operability.

[0004] Therefore, a main object of the present invention is to provide a digital camera capable of improving operability.

[0005]

SUMMARY OF THE INVENTION The present invention provides a photographing means for photographing a subject image, a first input means for inputting a photographing command,
First determining means for determining the presence or absence of a shooting command at a predetermined timing, an internal memory, securing means for securing an image signal corresponding to a subject image in the internal memory in accordance with the determination result of the first determining means, and securing in the internal memory A digital camera provided with recording means for intermittently recording a predetermined amount of image signals on a recording medium by a predetermined amount.

[0006]

When a photographing command is input, the first discriminating means determines that there is a photographing command. Then, the securing unit secures an image signal corresponding to the subject image photographed by the photographing unit in the internal memory. The image signal secured in the internal memory is
The data is intermittently recorded on the recording medium by a predetermined amount by the recording means. The first determination means determines at a predetermined timing whether or not there is a next shooting command.

In one embodiment of the present invention, each time a predetermined amount of image signal is recorded, the first discriminating means discriminates the presence or absence of the next photographing command.

[0008] In one aspect of the present invention, the first remaining capacity detecting means detects the first remaining capacity of the internal memory at a predetermined timing. The disabling means disables the first determining means based on the detected first remaining capacity. That is, the first remaining capacity detecting means detects the first remaining capacity every time a predetermined amount of the image signal is recorded on the recording medium. The comparing means compares the first remaining capacity with the predetermined size, and the disabling means disables the first determining means according to the comparison result of the comparing means.

In another aspect of the present invention, the second remaining capacity detecting means detects the second remaining capacity of the recording medium at a predetermined timing, and the invalidating means invalidates the next photographing command based on the second remaining capacity. In other words, the second remaining capacity detecting means detects the second remaining capacity every time one image signal is secured in the internal memory. The second remaining capacity is the remaining capacity after one image signal has been recorded. In one embodiment of the present invention, the calculating means calculates the number of shootable images based on the second remaining capacity, and the invalidating means invalidates the next photographing command according to the calculation result of the calculating means.

In another aspect of the present invention, when a predetermined command different from the photographing command is input, the second determining means determines that the predetermined command is present. The control means performs predetermined control according to such a determination result. The second determination means determines whether or not there is a next predetermined command each time a predetermined amount of image signal is recorded.

In one embodiment of the present invention, the predetermined command includes a resolution change command, and the control means sets a desired resolution.

[0012]

According to the present invention, the presence or absence of a shooting command is determined even while the image signal secured in the internal memory is being recorded on the recording medium, and the shooting is executed if the shooting command is issued. The operability can be improved as compared with the related art in which the next photographing instruction is received after the completion.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0014]

Referring to FIG. 1, a digital camera 10 of this embodiment includes a CCD imager 15. The CCD imager 15 has about 2 million pixels, and there are 1600 pixels and 1200 lines in the horizontal and vertical directions, respectively. Therefore, in order to read the camera signals of all lines from the CCD imager 15, 1 / 7.5 is required.
A period of seconds is required. The light image of the subject is divided into a zoom lens 12, an aperture 13, and Cy, Ye,
Color filter 14 in which Mg and G are arranged in a mosaic pattern
Irradiates such a CCD imager 15 via the.

When the operator sets the mode switching key 47 to the camera side, the system controller 46 gives the CPU 44 corresponding mode information. Then, CPU4
4 instructs a timing generator (TG) 16 provided in the ASIC 42 to perform thinning-out reading of the camera signal. TG 16 reduces the number of vertical lines to 1/4 to 3
The camera signals for 00 lines are read from the CCD imager 15. When attention is paid to eight vertically continuous lines, the CCD imager 15 outputs only the first Cy, Y... Line and the fourth Mg, G. Can be Therefore, the thinned-out camera signal of 1600 pixels × 300 lines includes the Cy, Ye,.
g, G... are alternately included. Since the number of lines in the vertical direction is thinned to １ ／, this 1600 pixels × 30
The time required to output a 0-line camera signal is
1/30 second.

The camera signal output from the CCD imager 15 is subjected to well-known noise removal and level adjustment by a CDS / AGC circuit 18. A / D converter 20
Converts the camera signal subjected to such processing to 18 MHz
Data (camera data) at a clock rate of
Convert to When the camera mode is set, the switch SW1 is connected to the A / D converter 20 and the switch SW1 is connected.
2 is connected to the thinning circuit 26 side. Further, the thinning rate of the thinning circuit 26 is set to “23/40” and “4/5” in the horizontal direction and the vertical direction, respectively. For this reason, the camera data output from the A / D converter 20 is subjected to color separation and YU
The V conversion is performed, and the number of horizontal pixels and the number of vertical pixels of the YUV data are thinned by the thinning circuit 26 to “920” and “240”. Thus, 920 pixels ×
240 lines of YUV data are generated and the generated Y
The UV data is input to the buffer control circuit 28 via the switch SW2. The CPU 44 also switches the switches SW1 and SW2 and sets the thinning rate of the thinning circuit 26.

The buffer control circuit 28 and the buffer 32 are specifically configured as shown in FIG.
That is, six controllers 28a to 28f are provided in the buffer control circuit 28, and buffers (SRAMs) 32a to 32f are assigned to the respective controllers. Controllers 28a to 28f include counters 29a to 2 respectively.
9f, and these counters 29a to 29f have C
The address data output from the PU 44 is loaded.

On the other hand, as shown in FIG. 4, the SDRAM 30 has 512 addresses in the column direction (horizontal direction) and 8192 addresses in the row direction (vertical direction), and each address has 16 addresses.
Is a bit. When the camera mode is set, the CPU
Reference numeral 44 maps the SDRAM 30 as shown in FIG. That is, a character area of 102 Kbytes, 5
JPEG work area of 2 Kbytes, thumbnail work area of 40 Kbytes, display data area of 504 Kbytes, camera data area of 2408 Kbytes, 460
A 2 Kbyte compressed data area and a 484 Kbyte software work area are formed in the SDRAM 30.

The controller 28a receives the YUV data output from the switch SW2, and writes the YUV data into the buffer 32a at a clock rate of 18 MHz. The controller 28a also receives the head address data of the display data area from the CPU 44,
Set to a. Controller 28a then outputs request signal RQT to SDRAM control circuit 30.
Acknowledgment signal ACK for this request signal and buffer 3
When the identification number (SRAM No.) of 2a is given from the SDRAM control circuit 30, the controller 28a
Converts the YUV data written in the buffer 32a into 72
It outputs to the SDRAM control circuit 30 at a clock rate of MHz. At this time, the address data based on the top address set in the counter 29a is
It is output to the M control circuit 30.

The SDRAM control circuit 30 includes controllers 28b to 28b in addition to the controller 28a.
The request signal RQT output from 8f is provided. Therefore, the SDRAM control circuit 30 accesses the SDRAM 58 while arbitrating each request signal RQT.
All of the controllers 28a to 28f exchange signals or data with the SDRAM control circuit 30 using the bus 66.

The SDRAM control circuit 30 transmits the input YUV data to the SDRAM 58 via a bus 60.
At the desired address. That is, the SDRAM control circuit 30 writes data by so-called burst transfer based on the input address data. The clock rate at the time of writing is 72 MHz.

The YUV data stored in the display data area is read by the SDRAM control circuit 30 when the bus 60 is open. That is, S
Since the DRAM 58 is accessed at a high clock rate of 72 MHz, the YUV data is read while the bus 60 is idle. The SDRAM control circuit 30 uses the same YU to create an image of one frame.
The V data is read twice. At this time, the controller 28b shown in FIG. 3 inputs the address data to the SDRAM control circuit 30,
0 reads the desired data at a clock rate of 72 MHz. The read YUV data is stored in the controller 28
b and the clock rate is returned to 18 MHz in buffer 32b.

YUV output from controller 28b
The data is input to the pseudo framing circuit 34, and each line data is given a predetermined weight. Specifically, 1
The weighting amount for the YUV data input in the first half of the frame period is “0.25”, and the weighting amount for the YUV data input in the second half of one frame period is “0.
As a result, as shown in FIG. 6, odd line data and even line data are pseudo-generated from the respective input line data. The interlaced scan data obtained in this way is 3
After passing through 6, the signal is converted into an analog signal by the D / A converter 38. The analog signal, that is, the interlaced scanned YUV signal is output from the output terminal S1 and input to the LCD 40, and a real-time moving image (through image) is displayed on the LCD 40.

When the operator operates the zoom key 52 while a through image is displayed, the system controller 46 instructs the CPU 44 to move the zoom lens 12. The CPU 44 moves the zoom lens 12 in response to such a movement instruction, whereby a through image with a desired zoom magnification is displayed on the LCD 40. Also,
When the operator operates the dial key 51, the CPU 4
Reference numeral 4 switches the exposure mode among an aperture priority mode, a shutter speed priority mode, and a program AE mode. In this way, a desired zoom magnification and a desired exposure mode are set.

When the operator operates the shutter key 53, the system controller 46 gives a photographing instruction to the CPU 44. Then, the CPU 44 sets the switch S
W1 is connected to the buffer control circuit 28 side, and the switch SW2 is connected to the thinning circuit 22 side. CPU44
Also controls the timing generator 16 so that the camera signals of all lines are output from the CCD imager 15 in an interlaced scan system. by this,
The interlaced scan camera signal for one screen is 1 /
It is output from the CCD imager 15 over 7.5 seconds.
This camera signal is transmitted to the A
/ D converter 20. When the camera signal for one screen described above is output, the CCD imager 15
Disabled by 4.

The camera signal for one screen output from the CCD imager 15 is supplied to the CDS / AGC circuit 18 and A
The signal is input to the thinning circuit 22 via the / D converter 20. At this time, the thinning rate of the thinning circuit 22 is set to “0” in both the vertical and horizontal directions, and the camera data for one screen output from the A / D converter 20 is directly provided to the controller 28a. . In response to the operation of the shutter key 53, the controller 28a
The head address of the camera data area formed in the SDRAM 58 is loaded. As described above, the controller 28a temporarily stores the input camera data in the buffer 32.
a and then, along with the address data,
M control circuit 30. This address data is also generated based on the loaded top address data. Therefore, SDRAM control circuit 30
Writes the input camera data into the camera data area shown in FIG. Since this camera data is interlaced scan data, odd field data is stored in the first half of the camera data area, and even field data is stored in the second half. That is, an odd field area and an even field area are formed in the camera data area.

When the writing of the camera data for all lines is completed, the SDRAM control circuit 30 reads the camera data according to the address data from the controller 28d. At this time, the camera data is alternately read out one line at a time from the odd field area and the even field area, whereby the interlaced scan data is converted to progressive scan data. The SDRAM control circuit 30 supplies the read progressive scan data to the controller 28d, and the controller 28d supplies the input progressive scan data to the signal processing circuit 24 via the switch SW1. As a result, the camera data of Cy, Ye, Mg, and G are subjected to color separation and YUV conversion, and YUV data of 1600 pixels × 1200 lines is generated. The thinning rate of the thinning circuit 26 is set by the CPU 44 to “23/40” and “1/5” in the horizontal direction and the vertical direction, respectively. Therefore, YUV data of 920 pixels × 240 lines is generated from 1600 pixels × 1200 lines of YUV data.

The CPU 44 switches the connection of the switch SW2 to the thinning circuit 26 when the camera data based on the operation of the shutter key 53 is written in the camera data area. Therefore, the YUV data output from the thinning circuit 26 is input again to the controller 28a via the switch SW2. The controller 28a writes the YUV data into the display data area in the same manner as when displaying a through image. Further, at the time when this writing is completed, the controller 28b sets the same YUV
The data is read and output to the pseudo framing circuit 34. As a result, a freeze image at the time when the shutter key 53 is operated is displayed on the LCD 40.

The controller 28d determines that the freeze image is L
After being displayed on the CD 40, the camera data stored in the camera data area is read again. Also at this time, the camera data is alternately read line by line from the odd field area and the even field area. The controller 28d supplies the read progressive scan data to the signal processing circuit 24 via the switch SW1. On the other hand, the CPU 44 sets the thinning rate of the thinning circuit 26 according to the resolution selected by the operator's menu operation. That is, if the selected resolution is “H”
If "Q", the horizontal and vertical thinning rates are set to "0". If the selected resolution is "SQ", the horizontal and vertical thinning rates are set to "2/5".
Therefore, in the HQ mode, 1600 pixels ×
1200 lines of YUV data is returned to the controller 28a, and in the SQ mode, 640 pixels × 480 lines of YUV data
UV data is returned to the controller 28a.

The controller 28a receives the above-mentioned YUV data from the thinning circuit 26,
Receives the start address data of the work area. And
It requests the SDRAM control circuit 30 to write the YUV data. As a result, the YUV data is stored in the JPEG work area. However, the JPEG work area can store only 16 lines of YUV data. Therefore, the 16 lines of YUV data written in the JPEG work area are updated with the subsequent 16 lines of YUV data.

Eight lines of YU are stored in the JPEG work area.
When the V data is written, the CPU 44
The thumbnail data is created from the YUV data for the line. 128 bytes in the first or second half 26 Kbyte area
There are 00 pixels (1600 pixels × 8 lines) of YUV data. Therefore, assuming that 64 pixels (8 pixels × 8 lines) constitute one block, the YUV data in the 26 Kbyte area can be divided into 200 blocks. The CPU 44 is an SD
The SDRAM 58 is accessed via the RAM control circuit 30, and Y data, U data, and V data are read for each block. Then, one pixel of thumbnail data is created from each block. Thereafter, the CPU 44 writes the created thumbnail data via the SDRAM control circuit 30 one pixel at a time in the thumbnail work area shown in FIG. This gives 26
Thumbnail data for 200 pixels is obtained from the YUV data in the K byte area.

When the process of creating thumbnail data for 200 pixels is completed, the SDRAM control circuit 30
According to the address data from the controller 28e, Y data, U data and V
Data is read out one block (8 pixels × 8 lines). The Y data, U data, and V data are individually written in the JPEG work area.
V = 4: 2: 2. Therefore, first, the Y data is read twice for each block, and then the U data and V data are read for each block.

Such a reading process is performed by the controller 2
Each block data repeatedly executed and read by 8e is input to the JPEG codec 56 via the bus 62. That is, block data is repeatedly input to the JPEG codec 56 in the order of Y data, Y data, U data, and V data. JPEG
The codec 56 performs a compression process on the Y data, U data, and V data according to the JPEG format for each block. Then, every time the compression processing for one block is completed, the compressed data is input to the controller 28f via the bus 62. As shown in FIG.
The start address of the compressed data area shown in
The compressed data is written to the compressed data area.

8 stored in one 26 Kbyte area
In parallel with the thumbnail creation process and the compression process for the line of YUV data, the subsequent eight lines of YUV data are written to the other 26 Kbyte area. As a result, the thumbnail creation processing and the compression processing are executed every eight lines. All YUs output from the thinning circuit 22
When the thumbnail creation process and the compression process for the V data are completed, thumbnail data and compressed data corresponding to all the YUV data are secured in the thumbnail work area and the compressed data area.

When the thumbnail creation processing and the compression processing are completed, the CPU 44 reads the thumbnail data from the thumbnail work area and reads the compressed data from the compressed data area through the SDRAM control circuit 30. Then, the thumbnail data and the compressed data are recorded on a removable flash memory (memory card) 55 via the interface 54.

When the operator sets the continuous shooting mode by operating a menu and keeps pressing the shutter key 53, the subject is photographed every predetermined period. That is, CC
From the D imager 15, an interlaced scan camera signal of 1600 pixels × 1200 lines is output intermittently a plurality of times. Then, the same processing as described above is performed on each camera signal, and the corresponding thumbnail data and compressed data are recorded in the flash memory 55.

The system controller 46 specifically processes the flowchart shown in FIG. First, the system controller 46 sets a flag f _{SYS in} step S1,
In step S3, all bits of the key state data are reset. The flag f _SYS is a flag indicating which of the system controller 46 and the CPU 44 has the initiative. By the processing in step S1, the system controller 46 first acquires the initiative. The key state data is data indicating the state of the mode switching key 47, menu key 48, OK key 49, cursor key 50, dial key 51, zoom key 52, and shutter key 53. In step S3, such key state data is initialized.

Subsequently, the system controller 46 scans the keys 47 to 53 in step S5, and determines in step S7 whether or not the key state data has changed. If YES here, step S21
It is determined whether or not the shutter key 21 is on, and in step S23, it is determined whether or not the number of shootable images is "0". Then, steps S21 and S23
Are YES, the shutter operation bit of the key state data is set in step S25.
Then, the process proceeds to step S27. On the other hand, step S21
If either one of S23 and S23 is NO, the process proceeds to step S27 without performing step S25. That is, if the number of shootable images is “0”, the shutter key 5
Operation 3 is invalidated. In step S27, the corresponding bit of the key state data is set according to the key state other than the shutter key 53.

When the initiative is transferred to the CPU 44, the data of the number of recordable frames and the current resolution data corresponding to "HQ" and "SQ" are set from the CPU 46 to the register 46a. In step S23, a determination process is performed based on such data.

The system controller 46 then determines in step S29 whether the flag f _SYS has been set. If it is in the reset state, step S1
Then, the process proceeds to step S31.
Transmits the key state data to the CPU 44, and resets the flag f _SYS in a step S33. Then, the process returns to step S3.

Changed to key state data in step S7
If not, the system controller 46 proceeds to step S7.
Is NO. Then, in step S9, the flag f
_SYSIs determined, and the CPU 44 determines in step S11
Determine if there was any input. Here, the flag f
_SYSIs in the set state or what input from the CPU 44
If not, the system controller 46 proceeds to step S5.
Return to However, the flag f _SYSIs reset and C
If there is any input from PU44, steps S13-
In step S17, the contents of the input are determined.

If the input is a key state request, the system controller 46 determines YES in step S13, and stores the key state data in the CPU 44 in step S19.
Send to Then, the process returns to step S5. On the other hand, if the input is a key state reset request, YES is determined in the step S15, and the process returns to the step S3. If the input is a processing end notification, Y is determined in step S17.
Judge as ES, and return to step S1. If the input does not correspond to any of these, the process returns to step S5.

Therefore, when the initiative is in the system controller 46, key state data is output to the CPU 44 in response to a key operation. After output, the initiative is C
Moving to the PU 44 side, the key state data is reset. Even if the control is transferred to the CPU 44, the key state data is updated according to the key operation, but the data output process is performed in response to the key state request. Such key state data is reset in response to a key state reset request. When the processing end notification is given, the system controller 46 acquires the initiative again.

FIG. 8 to FIG.
This will be described with reference to FIG. The CPU 44 first proceeds to step S41
Then, the remaining capacity of the memory card 55 is detected in step S43. In the following step S45,
The number of images that can be photographed in the HQ mode and the SQ mode is calculated based on the remaining capacity detected in step S43. That is, the YUV data of the photographed subject image is compressed so as to be smaller than a predetermined size, and the predetermined size is defined according to each resolution. Therefore, in step S45, the number of shootable images at each resolution is calculated based on the detected remaining capacity and the above-described predetermined size. CP
The U44 sets the photographable number data and the current resolution data thus obtained in the register 46a of the system controller 46. The resolution immediately after the power is turned on is specified by the initialization processing in step S41.

Subsequently, the CPU 44 outputs a processing end notification to the system controller 46 in a step S49. Thereafter, when key state data is input from the system controller 46, the CPU 44 determines YES in step S51.
Is determined, and the current mode is determined from the bit corresponding to the mode switching key 47 in steps S53 and S55.
If the current mode is the playback mode, the CPU 44 proceeds from step S55 to step S57, performs a playback process, and returns to step S49.

On the other hand, if the current mode is the camera mode, the CPU 44 proceeds from step S53 to step S59, and based on the number of recordable images and the current resolution calculated in step S45, the remaining capacity of the memory card 55 is sufficient. Is determined. If it is determined that the remaining capacity is insufficient, a warning is displayed on the LCD 40 by OSD in step S61, and the process returns to step S49. On the other hand, if the remaining capacity is determined to be sufficient, the through image is
Output to D40. The CPU 44 subsequently proceeds to step S65
At S67, the state of the keys 48 to 53 is determined based on the key state data. If the shutter key 53 is on, the CPU 44 determines YES in step S65, and proceeds to step S69. On the other hand, the shutter key 53
Is OFF, the CPU 44 processes the subroutine shown in FIG. 12 in step S67.

Referring to FIG. 12, when menu key 48 is operated, CPU 44 determines YES in step S201 and determines the display state of the menu in step S203. If the display is on, the menu display is turned off in step S205. If the display is off, step S20.
In step 7, the menu display is turned on, and thereafter, the process returns to the main routine. When the OK key 49 is operated, the CPU 44 determines YES in step S209, and determines the menu display state in step S211. If the display is off, the process returns to the main routine. If the display is on, the menu display is turned off in step S213, the shooting conditions are set in step S215, and the process returns to the main routine. When the cursor keys are operated,
The CPU 44 determines YES in step S217, and determines the display state of the menu in step S219. If the display is off, the process returns to the main routine. If the display is on, the cursor is moved in step S221 and the process returns to the main routine.

The menu has items for resolution and continuous shooting mode on / off. For example, if the OK key 49 is pressed while the cursor is pointing at "HQ", the HQ mode is set in step S215, and if the OK key 49 is pressed while the cursor is pointing at "SQ", a step is performed. In S215, the SQ mode is set. When the OK key 49 is pressed while the cursor points to "continuous shooting mode on", the continuous shooting mode is set in step S215, and when the cursor points to "continuous shooting mode off", the OK button is pressed. When key 49 is pressed, step S2 is performed.
At 15, the continuous shooting mode is released. When the resolution has been changed, the resolution data set in the register 46a is also updated in step S251.

When the dial key 51 is operated, the CPU
44 proceeds from step S223 to step S225,
An exposure mode corresponding to this key operation is set. That is, in the mode selected by the dial key 51,
There are an aperture priority mode, a shutter speed priority mode, and a program AE mode, and any one of these exposure modes is set by a key operation. When the setting is completed, the process returns to the main routine. When the zoom key is operated,
The CPU 44 determines YES in step S229, and moves the zoom lens 12 by a predetermined amount in step S231. Then, the process returns to the main routine. Note that key 4
If none of 8 to 51 is operated, the CPU 44 determines NO in step S229, and returns to the main routine. When the process of step S67 in FIG. 8 is completed in this way, the CPU 44 returns to step S49.

Referring to FIG. 9, in step S69, a photographing process at the current resolution is performed. As a result, compressed data corresponding to the captured subject image is secured in the compressed data area of the SDRAM 58. The CPU 44 determines the size of the compressed data thus obtained in step S71.
Then, in step S73, the remaining capacity of the compressed data area at the present time is detected. Further, in step S75, the memory card 55 after the compressed data (currently compressed data) generated by the process of step S69 is recorded.
Is calculated. For this calculation, the remaining capacity of the memory card 55 and the size of the current compressed data at the present time are used. In step S76, the number of shootable images at each resolution is calculated based on the remaining capacity calculated in step S75. When the respective resolutions are calculated, the flow advances to step S77 to update the data of the number of recordable images set in the register 46a.

Next, the CPU 44 determines whether or not the remaining capacity obtained in steps S73 and S75 is sufficient.
The determination is made in steps S79 and S81. As described above, the captured YUV data of the subject image is compressed to a data size equal to or smaller than a predetermined data size for each resolution. Therefore, in step S79, the data size corresponding to the current resolution is compared with the remaining capacity detected in step S73.
In step S81, the same data size and step S75
Is compared with the remaining capacity calculated in. And SDRAM
Compressed data (next compressed data) obtained by the next photographing process in either one of the memory card 58 and the memory card 55
If you do not have enough free space to write
44 proceeds to step S93.

On the other hand, if both SDRAM 58 and memory card 55 have a remaining capacity to store the next compressed data, CPU 44 proceeds to step S83.
In a step S83, it is determined whether or not the continuous shooting mode is set, and if YES, a key state request is output to the system controller 46 in a step S85. When the key state data is returned from the system controller 46, it is determined in a step S87 whether or not the shutter key 53 is on. If “YES” here, the process returns to the step S69 and the photographing process is repeated. On the other hand, if NO in step S83 or S87, step S8
In step 9, a through image is output to the LCD 40, and step S91 is performed.
Sends a key state reset request to the system controller 4
6 and then go to step S93.

In step S93, all the compressed image data stored in the compressed data area is stored in the memory card 55.
To determine if it has been recorded. If “YES” here, the process returns to the step S43 in FIG. 8, but if “NO”, the process proceeds to a step S95. In step S95, the compressed data secured in the compressed data area and the recording of which has not been completed is 2
Determine if there is more than 0 kilobytes. If NO here, the CPU 44 records the remaining compressed data on the memory card 55 in step S97, and returns to step S93. On the other hand, if the remaining amount of the compressed data is equal to or larger than 20 kilobytes, the CPU 44 records the compressed data of 20 kilobytes on the memory card 55 in step S99. In step S101, the remaining capacity of the compressed data area at the present time is detected, and in step S105, the above-described step S7 is performed.
The same processing as in step 9 is performed.

In step S105, a predetermined data size corresponding to the current resolution is compared with the remaining capacity detected in step S101. Here, if remaining capacity ≧ predetermined data size, it is determined that the next compressed data can be secured in the compressed data area, and the processing after step S109 is performed. First, a through image is output in step S109, and step S111
Outputs a key state request to the system controller 46. On the other hand, when the key state data is returned, a key operation is determined in steps S113 and S119. In step S119, the operation states of the keys 48 to 52 are determined by the subroutine shown in FIG.

If the operated key is the shutter key 53, the CPU 44 determines YES in step S113,
After outputting the key state reset request in step S115, the process proceeds to step S69. On the other hand, keys 48-5
If any one of the keys 2 is operated or none of the keys 48 to 52 is operated, the process proceeds to the step S121 via the step S119. After outputting the key state reset request, the process returns to step S93.

As described above, if the SDRAM 58 has a sufficient remaining capacity, various keys 4 including the shutter key 53
The presence / absence of operations 8 to 53 is determined, and processing according to the determination result is executed. That is, if the shutter key 53 is operated, the photographing process is executed, and if the other keys 48 to 52 are operated, the corresponding control is executed.

On the other hand, if it is determined in step S105 that the remaining capacity is smaller than the predetermined data size, the CPU 44 proceeds to step S1.
In step 17, a key state request is output, and the flow advances to step S119. That is, since the SDRAM 58 does not have a sufficient capacity to secure the next compressed data, the shutter key 5
The presence or absence of operation 3 (the presence or absence of a shooting command) is not determined, and only control corresponding to the operation of keys 48 to 52 is performed. Upon completion of the process in the step S119, the CPU 44 outputs a key state reset request in a step S121, and thereafter, returns to the step S93.

As can be understood from the above description, when the shutter key 53 is operated by the operator, the DMA (Di.
rect Memory Access), the YUV data corresponding to the subject image at the time of the operation is subjected to JPEG compression, and the compressed data is secured in the compressed data area of the SDRAM 58. The CPU 44 intermittently records the compressed data secured in the SDRAM 58 on the memory card 55 by 20 kilobytes at a time, and determines the presence or absence of a photographing command between recordings. Then, when it is determined that there is a shooting command, the same shooting process is executed, and the compressed data is secured in the compressed data area of the SDRAM 58. Therefore, operability can be improved as compared with the related art in which the next photographing instruction is received after the recording is completed.

If the remaining capacity of the compressed data area is smaller than the maximum size of the compressed data obtained at the current resolution, the CPU 44 disables the next photographing instruction determination process. If the remaining capacity of the memory card 55 is smaller than the maximum size of the compressed data obtained at the current resolution, the system controller 46 invalidates the shooting command. For this reason, it is possible to prevent a situation where the photographed subject image is not recorded.

The thumbnail data secured in the thumbnail work area of the SDRAM 58 is recorded on the memory card 55 before recording of the compressed data is started.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an illustrative view showing a complementary color filter;

FIG. 3 is an illustrative view showing a buffer control circuit;

FIG. 4 is an illustrative view showing an SDRAM;

FIG. 5 is an illustrative view showing a mapping state of an SDRAM;

FIG. 6 is an illustrative view showing another portion of the operation of the embodiment in FIG. 1;

FIG. 7 is an illustrative view showing one portion of an operation of a system controller;

FIG. 8 is an illustrative view showing one portion of an operation of a CPU;

FIG. 9 is an illustrative view showing another portion of the operation of the CPU;

FIG. 10 is an illustrative view showing another portion of the operation of the CPU;

FIG. 11 is an illustrative view showing still another portion of the operation of the CPU;

FIG. 12 is an illustrative view showing another portion of the operation of the CPU;

[Explanation of symbols]

 10 Digital camera 44 CPU 46 System controller 55 Flash memory 56 JPEG codec 58 SDRAM

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-95483 (JP, A) JP-A-10-42250 (JP, A) JP-A-10-308920 (JP, A) JP-A-4- 268284 (JP, A) JP-A-10-304306 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/225 H04N 5/907

Claims (15)

(57) [Claims] 1. A photographing means for photographing a subject image, a first input means for inputting a photographing command, a first discriminating means for discriminating the presence or absence of the photographing command at a predetermined timing, an internal memory, a discrimination result of the first discriminating means Securing means for securing an image signal corresponding to the subject image in the internal memory in accordance with
And a recording means for intermittently recording the image signal secured in the internal memory by a predetermined amount on a recording medium. 2. The digital camera according to claim 1, wherein said first discriminating means discriminates the presence or absence of said photographing command every time said predetermined amount of image signal is recorded. A first remaining capacity detecting means for detecting a first remaining capacity of the internal memory at a predetermined timing; and a disabling means for disabling the first determining means based on the first remaining capacity. The digital camera according to claim 1. 4. The digital camera according to claim 3, wherein said first remaining capacity detecting means detects said first remaining capacity each time said predetermined amount of image signal is recorded. 5. The apparatus according to claim 3, further comprising comparing means for comparing said first remaining capacity with a predetermined size, wherein said disabling means disables said first discriminating means in accordance with a comparison result of said comparing means. 4. The digital camera according to 4. 6. An image processing apparatus according to claim 1, wherein said securing means compresses an image signal output from said photographing means to a predetermined size or less, and a writing means for writing the compressed image signal generated by said compressing means to said internal memory. The digital camera according to claim 5, comprising: 7. The digital camera according to claim 5, wherein said predetermined size differs according to a resolution of said image signal. 8. The apparatus according to claim 1, further comprising a second remaining capacity detecting means for detecting a second remaining capacity of the recording medium at a predetermined timing, and invalidating means for invalidating a next photographing command based on the second remaining capacity. 8. The digital camera according to any one of 1 to 7. 9. The digital camera according to claim 8, wherein said second remaining capacity detecting means detects said second remaining capacity every time one image signal for one sheet is secured in said internal memory. 10. The digital camera according to claim 9, wherein said second remaining capacity is the remaining capacity after said one image signal has been recorded. 11. The apparatus according to claim 8, further comprising a calculating unit that calculates the number of images that can be photographed based on the second remaining capacity, wherein the invalidating unit invalidates the next photographing command according to a calculation result of the calculating unit. 11. The digital camera according to any one of claims 10 to 10. 12. The digital camera according to claim 11, wherein said calculating means calculates said number of recordable images based on said second remaining capacity and a predetermined size. 13. A second input means for inputting a predetermined command different from the photographing command, a second discriminating means for discriminating the presence or absence of the predetermined command at a predetermined timing, and a predetermined signal in accordance with a result of the discrimination by the second discriminating means. 13. The digital camera according to claim 1, further comprising control means for performing control. 14. The digital camera according to claim 12, wherein said second determining means determines whether or not said predetermined command is issued each time said predetermined amount of image signal is recorded. 15. The digital camera according to claim 13, wherein said predetermined command includes a resolution change command, and said control means sets a desired resolution.