JP3312650B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device , and more particularly, to a novel method for forming a Cu damascene wiring.

[0002]

2. Description of the Related Art In a process of forming a Cu damascene wiring of a semiconductor device , in order to obtain in-plane uniformity of wiring resistance, C
Reduction of in-plane variation of u-CMP is required. For this reason, it is desired to improve the in-plane film thickness uniformity in the Cu plating step, which is a pre-step of the CMP.

[0003]

In the above-described Cu plating process, the in-plane uniformity of the thickness of the Cu plating largely depends on the resistance value of the plating base. This is advantageous for thickness uniformity. However, the profile of the seed film in the via or trench has a larger thickness at the opening than at the bottom of the pattern, and as the thickness of the seed film increases, it becomes more difficult to bury the seed film in the fine pattern. Therefore, there has been a demand for a method of lowering the resistance value of the plating base without increasing the seed film thickness. Further, as another approach for improving the in-plane uniformity of wiring resistance, there is a demand for dishing improvement during Cu-CMP, and measures from a total process have also been required.

The present invention has been made in view of the above-mentioned circumstances, and in the Cu plating step of the Cu damascene wiring formation process, a Cu electrolytic plated film having a good film thickness in-plane distribution can be obtained. Cu with excellent internal uniformity
An object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming a damascene wiring.

[0005]

According to the present invention, in order to achieve the above object , an etching stopper film, an interlayer film , a base film of an IR loss reducing film, and an IR loss reducing film are sequentially formed on a semiconductor substrate.
Next, a step of forming a film , and then, a photoresist is patterned to a desired pattern.
The IR loss reduction film, the underlayer, and the layer.
Forming a trench pattern or a via pattern by etching the interlayer film and the etching stopper film ;
After removing the photoresist, a step of forming a barrier film and a seed film over the entire surface of the semiconductor substrate ;
Functioning as a base for electrolytic plating, C
forming a u-plated film, the Cu-plated film,
A seed layer, the barrier layer, the IR loss reducing film, the underlayer
The film is removed by CMP to form Cu damascene wiring
And a method for manufacturing a semiconductor device .

FIGS. 1A to 1D are sectional views showing the present invention in the order of steps. FIG. 1A shows a state in which after a stopper film 2 for etching, an interlayer film 3, an IR loss reduction film 5, and a base film 4 thereof are laminated on a substrate 1, a photoresist 6 is patterned into a desired shape. It is a thing. As shown in FIG. 1A, the IR loss reduction film 5, the base film 4, the interlayer film 3,
FIGS. 1B and 1C are cross-sectional views after the stopper film 2 is removed by dry etching, and FIGS. 1C and 1C are cross-sectional views after the photoresist 6 is removed from FIG. 1B. FIG. 1D is a cross-sectional view after the film 7 and the seed film 8 are formed.

According to the method of forming a Cu damascene wiring of the present invention, it is possible to perform Cu electrolytic plating having a good thickness distribution in a plane without depending on the thickness or specific resistance of the seed film 8. Also, Cu
If a film having a high selectivity with respect to the above is used as the IR loss reduction film 5, a dishing prevention effect can be also obtained in the subsequent CMP process.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments. A method for manufacturing a semiconductor device according to the first embodiment will be described with reference to FIGS. FIG. 2 (a)
Is formed on a lower substrate composed of a semiconductor substrate 9, a W via 10, and a SiO ₂ film 11 by using Si for the purpose of etching stop.
N film 12, SiO ₂ film 13 as an interlayer film, Cu film 15 for reducing IR loss, and TaN film 1 as a base film thereof
4 is a cross-sectional view after a film is formed and a photoresist 16 is formed in a desired pattern.

As shown in FIG. 2A, the Cu film 15, the TaN film 1
4. When the SiO ₂ film 13 and the SiN film 12 are removed by dry etching, the cross-sectional shape of FIG. 2B is obtained. FIG.
2 (b), when the photoresist 16 is removed, FIG.
2C. When the TaN film 17 as the barrier layer and the Cu film 18 as the seed layer are formed from FIG. 2C, the cross-sectional shape in FIG. can get.

Compared with the conventional manufacturing method using only the TaN film 17 and the Cu film 18 as the base for Cu electrolytic plating, the substrate having the cross-sectional shape of FIG.
In addition to the TaN film 17 and the Cu film 18, the TaN film 14, C
The u film 15 also functions as a base for Cu electrolytic plating. Cu
In electrolytic plating, the contact between the electrode of the device and the wafer is mostly made near the wafer edge,
In addition, since constant current plating is the mainstream, IR loss (voltage drop) from the wafer edge to the wafer center is almost proportional to the resistance value of the plating base. Therefore, in the manufacturing method of the present embodiment in which the resistance value of the plating underlayer can be reduced, it is possible to perform Cu electrolytic plating with a good film thickness in-plane distribution without depending on the plating underlayer, that is, the thickness or specific resistance of the Cu film 18. Becomes

That is, as described above, in the current Cu electrolytic plating, the contact between the electrode of the apparatus and the wafer is mostly made near the wafer edge, and the constant current plating is mainly used. During the electroplating using the above apparatus, the potential at the position a of the wafer center is V (a), the potential at the position b of the wafer edge is V (b), the current flowing between a and I is I, the plating base resistance between a and ab. Assuming that the value is R, the relationship between V (a) and V (b) can be approximated by | V (b) -V (a) | = IR. Therefore, in constant current electrolysis, V (a) and V (b)
, That is, the difference between the deposition rates at the positions a and b depends on the resistance value R of the plating base. In the method of manufacturing the semiconductor device according to the present embodiment, the TaN film 14 and the Cu film 15 also function as the Cu electroplating base in addition to the TaN film 17 and the Cu film 18, so that the resistance R of the plating base is significantly reduced. Is done. Therefore, the potential difference between the wafer center and the wafer edge, that is, the difference between the film forming rates is reduced.

According to the structure of this embodiment, the potential difference between the wafer center and the wafer edge, that is, the difference between the film formation rates is reduced as in the operation of the above embodiment, without depending on the thickness or specific resistance of the seed film. Is possible,
A Cu electrolytic plating film having a good thickness distribution in the plane can be obtained.

A method of manufacturing a semiconductor device according to a second embodiment will be described with reference to FIGS. 3 (a) to 3 (c) and 4 (d) to 4 (f). FIG. 3A shows a semiconductor substrate 9, a W via 10,
A lower layer on a substrate of SiO ₂ film 11, SiN film 12 for the purpose of etching stopper, Si as an interlayer film
FIG. 3 is a cross-sectional view after forming an O ₂ film 13, a W film 20 for the purpose of reducing IR loss, and a Ti / TiN film 19 as a base film thereof, and forming a photoresist 16 in a desired pattern.

FIG. 3A shows that the W film 20, Ti / TiN
When the film 19, the SiO ₂ film 13, and the SiN film 12 are removed by dry etching, the cross-sectional shape of FIG. 3B is obtained.
From FIG. 3B, when the photoresist 16 is removed, FIG.
3C. When the TaN film 17 as the barrier layer and the Cu film 18 as the seed layer are formed from FIG. 3C, the cross-sectional shape of FIG. can get. In the present embodiment, similarly to the first embodiment, it is possible to perform Cu electrolytic plating with a good film thickness in-plane distribution without depending on the plating base, that is, the thickness or specific resistance of the Cu film 18.

FIG. 4 (e) shows that Cu
FIG. 4F is a cross-sectional view after plating, and FIG.
(E) From Cu plating film 21, Cu film 18, TaN film 1
7 is a cross-sectional view after the W film 20 and the Ti / TiN film 19 have been removed by CMP. W film 20 and Ti / TiN film 1
When CMP is performed by using CMP, slurry and polishing conditions having a small selectivity to Cu can be used to prevent dishing of the Cu wiring, prevent particles from remaining in the Cu wiring, and reduce wiring resistance. It also contributes to the improvement of internal uniformity.

In the above embodiment, the IR loss reduction film is made of C
The film is formed of u and W, but may be formed of, for example, Al or AlCu. In the above embodiment, the base film of the IR loss reduction film is formed of TaN or Ti / TiN, but may be formed of, for example, Ta or Ta / TaN. further,
Other configurations may be variously changed without departing from the gist of the present invention.

[0017]

According to the present invention, in the Cu plating step of the Cu damascene wiring forming process, a Cu electrolytic plating film having a good film thickness in-plane distribution can be obtained, and the Cu damascene having excellent in-plane uniformity of wiring resistance can be obtained. Wiring can be formed. If a film having a high selectivity to Cu is used for the IR loss reduction film, the effect of preventing dishing can also be obtained in the subsequent CMP process.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the present invention in the order of steps.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing the semiconductor device in Example 1 in the order of steps.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the second embodiment in the order of steps;

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in Example 2 in the order of steps.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Substrate 2 Stopper film 3 Interlayer film 4 Underlayer film 5 IR loss reduction film 6 Photoresist 7 Barrier film 8 Seed film 9 Semiconductor substrate 10 W via 11 SiO ₂ film 12 SiN film 13 SiO ₂ film 14 TaN film 15 Cu film 16 Photo Resist 17 TaN film 18 Cu film 19 Ti / TiN film 20 W film 21 Cu plating film

──────────────────────────────────────────────────続 き Continued on the front page (58) Investigated field (Int. Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/768 H01L 21/3213 H01L 21/28 301

Claims (4)

(57) [Claims] An etching stopper film, an interlayer film , a base film of an IR loss reducing film, and an IR loss reducing film are sequentially formed on a semiconductor substrate.
Next, a step of forming a film , and then, a photoresist is patterned to a desired pattern.
The IR loss reduction film, the underlayer, and the layer.
Forming a trench pattern or a via pattern by etching the interlayer film and the etching stopper film ;
After removing the photoresist, a step of forming a barrier film and a seed film over the entire surface of the semiconductor substrate ;
Functioning as a base for electrolytic plating, C
forming a u-plated film, the Cu-plated film,
A seed layer, the barrier layer, the IR loss reducing film, the underlayer
The film is removed by CMP to form Cu damascene wiring
And a method of manufacturing a semiconductor device . 2. A method of manufacturing a semiconductor device according to claim 1, characterized in that formed by the IR loss reducing film Cu, W, Al or AlCu. 3. The method according to claim 1, wherein the underlayer is made of TaN, Ti / TiN, T
3. The method of manufacturing a semiconductor device according to claim 1, wherein the film is formed by a or Ta / TaN. 4. The method according to claim 1, wherein the IR loss reduction film and the underlayer are made of CM.
Slurry with a small selectivity to Cu when treating with P
And polishing conditions are used.
A method for manufacturing a semiconductor device according to claim 3.