JP3311624B2 - Barrel shifter control method and integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a barrel shifter, and more particularly, to a high speed conversion of a two's complement coded shift value for controlling a barrel shifter.

[0002]

2. Description of the Related Art N-bit barrel shifters (where N
Is a combinational logic circuit having N digit data input bits, N digit data output bits, and N digit control inputs, which are encoded into log ₂ N bits. I have. The N digit data input bits are the input word. The N data output bits are the input word, which is determined by the control input and is rotated or shifted by the number of bit positions, ie, the shift value. The barrel shifter is used to shift either left or right, and the shift value is + (N-1)
And any value in the range from-(N-1) to.

[0003] The barrel shifter shifts left only, shifts right only, or shifts left or right only. 1
Rather than providing two barrel shifters, one for left shift and another for right shift, the barrel shifter usually has the appropriate multiplexing function to either shift left or right. Such a barrel shifter is called a bidirectional barrel shifter. Bi-directional barrel shifters increase the variety of system designs because they often do not know the shift value and shift direction in advance. Thus, both the shift value and the shift direction need to be supplied to the bidirectional barrel shifter as control inputs. The following four combinations can be considered for two input quantities. That is, a positive right shift, a negative right shift (this is actually a left shift),
A positive left shift and a negative left shift (which is actually a right shift). A barrel shifter has a primary shift direction, and shifting in the other direction requires converting the shift value to a value that is the difference between the bit width of the barrel shifter and the shift value. The barrel shifter causes the data path to be single stage and decodes the m-bit shift value into 2 ^m -1 control bits to control the barrel shifter.

[0004] The barrel shifter can perform an arithmetic shift and a logical shift together with a rotate operation (rotation operation). In a left shift, each bit of the input word is shifted left by the number of bit positions indicated by the shift value to produce an output word. The low order bits of the output word are zero filled. In a right shift,
Each bit of the input word is shifted to the right by the number of bit positions indicated by the shift value, producing an output word. The higher order bits are for the sign extension in arithmetic shifts and are filled with zeros in logical shifts. In the rotation operation, each bit shifted out from one end of the word appears again shifted in and into the other end of the word.

[0005] Calculations in the digital signal processor are performed by hardware that performs two's complement arithmetic.
The shift value must be represented by a two's complement system, which is the radix complement of a binary number. The two's complement representation of a number can be obtained by performing a complement operation on each digit from the binary representation and adding one. In a two's complement system, the most significant bit is 1 for negative numbers and 0 for positive numbers. Zero is considered positive because its sign is positive. m
In the case of the bit representation, the range of the number is from − (2 ^m−1 ) to + (2
^m-1 -1), and only one negative number -2 ^m-1 has no corresponding number on the positive side.

FIG. 3 shows a schematic diagram of a prior art circuit for controlling a barrel shifter, which is derived from a binary representation using an exclusive OR gate (EOR gate) and an adder as shown. A two's complement representation of a number can be made. The shift direction is 0 for right shift and 1 for left shift.
It is expressed as The shift direction 302 corresponds to the sign bit 30 of the shift value 308 in the exclusive OR gate 300.
4 to create a modified shift direction 306. This sign bit 304 is 0 for positive shift values.
Where 1 is a negative shift value. The bit of the shift value 308 is XORed with the shift direction 302 by EOR gates 310 _{0 to} 310 _{m -1} and 311, and the output 312 is output.
Make the one's complement of the bits. To accommodate the shift direction, either the shift of the barrel shifter in the main direction, 0, or the bit width of the barrel shifter is selected by the multiplexer 316, controlled by the select input 306, and shifted by the full adder 318. Added to the two's complement representation of the value. The shift direction 302 is added to the one's complement representation and either 0 or the bit width of the barrel shifter 314, as selected by the multiplexer 316, in a full adder 318, and the shift value 2 of the shift value is output 320. Create the complement representation. The most significant bit of output 320 is discarded. The output from full adder 318 is always positive.
The low order m bits of output 320 of full adder 318 are the encoded shift values, which are decoded by decoder 324 and provided with an N digit control signal 326 used to control barrel shifter 314. You. Barrel shifter 314 also receives the modified shift direction 306 directly and produces a shifted version of input word 328 as its output 330 in response to control input 326.

[0007]

Such a conventional technique has a disadvantage in that a delay occurs in producing an N-digit control signal used to control the barrel shifter 314. This delay is caused by the operation of the adder 318. The delay in creating the control input to the barrel shifter will cause a delay in the operation of the barrel shifter. An object of the present invention is to provide a barrel shifter that performs high-speed conversion without causing such a delay.

[0008]

SUMMARY OF THE INVENTION A barrel shifter control method and integrated circuit of the present invention are provided for controlling an N-bit barrel shifter to shift bits of an input word by a shift value. The method performs a one's complement operation of an m-bit binary representation of the shift value to generate an input if the shift direction is the first direction, and this binary value of the shift value if the shift direction is the second direction. Passing the representation as an input, decoding the input into a 2 ^m control signal, generating a plurality of control signal groups from the 2 ^m control signal, and controlling the barrel shifter. And selecting one of the control signal groups. The bits of the binary representation of the shift value are
Passed through an OR gate and provided as input to the first decoder. The first decoder decodes this input into a plurality of bits used as control signals. The control signals are divided into a plurality of groups. Some of the control signals are padded with other control signals to provide zero padding. Based on the selection input, the multiplexer selects which of a plurality of control signals to pass to control the barrel shifter. A second decoder decodes the sign of the shift direction and the shift value and provides a select input to the multiplexer.

[0009]

FIG. 1 shows a control circuit 10 for controlling a barrel shifter such as a bidirectional barrel shifter 22 according to an embodiment of the present invention. The control circuit 10 includes a modified shift direction generator, a complement generator of the EOR gates 12 and 1, and
The one's complement generator has EOR gates 14 _{0 to} 14 _{m -1} ,
It comprises decoders 16 and 18 and a multiplexer 20. The control circuit 10 is made on an integrated circuit chip. The control circuit 10 is a part of an integrated circuit such as a microprocessor and a digital signal processor.

The control circuit 10 includes a positive right shift, a negative right shift (which is actually a left shift), a positive left shift,
And four possible control requests of negative left shift (which is actually a right shift) need to be handled. In the preferred embodiment, barrel shifter 22 is a bi-directional barrel shifter that can handle both right and left shifts of an N-bit input word 24 and produce an N-bit shift output word 26.

The inputs to control circuit 10 are shift value 30 and shift direction 32. The shift value 30 is the shift value m.
It is a bit binary representation. The most significant bit is a sign bit, which is usually 1 for a negative shift value and 0 for a positive shift value. The shift direction is either left or right, requiring only one bit to represent. In the embodiment, a left shift is represented by 1 and a right shift is represented by 0.

The sign bit 28 and the shift direction 32 of the shift value 30 provide an input to the EOR gate 12 which
The OR gate 12 combines the respective inputs and supplies as its output the modified shift direction 34, which is the exclusive OR combination.
This modified shift direction 34 is provided as an input to barrel shifter 22. The EOR gate 12 controls the shift direction 3
2 and the sign bit 28 of the shift value are decoded, and the following first
As shown in the table, a modified shift direction 12, which is an exclusive OR combination of each input, is created.

[0013]

[Table 1]

The EOR gates 14 are a plurality of m EOR gates corresponding to the number of bits of the shift value 30.
Each EOR gate 14 ₀ -14 _m-1 receives the shift direction 32 as one input and one of the m bits of the shift value 30 as the other input, and combines those inputs to produce a corresponding output. The output 36 from the EOR gates 14 ₀ -14 _m-1 is m bits representing the one's complement of the binary representation of the shift value 30.

The m bit, one's complement output from EOR gates 14 ₀ -14 _{m -1} provides an input to decoder 16. The decoder 16 (m TO 2 ^m decoder) is a combinational logic circuit that decodes an m-bit one's complement into an output of a 2 ^m decoded control signal 38, which is supplied to the barrel shifter 22. You. 1 of 2 ^m output
One is high and the other 2 ^m -1 outputs are low. In the preferred embodiment, the output that is high is the output represented by the binary input to decoder 16. For example, Table 2 below shows that from a 3-bit binary input, C
The content of decoding into eight outputs represented by L0 to CL7 is shown.

[0016]

[Table 2]

The present invention takes advantage of the decoding operation performed after the one's complement operation. As can be seen from Table 2, incrementing the decoder output by one is equivalent to shifting the decoder output control line, one of the higher order control lines, to the left. In the example in Table 2, it is not possible to increment the input to the decoder by 1 and pad it to the right with 0, such as from 3 ₁₀ (011 ₂ ) to 4 ₁₀ (100 ₂ ) (binary number in parentheses) ,
The output of the higher control line is shifted from the state where CL3 is higher to the state where control line CL4 is higher. Zero padding, such as by coupling a hard wire to VSS, keeps all but one control output 38 low. The shift direction differs depending on how the right or left shift is represented.

The decoder 18 (2 TO 4 decoder)
It is a combinational logic circuit that decodes a bit input into four outputs. In each combination of the two bit inputs, one of the four outputs 50 is high and the other three are low. Shift direction 32 and sign bit 2 of shift value 30
8 is decoded by decoder 18 and provides four select inputs 50 to multiplexer 20. These four selection inputs 5
0 selects one of the four inputs 40, 42, 44, 46 as the output 52 of the multiplexer 20. This selection input 50 is used for the operation of one's complement evaluation and the decoder 16.
And the delay of the operation of the control circuit 10 and therefore of the barrel shifter 22 can be minimized. In Table 3,
Decoding from two inputs to four outputs is shown. Here, the numerals shown in the item of the input to be selected are the symbols used in FIG.

[0019]

[Table 3]

The decoder 16 receives the m input bits and decodes the ^m input bits into 2 ^m outputs 38 to control the barrel shifter 22. This barrel shifter 22 has a bit width of N digits (where N ≦
2 ^m ). N = 2 ^m representing a decoder full and high
For all bit widths, a shift value of − (N−1) to (N−1) is used, which may be the entire range of 2 ^m . If it is smaller than the high and full decoder, all possible 2 ^m shift values are not used.

Four control signal groups 40, 42, 44, 46
Is supplied as an input to the multi-bit multiplexer 20. Each of the four control signal groups is obtained from 2 ^m outputs 38 by connection logic (hard wire) or the like. Each of the 2 ^m outputs 38 forming control signals 40, 42, 44, 46 is generated corresponding to each received shift value and shift direction. The multiplexer 20
It is used to select the appropriate output 38 and provides it as a control signal 52 to the barrel shifter 22. This control signal 52
Thus, N control signals are supplied to the barrel shifter 22 on the control lines 0 to (N−1).

The control signal 40 is selected when both the shift direction and the sign bit are zero, ie, when the shift direction is right and the shift value is positive. This is the positive right shift, the primary shift direction of the bi-directional barrel shifter 22 in the preferred embodiment. The control signal 40 is selected from 2 ^m control signals 38 generated by the decoder 16. The input to the decoder 16 is a shift value having a range of [0, (N-1)] because it causes a positive right shift. The notation of this range is as follows: control lines 0 to (N
-1) It means that the control signal 38 output upward is selected as the control signal 40 by connection logic or the like. Also, using another notation notation indicating the range of the control signal 38 selected as the control signal 40, [LSB: MSB] is changed to [0: (N−1)] as shown by “Range 1” in FIG. (Where LSB is the least significant bit,
The MSB is the most significant bit).

The control signal 42 is selected when the shift direction is 0 and the shift bit is 1, that is, when the shift direction is right and the shift value is negative. This negative right shift is actually a left shift. Then, the control signal 42 is selected from the 2 ^m control signals 38 generated by the decoder 16. Since a negative right shift is performed, the decoder 16
Has the range | 0, (N−1)]. FIG.
Control line [2 ^“log ₂ ^N” -(N-
1): 2 The control signal 38 output from the ^“log ₂ ^N” −1, VSS] decoder 16 is selected as the control signal 42 by connection logic or the like. In the above range description, the expression “log ₂ N”, which is a power of 2, represents a sealing function, and non-integer values are rounded up to the next larger integer. The control signal 38 is modified to be a control signal 42 by subtracting 1 by a connection logic, etc. Here,
The control signal 38 is shifted by one digit, which is equivalent to decrementing by one. Using the method of the embodiment, the control signal 38
Is shifted to the right one line, producing a control signal 42. Shifting the control signal 38 to the one line to the right is the same as subtracting one from the one's complement representation of the shift value. The control signal 42 is selected and supplied according to the selection input 50 to the bidirectional barrel shifter 22 through the multiplexer 20.

The control signal 44 is selected when the shift direction is 1 and the sign bit is 0, that is, when the shift direction is left and the shift value is positive. This represents a positive left shift. The control signal 44 is selected from the 2 ^m control signal 38 generated by the decoder 16. To make a positive left shift, the input to decoder 16 is the one's complement of the shift value. The one's complement sign of the shift value is not used. The control line [2 ^“log ₂ ^N” −N: 2 indicated by “range 3” in FIG.
^The output of the control signal 38 from the decoder 16 of ^"log ₂ ^N" -1] is selected as the control signal 42 by connection logic or the like. Control signal 44 is provided through multiplexer 20 to bidirectional barrel shifter 22 as selected at select input 50.

The control signal 46 is selected when the shift direction is 1 and the sign bit is 1, that is, when the shift direction is left and the shift value is negative. A negative left shift actually represents a right shift. The control signal 46 is selected from the 2 ^m control signal 38 generated by the decoder 16. To perform a negative left shift, the input to decoder 16 is the one's complement of the shift value. To get the two's complement representation from the binary representation,
A one's complement is taken and one is added to the one's complement. Since the one's complement of the negative shift value was generated as an input to the decoder 16, only one need be added. This can be achieved by shifting the output of the decoder 16 by one control line as described above. The control signal 38 output from the decoder 16 of the control line [VSS, 0: (N−1)] indicated by “Range 4” in FIG.
6 is selected. VSS represents the zero padding required by the shift. The input shift value for negative left shift is
-1 to-(N-1). Control signal 44
Is transmitted through the multiplexer 20 to the two-way barrel shifter 2.
2 is selected and supplied according to the selection input 50.

As shown, the main shift direction (left)
Control line [0: (N-1)]
A (range 1) control signal 38 is selected to control the barrel shifter 22. If the shift value is negative, the control line output by the decoder 16 is shifted, and a control signal to be supplied to the multiplexer 20 is generated. If the shift direction is not the primary shift direction, the one's complement of the shift value is provided as an input to decoder 16.

FIG. 2 shows the decoder 16 and the multiplexer 2
FIG. 5 is a schematic diagram illustrating 0, connection logic (path) shift, and zero padding. FIG. 2 further illustrates a technique for laying out the present invention on a chip. For example, a barrel shifter having a bit width of 40 requires 6 bits to represent the shift value, except for the sign bit. The decoder 16 has bits 0 to 63
Produces 64 outputs 52 represented by The decoder 16 comprises 2 ^m cells, represented as output numbers in FIG. Each cell of the decoder 16 is manufactured on-pitch so as to achieve a connection logical shift. Bit 63 of the decoder is
It must be able to be supplied as an input to both cells 39 and 38 of multi-bit multiplexer 20. . Similarly, bit 62 needs to be available as an input to both cells 38 and 37 of multiplexer 20, and bit 38 needs to be available as an input to both cells 39 and 38 of multi-bit multiplexer 20. There is. The VSS is supplied as one of the inputs to each of the cells 39 and 0 of the multiplexer 20, and performs zero padding when adding 1 by a shift operation. The four inputs to each cell of the multiplexer 20 are, from left to right in FIG.
2, 44, 46.

Also, instead of manufacturing the cell decoders 16 of 0 to 63 at an on-pitch, cells 0 to 3 of the decoder 16 are
9 can be manufactured on-pitch with the corresponding 0-39 cells of the multiplexer 20. The decoder cells 24-39
Duplicated to form the decoder 16
And the decoder cells 0 to 15 of the multiplexer 20 (in the horizontal direction), and are mounted on the cells 16 to 39. The cells 40 to 63 of the decoder 16 are
Line up with the corresponding one of the 39, and rest on cells 16-39.

Since the decoders are stacked (stacked) in this manner, the amount of path shift can be suppressed. For a positive shift to the right, the output bits from cells 0-39 of decoder 16 provide a direct input at the same pitch (pitch match) to cells 0-39 of multiplexer 20 via a path. No shift is performed. These are the cases of the control signal 40 in FIG.

In the case of the left negative shift, the output bits from the cells 0 to 38 of the decoder 16 are output to the cells 1 to 3 of the multiplexer 20 at the same pitch and shifted by one unit of the pitch.
9 is provided as an input to. Here, ground (VSS) is input to the cell 0 of the multiplexer 20. At the output of the decoder 16, 1
Only one conductor (metal, etc.) path is required.

For the left positive shift, the output bits from cells 24-63 of decoder 16 provide the direct input to cells 0-39 of multiplexer 20 of the same pitch without path shifting. These are control signals 44.

In the case of a negative shift right, the output bits from cells 25-63 of decoder 16 are provided as inputs to cells 0-38 at the same pitch and shifted by one unit of the pitch. Here, the ground is supplied to the cell 39 of the multiplexer 20. It is not necessary to shift only one conductor path in the opposite direction of the path shift. A path shift to a negative right shift is the opposite of a path shift to a negative left shift.

If N is a power of two, only one row of decoder cells is needed and the cells are no longer double. However, two path shifts are still required.

The N-digit output control signal 52 supplied by the multiplexer 20 is supplied to the barrel shifter 22,
Control this. Also, another control input is barrel shifter 2
2 is supplied.

Although the embodiment controls the bidirectional barrel shifter, a right-shift or left-shift barrel shifter may be used.

In the barrel shifter control circuit, 0 does not need to indicate the right shift direction and 1 does not indicate the left shift direction, and the sign bit of 0 indicates a positive shift value and the 1 shift bit indicates a negative shift value. It doesn't have to be something. Further, the barrel shifter control circuit may be one in which the main shift (sign bit 0 and shift direction 0) is not positive on the right. A method other than the connection logic may be used to correct the decoder output. While one decoder output is shown as high and the remaining outputs as low, the design may be based on the opposite or other combination of states. In such a barrel shifter, it is necessary to fill not with a low logical value but with a high logical value.

The present invention is particularly useful in communication systems and devices that use integrated circuits, which eliminates the delay of adders, usually ripple adders, and where the multiplexer input is set up during the operation of the decoder. , The adder delay can be replaced by a multiplexer delay. Also, when used in an integrated circuit, the barrel shifter can be operated faster than the control circuit of the prior art, and high-speed right and left shift or rotation operations can be performed.

The present invention takes advantage of the advantages of the decoding operation after the one's complement operation. Adding one to the input of the decoder is equivalent to shifting the higher output of the decoder by one control line.

[0039]

As described above, the barrel shifter control method and integrated circuit of the present invention controls the N-bit barrel shifter 22 to shift the bits of the input word 24 by the shift value 30. The method performs a one's complement operation of an m-bit binary representation of the shift value to generate an input if the shift direction is the first direction, or a shift value of the shift value if the shift direction is the second direction. Passing the binary representation as an input, decoding the input into a 2 ^m control signal, generating a plurality of control signals from the 2 ^m control signal, and controlling the barrel shifter. Selecting one of the plurality of control signal groups. The bits in the binary representation of the shift value are
It passes through a plurality of EOR gates 14 _{0 to} 14 _{m -1} and is provided as an input to the first decoder 16. The first decoder 16 decodes this input into a plurality of bits used as control signals, which are divided into a plurality of groups. Thus, some of the control signals are padded with other control signals so as to pad with zeros. Based on the selection input 50, the multiplexer 20 selects which of a plurality of control signals to pass to control the barrel shifter 22. The second decoder 18 decodes the sign of the shift direction and the shift value, and
Provide a selection input 50 to the. In this way, it is possible to solve the problem of delay caused by the operation of the adder 318 that occurs when creating an N-digit control signal used for controlling the barrel shifter 314, and a barrel shifter that performs high-speed conversion is made possible.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a barrel shifter control circuit of the present invention.

FIG. 2 is a detailed cell diagram of a decoder and an output control selection multiplexer.

FIG. 3 is a schematic diagram showing a prior art circuit for controlling a barrel shifter.

[Explanation of symbols]

 Reference Signs List 10 control circuit 12, 14 EOR gate 16, 18 decoder 20 multiplexer 22 N × N bidirectional barrel shifter 24 input word 26 shift output word 28 sign bit 30 shift value 32 shift direction 34 correction shift direction 36 EOR gate output 38 control signal 40 , 42, 44, 46 control signal 50 selection input 52 control signal 300 EOR gate 302 shift direction 304 sign bit 306 selection input 308 shift value 310, 311 EOR gate 312 EOR gate output 314 N × N bidirectional barrel shifter 316 multiplexer 318 all Adder 320 Output of full adder 324 Decoder 326 Control signal 328 Input word 330 Shift output word

Continuation of the front page (73) Patent holder 596077259 600 Mountain Avenue, Murray Hill, New Jersey 07974-0636 U.S.A. S. A. (72) Inventor Mark Stephen Diamond Stein United States of America, 18104 Pennsylvania, Lehigh County, Alentaun, NJ. Forties Street 1491 (72) Inventor Hosahari Earl. Srinivas United States, 18104 Pennsylvania, Lehigh County, Arrentaun, Benner Road 554, Apartment No. 102 (56) References JP-A-4-245323 (JP, A) (58) Fields studied (Int. Cl. ⁷ , (DB name) G06F 7/00 G11C 19/00

Claims (11)

(57) [Claims] 1. An input word (2) corresponding to a shift value (30).
To shift the bits of 4), the barrel shifter (2
A) performing a one's complement operation of an m-bit binary representation of the shift value to generate an input when the shift direction (32) is the first direction; b) passing the binary representation of the shift value as an input when the shift direction (32) is the second direction; c) decoding the input into a 2 ^m control signal; d) generating a plurality of control signal groups from the ^m control signals; and e) selecting one of the plurality of control signal groups to control the barrel shifter (22). Method. 2. The method of claim 1, further comprising: f) filling at least one of the control signals with another control signal. 3. The method of claim 1, wherein said generating step (d) comprises selecting control signals that are a subset of said 2 ^m control signals. 4. The method of claim 3, further comprising the step of: g) padding one of the control signals with another control signal. 5. a) A number m of exclusive ORs corresponding to a predetermined number of bits in a binary representation of a shift value (30).
Each of the R gates (14 _{0 to} 14 _{m -1} ) and the plurality of EOR gates (14) has a first input for receiving a bit of the shift value (30) in binary representation and a second input for receiving a shift direction (32). An output (36) having two inputs and an output (36), wherein the output (36) of the plurality of exclusive OR gates is a 1's complement of the first input if the shift direction is a first value. Supplying, if the shift direction is a second value, supplying the same output as the first input; b) a first decoder (16) receiving the output from the plurality of EOR gates; To control the barrel shifter
Decoding the outputs from the plurality of EOR gates into 2 ^m control signals; c) receiving the 2 ^m control signals;
A predetermined number 1 of the subset of the 2 ^m control signals
A multiplexer (20) controlled by a selection input (50) for selecting one; d) a first receiving a shift direction (32) and a sign bit (28) of a shift value as first and second inputs. A second decoder (18); and the second decoder (20).
Decoding the first and second inputs to the select input (50) to control the integrated circuit. 6. e) an EO receiving the sign bit of the shift direction and the shift value as first and second inputs.
The EOR gate further has an R gate, and the EOR gate has a modified shift direction.
6. The integrated circuit according to claim 5, wherein the first and second inputs are combined to produce 7. The integrated circuit according to claim 6, further comprising: f) a barrel shifter (22) for receiving said output (52) of said multiplexer 20. 8. The integrated circuit according to claim 7, wherein said barrel shifter is a bidirectional barrel shifter. 9. The first decoder (16) includes a plurality of decoder cells, the multiplexor includes a plurality of multiplexor cells, and each of the decoder cells is manufactured with the multiplexor cells at an on-pitch. The integrated circuit according to claim 5, wherein: 10. The method of claim 1, wherein at least one of the plurality of decoder cells is duplicated, the decoder cells are divided into a first group and a second group, and wherein at least one of the plurality of decoder cells is The at least one of the plurality of decoder cells and the first group of decoder cells located in proximity to the first group are fabricated on-pitch with a corresponding one of the multiplexor cells. An integrated circuit according to claim 9. 11. The method of claim 11, wherein at least one of the plurality of decoder cells is duplicated, the decoder cells are divided into a first group and a second group, and wherein at least one of the plurality of decoder cells is Located in the vicinity of the first group, the at least one of the plurality of decoder cells and the first group of decoder cells are a corresponding one of the multiplexor cells and a corresponding one of the second group of decoder cells. 10. The integrated circuit according to claim 9, wherein one of the integrated circuits is manufactured on-pitch.