JP3307960B2 - Brushless motor drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described in the following order. Industrial application Conventional technology (FIGS. 5 to 7) Problems to be solved by the invention (FIGS. 8 and 9) Means for solving the problems (FIGS. 1 to 3) Action (FIGS. 1 to 4) Example (FIGS. 1 to 4) Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a brushless motor driving circuit, and more particularly to a brushless motor driving circuit which does not use a rotation detecting element such as a Hall element.

[0003]

2. Description of the Related Art Conventionally, in a circuit for driving a three-phase brushless motor, for example, a drive current is applied to the drive coil by using a back electromotive force generated in the drive coil without using a rotation detecting element such as a Hall element. In order to switch between the two, a configuration as shown in FIG. 5 has been proposed (JP-A-2-51389).

That is, reference numeral 1 denotes a brushless motor drive circuit as a whole, which compares a back electromotive voltage VU, VV and VW generated in three-phase drive coils LU, LV and LW provided on the stator side of the brushless motor with a comparison circuit 2, 3 and 4 are input to the non-inverting input terminals, respectively.
By inputting the voltage values VCOM of the other ends of U, LV, and LW to the inverting input terminals of the comparison circuits 2, 3, and 4, respectively, a sinusoidal waveform centering on the voltage value VCOM as shown in FIG. Waveforms of the back electromotive voltages VU, VV and VW of
The waveform of each back electromotive voltage VU, VV and VW is the center voltage VCO
Points (hereinafter referred to as zero-cross points) PU1, PU2, PU3 that cross M (this is the 0 level)
... and PV1, PV2, PV3 ... and PW1, PW
, PW3,..., And detection signals S1, S2, and S3 (FIG. 6 (B),
(C) and (D)) are input to the D input terminals of the following D flip-flop circuits 6, 7 and 8, respectively, and also to the exclusive OR circuit 11.

The exclusive OR circuit 11 comprises two exclusive OR circuits 11A and 11B as shown in FIG.
The detection signals S1 and S2 are converted to a first exclusive OR circuit 11A.
And the output of the first exclusive-OR circuit 11A is input to the first input terminal of the second exclusive-OR circuit 11B, and the second exclusive-OR circuit 11B The detection signal S3 is input to the input terminal of the second exclusive-OR circuit 11B as the output signal S5 of FIG.
Time points t1, t3, t5, t7, t9, t11 at which the detection signals S1, S2 and S3 are inverted as shown in FIG.
(Ie, a signal that is inverted at the zero cross point of the back electromotive voltages VU, VV and VW).

The output signal S5 is sent to the integration circuits 15 and 16 via the subsequent non-inverting circuit 13 and the inverting circuit 14, and is sent to the activation detecting circuit 17.

The integrating circuits 15 and 16 integrate the output signal S5 of the exclusive OR circuit 11 and a signal obtained by inverting the output signal S5, thereby obtaining the output of the integrating circuit as shown in FIGS. 6 (F) and 6 (G). The signals S7 and S8 are obtained, and these are input to the following comparison circuit 21.

Here, the integration circuit output signals S7 and S8 are
Since they are symmetrical about the midpoint of the amplitude, the comparison output signal S11 of the comparison circuit 21 becomes a signal that is inverted at the midpoint of the amplitude of the integration circuit output signals S7 and S8.

The brushless motor driven by the brushless motor drive circuit 1 has a three-phase structure, and the zero cross points of the back electromotive voltages VU, VV, and VW appear as a whole at every 60 ° electrical angle, so that they are mutually exclusive. The output signal S5 of the logical OR circuit 11 is also inverted correspondingly every 60 electrical degrees.

Therefore, the comparison output signal S11 is generated by each counter electromotive voltage V
Time points t2, t4, t6, t delayed from the zero-cross points of U, VV and VW (FIG. 6A) by an electrical angle of 30 °, respectively.
The signals are inverted at 8, t10, t12,....

Thus, by inputting the comparison output signal S11 to the following edge detection circuit 22, each change point t
At time t2, t4, t6, t8, t10, t12,..., The edge detection signal S12 changing in the same direction is obtained.
The signal is input to each clock input terminal CK of the flip-flop circuits 6, 7, and 8.

The D flip-flop circuits 6, 7, and 8 output detection signals S1, S2, and S3 input to the D input terminal from the Q output terminal at the timing of inputting the edge detection signal S12 to the clock input terminal CK, respectively. As a result, the phases of the detection signals S1, S2 and S3 are
It outputs timing signals S15, S16 and S17 delayed by 30 °, and sends them to the first switch circuit 24A, second switch circuit 24B and third switch 24C of the switch circuit unit 24 that follow.

The switch circuits 24A, 24B and 24C are respectively switched to the input terminal A side in the motor driving state, and the timing signals S15, S16 and S17 are provided.
Are respectively output from switch circuit output signals a, b and c (FIG. 6).
(I), (J) and (K)).

The 120 ° logic circuit 29 includes transistors Q 1, Q 2, Q 3, Q
4, a circuit for generating switching signals S31, S32, S33, S34, S35 and S36 based on the timing signals a, b and c for controlling the on / off of Q5 and Q6, and the switching signal S31 is a timing signal b The switching signal S32 is generated by an AND operation of the inverted signal of the timing signal c and the timing signal b.
The switching signal S33 is generated by an AND operation of an inverted signal of the timing signal a and the timing signal c, and the switching signal S34 is generated by an AND operation of the inverted signal of the timing signal c and the timing signal a. S
35 is generated by an AND operation of the inverted signal of the timing signal b and the timing signal c, and further includes a switching signal S.
Reference numeral 36 is generated by an AND operation of the inverted signal of the timing signal a and the timing signal b.

Thus, the switching signals S31, S32 and S
Reference numeral 33 denotes an output whose output is inverted through inverting circuits 31, 32 and 33 each having an open collector configuration, and further comprising a resistor R
1, R2 and R3 are input to the bases of PNP transistors Q1, Q3 and Q5, respectively.

The switching signals S34, S35 and S36
Is a non-inverting circuit 3 whose output is open collector
NPN type transistor Q through 4, 35 and 36
2, input to the bases of Q4 and Q6.

The transistors Q1 and Q2 are push-pull connected, and the first-phase driving coil L formed on the stator of the brushless motor is connected to each collector output terminal.
U is connected. The transistor Q1 has an emitter connected to the power supply VS and a base connected to the power supply VS via the bias resistor R4. Further, the base of the transistor Q2 is connected to the power supply VS via the bias resistor R7. Accordingly, by controlling the transistors Q1 and Q2 to be turned on / off by the switching signals S31 and S36, a drive current can be supplied to the first phase drive coil LU.

Here, as shown in FIG. 6 (L), the switching signal S31 has a zero cross point PU1 (t) of the back electromotive voltage VU waveform.
The timing signal S15 (that is, a) which rises at the time t2 delayed by 30 electrical degrees from 1) and the electrical angle from the zero cross point PV1 (t5) of the back electromotive voltage VV waveform.
It is generated based on the inverted signal of the timing signal S16 (that is, the inverted signal of b) which rises at time t6 delayed by 30 °, and the waveforms of the back electromotive voltages VU and VV have a phase difference of 120 electrical degrees. As a result, in the first drive coil LU, the collector of the transistor Q1 from the collector of the transistor Q1 in the section of 120 ° electrical angle from time t2 to time t6 delayed by 30 ° electrical angle from the zero cross point PU1 (t1) of the back electromotive voltage VU waveform Drive current flows.

As shown in FIG. 6 (M), the switching signal S36 has a zero cross point PU2 (t) of the back electromotive voltage VU waveform.
7), an inverted signal of the timing signal S15 (that is, an inverted signal of “a”) which falls at the time point t8 delayed by 30 electrical degrees from the zero point P of the back electromotive force VV waveform.
It is generated based on the timing signal S16 (that is, b) that rises at time t6 delayed by 30 electrical degrees from V1 (t5), and the waveforms of the back electromotive voltages VU and VV each have a phase difference of 120 electrical degrees. Accordingly, in the first phase drive coil LU, the transistor Q2 is turned on in the section of the electrical angle of 120 ° from the time t8 to the time t12 delayed from the zero cross point PU2 (t7) of the back electromotive voltage VU waveform by the electrical angle of 30 °. Drive current flows to the collector.

Therefore, the magnet rotor of the brushless motor can be efficiently rotated by supplying a drive current to a portion where the back electromotive voltage VU is high (that is, a portion where the magnetic flux is large).

Similarly, the switching signal S3 is also applied to the second-phase driving coil LV and the third-phase driving coil LW.
2, the transistors Q by S35 and S33 and S34
3, Q4 and Q5 and Q6 are turned on and off, respectively, to obtain the waveforms of the back electromotive voltages VV and VW (FIG. 6A).
The drive current is supplied in a section having a width of 120 ° delayed from the zero crossing point by an electrical angle of 30 °.

Here, the switch circuit section 24 is switched to the input terminal B side when the motor is started, and the oscillation circuit (OS
C) Three-phase signal S2 output from three-phase signal generation circuit 27 having a ring counter configuration based on oscillation output S19 at 26
By sending 1, S22 and S23 to the 120 ° logic circuit 29, the brushless motor is started.

When the brushless motor starts, the exclusive OR circuit 1 is activated based on the detection signals S1, S2 and S3.
1 outputs an output signal S5.
7, the switching signal S18 is sent to the switch circuit unit 24, and the switch circuits 24A, 24B and 24C of the switch circuit unit 24 are respectively switched to the input terminals A, and thereafter the back electromotive voltages VU, VV and VW , A drive current is supplied to the drive coils LU, LV and LW based on the detection signals S1, S2 and S3, thereby rotating the brushless motor.

[0024]

However, in this way, the zero-crossing points PU1, PU1 of the back electromotive voltages VU, VV and VW are thus obtained.
PU2, PU3... And PV1, PV2, PV3... And PW1, PW2, PW3.
When a drive current is supplied to U, LV and LW, when a torque is generated in the same direction as the rotation direction as shown in FIG. 8 (that is, when acceleration is performed), the drive current is supplied to drive coils LU, LV and LW. The voltage drop of the drive coils LU, LV and LW due to the energization of the
When torque is generated in the direction opposite to the rotational direction as shown in FIG. 9 (that is, when the motor is decelerated), the drive coils LU, LV and LW are added to the drive coils LU, LV and LW.
Drive coils LU, L caused by applying a drive current to W
The voltage drops of V and LW are the back electromotive voltages VU, VV and VW
From the zero cross points BAD1, BAD2, and BAD at the time when the zero cross points do not originally occur.
3 and BAD4 are generated, and drive coils LU, LV and L
There is a problem that the timing of energizing W cannot be accurately detected.

The present invention has been made in consideration of the above points, and provides a brushless motor drive circuit capable of supplying a drive current to each drive coil at an accurate timing even when torque is generated in a direction opposite to the rotation direction. It is something to propose.

[0026]

According to the present invention, in order to solve the above-mentioned problems, a drive current flowing through a plurality of drive coils LU, LV, LW provided on a stator side is supplied to the drive coils LU, LV, LW. Back electromotive voltages VU and V generated
V, VW zero cross points PU1, PU2, PU3 ...,
PV1, PV2, PV3 ..., PW1, PW2, PW3
In the brushless motor driving circuit 50 that rotates the magnet rotor 61 by switching at predetermined timings based on the driving coils LU and L, respectively.
When the application of the drive current to V and LW ends, respectively, the zero-cross points PU1, PU2, PU3,.
V1, PV2, PV3 ..., PW1, PW2, PW3 ...
, And based on the detection result of the zero cross point of the back electromotive voltage, each of the drive coils LU, LV, L
The periods t51 to t54, t56 to t59,... For prohibiting the detection of the zero crossing point when the drive current is supplied to W are provided, so that the phase coils LU1, LU2, LV1, LV1, LV1, LV2, LW1 and LW
2, the unnecessary zero-cross points BAD1, BAD2, BAD3, BAD3, BAD2, BAD3, Inhibit BAD4 detection.

[0027]

When the energization of the drive current to each of the drive coils LU, LV, and LW ends, the back electromotive voltages VU, VV
And VW zero cross points PU1, PU2, PU3 ... and PV1, PV2, PV3 ... and PW1, PW2, P
W3... Are detected, and zero cross points PU1, PU2, PU3... And PV1, PV2,.
When the drive current is switched by controlling to a state where detection of the zero-cross point is prohibited when PV3... And PW1, PW2, PW3... Are detected or when the drive current is started based on the detected zero-cross point. .. And PV1, PV2, PV3... And PW1, PW2, PW
.. Can be detected, whereby a plurality of zero cross points BAD1, BAD generated during deceleration can be detected.
2, BAD3 and BAD4 may not be detected.
Thus, a drive current can be supplied to each drive coil at an accurate timing.

[0028]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

In FIG. 1 in which the same reference numerals are given to the parts corresponding to FIG. 5, the brushless motor drive circuit 50 detects the detection signals S1, S2 and S3 output from the comparison circuits 2, 3 and 4 by latch circuits. Input to the D input terminals 51, 52 and 53.

The latch circuits 51, 52 and 53 are connected to the gate terminals G when the detection inhibition signals S55, S56 and S57 from the masking circuits 55, 56 and 57 rise to the "H" level. Hold the states of the detection signals S1, S2, and S3 at the D input end, and until the detection prohibition signals S55, S56, and S57 fall to the “L” level, and hold the detection signals S1, S2, and S3. The level is sent from the Q output terminal to the D input terminals of the following D flip-flop circuits 6, 7 and 8 as latch output signals S51, S52 and S53.

The latch circuits 51, 52 and 53 are masking circuits 55, 56 and 5 input to the gate terminal G.
7, when the detection inhibition signals S55, S56 and S57 fall to the "L" level, the detection signals S1, S2 and S3 input to the D input terminal are passed as they are, and the latch output from the Q output terminal. Signals S51, S52 and S
The signal is sent to the D input terminals of the D flip-flop circuits 6, 7, and 8 as 53.

Here, the masking circuit 55 includes switching signals S31 and S36 output from the 120 ° logic circuit 29.
(Ie, a signal for switching the drive current of the drive coil LU) and a latch output signal S51, and a detection inhibition signal S55 is generated based on this.

That is, as shown in FIG. 2, the masking circuit 55 comprises a detection permission judgment circuit 55A and a detection prohibition judgment circuit 55B. The switching signal S31 output from the 120 ° logic circuit 29 is subjected to detection permission judgment. Circuit 55
A is input to the first inverted input terminal of the NAND circuit 55C having the inverted input terminal configuration of A, and is input to the second inverted input terminal of the NAND circuit 55C via the NOT circuit 55D.

As a result, in the NAND circuit 55C, the switching signal S31 (FIG. 3B) and the inverted signal S55D delayed by a predetermined time from the switching signal S31.
Based on (FIG. 3 (C)), the “L” level is maintained from the time point t54 when the switching signal S31 falls (that is, the time point when the energization of the drive coil LU ends) to the time point t55 when the inversion signal S55D rises. Output signal S falling to
55C (FIG. 3D) is obtained and input to the first input terminal of the OR circuit 55G having the inverted input terminal configuration.

The masking circuit 55 inputs the switching signal S36 output from the 120 ° logic circuit 29 to the first inverting input terminal of the NAND circuit 55E having an inverting input terminal of the detection permission judging circuit 55A. The signal is input to the second inverting input terminal of the NAND circuit 55E via the NOT circuit 55F.

As a result, in the NAND circuit 55E, the switching signal S36 (FIG. 3E) and the inverted signal S55F delayed by a predetermined time from the switching signal S36.
Based on (FIG. 3 (F)), the “L” level is maintained from time t59 when the switching signal S36 falls (that is, when power supply to the drive coil LU ends) to time t60 when the inversion signal S55F rises. Output signal S falling to
55E (FIG. 3 (G)) is obtained and input to the second input terminal of the OR circuit 55G having an inverted input terminal configuration.

On the other hand, the detection inhibition determination circuit 55B
A latch output signal S51 output from the latch circuit 51
(Ie, the detection signal S1) (FIG. 3 (H)) is input to the first input terminal of the NAND circuit 55H having an inverted input terminal configuration, and the latch output signal S51 is inverted via the NOT circuit 55I. This is converted to an inverted signal S55I (FIG. 3).
(I)) is input to the second input terminal of the NAND circuit 55H.

As a result, in the NAND circuit 55H, the latch output signal S51 and the latch output signal S5
The time t56 when the latch output signal S51 falls based on the inverted signal S55I delayed by a predetermined time from the time t56.
The output signal S55H that falls to the “L” level for a predetermined time at (ie, the zero cross point PU2 of the back electromotive voltage VU).
(FIG. 3 (K)) is obtained and input to the first input terminal of the OR circuit 55K having the inverted input terminal configuration.

The latch output signal S51 input to the detection inhibition determination circuit 55B is input to the first input terminal of the NAND circuit 55J, and the second output signal S51 of the NAND circuit 55J is input via the inverting circuit 55I. Input to the input terminal.

As a result, in the NAND circuit 55J, the latch output signal S51 and the latch output signal S5
The time t51 at which the latch output signal S51 rises based on the inverted signal S55I delayed by a predetermined time from 1.
The output signal S55J that falls to the “L” level for a predetermined time at (ie, the zero cross point PU1 of the back electromotive voltage VU).
(FIG. 3 (J)) is obtained and input to the second input terminal of the OR circuit 55K having the inverted input terminal configuration.

Here, the OR circuit 55G having the inverting input terminal configuration
Is input to the third input terminal of the OR circuit 55K having an inverted input terminal, and the output signal S55K of the OR circuit 55K is input to the third input terminal of the OR circuit 55G. To be entered at the end,
Thus, the OR flip-flop circuit 55G and 55K constitute an RS flip-flop circuit.

As a result, the output signal S55C or S55E
As the output signal S55H or S55J falls, the detection prohibition signal S55 which rises to the "H" level at the same time as the output signal S55H or S55J falls is obtained.

Thus, by inputting the detection inhibition signal S55 to the gate terminal G of the latch circuit 51, the detection is inhibited when the switching signal S31 or S36 falls (that is, when the energization of the drive coil LU ends). When the signal S55 falls to the "L" level, the detection signal S1 input to the D input terminal of the latch circuit 51 is output as it is from the Q output terminal, and the detection signal S1 is inverted (that is, the back electromotive voltage). Zero cross point PU of VU
1, PU2, PU3,...), The detection inhibition signal S55 rises to the “H” level, and the detection signal S input to the input terminal D of the latch circuit 51 at this time.
The state of 1 is held and output.

Accordingly, the latch circuit 51 holds the detection signal S1 while energizing the drive coil LU so as not to detect the zero cross point of the back electromotive voltage VU. Detection signal S1
Is output as it is, the zero cross point of the back electromotive voltage VU can be detected.

As a result, when a drive current is applied to the drive coil LU, a plurality of zero cross points B as shown in FIG.
Even if AD1, BAD2, BAD3, BAD4... Occur, the zero-cross point PU1,
It is possible to detect only PU2, PU3,..., So that the power supply to the drive coil LU can be accurately performed.

Although the case where the drive coil LU is driven has been described above, also in the case where the drive coils LV and LW are driven, the masking circuits 56 and 57 having the same configuration as the masking circuit 55 have the counter electromotive voltages VV and VW. Necessary zero cross points PV1, PV2, PV3 ... and PW
, PW2, PW3,... Can be detected, whereby the power supply to each of the drive coils LV and LW can be accurately performed.

Here, the brushless motor driving circuit 50
As shown in FIG. 4, a three-phase brushless motor driven by
1 and LU2, the coils LV1 and LV2 forming the second-phase drive coil LV, and the coils LV1 and LW2 forming the third-phase drive coil LW are respectively arranged circumferentially on the stator side (see FIG. )), A disk-shaped magnet rotor 61 (FIG. 4)
(B)) is rotatably supported.

The driving coils LU1, LU2, LV1,
As shown in FIG. 4C, LV2, LW1, and LW2 have drive coils LU1 and LU2, LV1, LV2, LW1, and LW2 connected in series at respective symmetrical positions with respect to the center of the circumferentially arranged array. The output terminals COM are commonly connected to the input terminals U, V, and W.

In the above configuration, when the brushless motor drive circuit 50 generates torque in the direction opposite to the rotation direction of the magnet rotor 61, the back electromotive force generated in each of the drive coils LU, LV and LW as shown in FIG. The voltage levels of the voltages VU, VV and VW decrease when the drive current is applied,
Multiple zero cross points BAD1, BAD2, BAD3, B
AD4... Occur, but zero-cross points PU1, PU2, PU3.
1, PV2, PV3 ... and PW1, PW2, PW3 ...
... at the timing of detecting...
By causing S56 and S57 to fall to the “L” level, the zero-cross point is detected, and while the drive current is applied to the drive coils LU, LV and LW, the detection inhibition signals S55, S56 and S57 are respectively set to “H”. Level, a plurality of unnecessary zero-cross points BAD1 and BAD generated at the time of the energization.
2, BAD3, BAD4... Are not detected.

Thus, the switching signals S31 to S36 for applying the drive current to the drive coils LU, LV and LW are changed to the electrical angles 180 ° of the detected back electromotive voltages VU, VV and VW.
The switching can be accurately performed based on the zero-crossing point for each case, and the power can be correctly supplied at a predetermined timing.

According to the above configuration, the drive coils LU, L
While a drive current is applied to V and LW, a back electromotive voltage VU,
By not detecting the zero-cross points of VV and VW, and detecting only the zero-cross points generated at every 180 ° of the back electromotive voltages VU, VV and VW, the drive can be performed even when the brushless motor is decelerated. A drive current can be supplied to the coils LU, LV, and LW at the correct timing, and a smooth deceleration torque can be obtained.

As a result, the speed controllability of the brushless motor can be further improved, and the time required for stopping the brushless motor can be reduced when the brushless motor is stopped.

In the above embodiment, the detection signal S
The case where the detection prohibition signals S55, S56 and S57 are respectively raised to "H" level based on the inversion of 1, S2 and S3 to control the zero cross points of the back electromotive voltages VU, VV and VW to the detection prohibition state. As described above, the present invention is not limited to this. For example, the rising edges of the switching signals S31 to S36 (that is, the drive coils LU, LV, and LW
(A timing at which a drive current is supplied to the motor) to control the detection to a prohibited state.

In the above-described embodiment, the case of driving a three-phase brushless motor has been described. However, the present invention is not limited to this, and can be widely applied to brushless motor driving circuits for driving various brushless motors. it can.

[0055]

As described above, according to the present invention, when the energization of the drive current to each drive coil is completed, the state is controlled so that the zero cross point of the back electromotive voltage is detected, and the zero cross point of the back electromotive voltage is detected. By controlling to a state where detection of the zero-cross point is prohibited when it is performed or at the start of energization of the drive current based on the detected zero-cross point,
It is possible to detect only the zero-cross point required when switching the drive current, and thereby to apply the drive current to each drive coil at an accurate timing.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing one embodiment of a brushless motor drive circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a masking circuit according to the present invention.

FIG. 3 is a signal waveform diagram for explaining a generation of a detection inhibition signal according to the present invention;

FIG. 4 is a schematic diagram showing a configuration of a stator coil and a magnet rotor of the brushless motor according to the present invention.

FIG. 5 is a connection diagram showing a conventional brushless motor drive circuit.

FIG. 6 is a signal waveform diagram for describing a driving state of the brushless motor.

FIG. 7 is a block diagram showing a configuration of an exclusive OR circuit of the brushless motor drive circuit.

FIG. 8 is a characteristic curve diagram showing a back electromotive force waveform during acceleration.

FIG. 9 is a characteristic curve diagram showing a back electromotive voltage waveform during deceleration.

[Explanation of symbols]

1, 50... Brushless motor drive circuit, 2, 3, 4,.
... Comparator circuit, 6, 7, 8 ... D flip-flop circuit
11: exclusive OR circuit, 29: 120 ° logic circuit,
51, 52, 53 ... Latch circuit, 55, 56, 57 ...
... Masking circuit, LU, LV, LW ... Driving coil,
VU, VV, VW ... Back electromotive voltage, S55, S56, S5
7 ... Detection inhibit signal.

Claims (1)

(57) [Claims] 1. A plurality of drive coils provided on a stator side
Back electromotive force that generates a drive current that flows through the drive coil
Predetermined timing based on pressure zero-cross point
Rotate the magnet rotor by switching with
In the brushless motor drive circuit, the energization of the drive current to each of the drive coils is completed.
When the zero cross point of the back electromotive voltage is detected
Based on the detection result of the zero cross point of the back electromotive force
hand, When the drive current is applied to each of the drive coils.Above zero
Prohibit cross point detectionBy setting a period, Prohibition of detection provided for each phase coil of each drive coil
Each of the above phases is controlled by each detection inhibit signal sent from the means.
Prohibit detection of unnecessary zero-cross points in coils This
And a brushless motor drive circuit.