JP3306851B2 - Power supply method for recording medium cassette and recording / reproducing apparatus for the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for supplying power to a recording medium cassette containing a memory used in a video tape recorder (hereinafter, referred to as a VTR).

[0002]

2. Description of the Related Art Conventionally, recording medium cassettes having a built-in memory are well known. In this memory, information such as the length of the magnetic tape wound on the cassette, the remaining time of the tape, whether or not the recording has been completed, and whether or not it is a rental video (hereinafter referred to as recording information) Is used to eliminate dubbing times and to prevent unauthorized use.

In order to read or write the recorded information, first, the contact of the terminal of the recording medium cassette is brought into contact with a connection terminal provided in the recording / reproducing apparatus, and data communication is performed while maintaining the connected state. Was. The number of the contacts and terminals includes, for example, a power supply terminal, a clock terminal, a data terminal, a GND terminal, a select terminal for selecting a cassette, and the like.

[0004]

However, in today's cassettes and VTR bodies, while miniaturizing them with high performance, the positions of the contact points of the cassettes and the positions of the terminals provided on the VTR body have been limited. Further, in the related art, there has been a problem that a connection area required for maintaining a state in which the contact point of the recording medium cassette and the terminal of the VTR main body are well connected cannot be secured.

Therefore, even if the cassette and the VTR main body are miniaturized, there is a problem to be solved that the connection state between the contact of the cassette and the terminal of the VTR main body can be reliably maintained.

[0006]

In order to solve the above-mentioned problems, a method for supplying power to a recording medium cassette according to the present invention comprises a plurality of connections for connecting external devices to an outer surface of a cassette case containing a recording medium. Providing a terminal, connecting an IC provided in the cassette case to the connection terminal, and supplying power to the IC, wherein one of the plurality of connection terminals is selected by the chip select of the IC. A common terminal connected to a terminal and a power supply terminal is allocated, and power is supplied to the common terminal only when it is selected to drive the IC.

In the recording / reproducing apparatus of the present invention, a plurality of connection terminals for connection to external equipment are provided on an outer surface of a cassette case accommodating a recording medium, and an IC provided in the cassette case is connected to the connection terminal. In a recording / reproducing apparatus using a recording medium cassette connected to terminals, one of the plurality of connection terminals is assigned to a common terminal connected to a chip select terminal and a power supply terminal of the IC, and the IC is driven. Power is supplied to the common terminal only when the selected mode is selected; the common terminal is connected to a selection control terminal of a mode controller that controls an operation mode of the recording / reproducing apparatus; The connection terminal
A common terminal, a GND terminal, a clock terminal, and a data terminal connected to a chip select terminal and a power supply terminal of the IC.

[0008]

According to the present invention, one of a plurality of connection terminals for connecting to an IC mounted on a recording medium cassette is assigned to a common terminal connected to a chip select terminal and a power supply terminal of the IC so that the IC is driven. By supplying power to the common terminal only when selected, it is possible to reduce the number of terminals equivalent to the power supply terminal, and it is possible to use more compact cassette contacts and VTR body terminals In addition, by turning on a predetermined signal, power can be supplied to the memory only when required.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a power supply method for a recording medium cassette and a recording / reproducing apparatus according to the present invention will be described with reference to the drawings.

[0010] A digital VTR according to an embodiment of the present invention comprises:
As shown in FIG. 1, a recording medium cassette 1 and a digital VT
The recording medium cassette 1 is provided with a memory and a controller for controlling the memory.

The digital VTR main body 2 has a box shape provided with an insertion slot 3 into which the recording medium cassette 1 is inserted. Although not shown, a mechanism for loading a magnetic tape from the recording medium cassette 1 is provided therein. A reading mechanism and the like are provided, and a recording medium cassette 1 described later is provided with a power supply and a recording information section for transmitting and receiving recording data.

The connection between the recording information section of the digital VTR main body 2 and the recording medium cassette 1 is made as shown in FIG.
The contacts are made from four contacts 4, 5, 6, 7. That is, when the recording medium cassette 1 is inserted into the digital VTR main body 2 from the insertion slot 3, as shown in FIG.
Are connected to the connector 8 connected to the recording information section of the digital VTR main body 2 so that writing to or reading from the memory of the recording medium cassette 1 can be performed. It is.

The recording medium cassette 1 and a digital VTR
When communication is performed with the main unit 2 connected, FIG.
As shown in the figure, the recording information section 9 on the recording medium cassette 1 side.
And the control unit 10 of the digital VTR main body 2 are connected.

The recording information section 9 of the recording medium cassette 1 has I
It comprises a RAM 11 as a C memory and a RAM controller 12 for writing to and reading from the RAM 11.

The RAM controller 12 has V
Chip select signal CE from control unit 10 of TR main unit 2
3 is directly supplied to the power supply terminal 13 to supply power to the RAM controller 12 and the RAM 11. Since the recording information section 9 of the recording medium cassette 1 is driven by directly using the potential of the chip select signal CE3, it is not necessary to provide a separate power supply terminal.

The RAM controller 12 has a controller 1
The GND terminal 14 connected to the GND of 0, the clock terminal 15 connected to the clock, the data terminal 16 connected to the data, the connection to the chip select signal CE3 and the connection to the power supply terminal 13 described above are shared. A select terminal 17 is provided.

When the recording information section 9 having such a configuration is connected to the control section 10 described later, first, if the chip select signal CE3 supplied to the select terminal 17 is in a so-called high level state, the RAM controller When the power is supplied to the RAM 12 and the RAM 11 at the same time, and the GND signal is supplied from the GND terminal 14, the operation becomes possible.

In this state, a clock signal is obtained from the control unit 10 via the clock terminal 15 and data is obtained via the data terminal 16 so that the RAM 11
, And conversely, data read from the RAM 11 can be transmitted via the data terminal 16 based on the clock signal from the clock terminal 15. The control of reading and writing is distinguished by a control code included in a data signal from the control unit 10.

The control unit 10 includes a mode controller 18
, A mechanical controller 19, and a timer / tuner controller (hereinafter, referred to as a T / T controller).
The power supply Vcc and GND are supplied to each of them.

The mode controller 18 controls, for example, reading and writing of information recorded on the recording medium cassette 1. And this mode controller 1
8, a clock signal terminal 21 for transmitting a clock having a predetermined cycle, a data input / output terminal 22 for transmitting and receiving data, and a chip for controlling operations of the mechanical controller 19, the T / T controller 20, and the recording information unit 9. It has a structure including chip select terminals 23, 24 and 25 for transmitting select signals CE1, CE2 and CE3. A driver 32 is provided between the chip select terminal 25 and the recording information section 9.

The mechanical controller 19 is mounted on the digital VTR main body 2 and performs mechanical control for driving a magnetic tape, for example. Then, a clock signal terminal 26 for receiving a clock signal from the mode controller 18, a data input / output terminal 27 for transmitting / receiving data to / from the mode controller 18 or the recording information unit 9, and a chip select for receiving the chip select signal CE1 of the mode controller 18 And a terminal 28.

The T / T controller 20 is a controller for controlling a timer and a tuner, and includes a clock signal terminal 29 for receiving a clock signal from the mode controller 18 and a data for receiving data from the mode controller 18 or the recording information section 9. I / O terminal 3
0 and a chip select terminal 31 for receiving a chip select signal CE2 from the mode controller 18.

As shown in FIG. 5, the operation of the control section 10 having such a configuration is performed by the clock signals 15a,
Data 16a, 16b, 16c... Are input and output by rectangular waves of chip select signals CE1, CE2, CE3 synchronized with 5b, 15c, 15d, 15e, 15f.

For example, in the case of the clock signal 15a, the chip select signal CE1 becomes a high-level rectangular wave, and the data 16a based on the chip select signal CE1 is transmitted to the mode controller 18 and the mechanical controller 1
9, when the clock signal 15c, the chip select signal CE2 becomes a high level rectangular wave, and the data 16b based on the chip select signal CE2 is input / output to the mode controller 18 and the T / T controller 20, and When the signal is 15e, the chip select signal C
E3 becomes a high-level rectangular wave, and the signal of the chip select signal CE3 is input to the power supply terminal 13 (see FIG. 4) of the recording information section 9 via the driver 32, and the recording information section 9 is activated. The transmission and reception of the data 16c can be performed with the mode controller 18.

Next, as described above, the mode controller 18 controls the chip select signals CE1, CE2, CE3.
Are successively generated in synchronization with the clock signal. Data transmission / reception with the recording information unit 9 at the timing of the chip select signal CE3, that is, the case where data is read from the RAM 11 of the recording information unit 9 and the case where data is written This will be described below. The description will be made with reference to FIG.

(1) When the mode controller 18 reads data from the RAM 11 of the recording information section 9. When the mode controller 18 reads data from the RAM 11 of the recording information section 9, as shown in FIG. 6, the chip select signals CE1 and CE synchronized with the clock signal are output.
2, the data is transmitted and received at the timing of the chip select signal CE3.

That is, when the chip select signal CE3 from the mode controller 18 goes high, power is supplied to the RAM 11 and the RAM controller 12 of the recording information section 9 via the driver 32, and the RAM 11 and the RA
When the function of the M controller 12 can be sufficiently operated, a receivable signal 33 is sent to the mode controller 18 via the data terminal 16 of the RAM controller 12. That is, the control unit 10 can receive the receivable signal 33 after a predetermined time (A) has elapsed since the rise of the chip select signal CE3.

When the control section 10 receives the receivable signal 33, the mode controller 18 sends a data group 34 composed of a header 35, an address 36 and a parity 37 to the recording information section 9.

The header 35 is added for identifying or synchronizing a data group in the recording information section 9, and the address 36 is a read command code (CMD) that can be decoded by the RAM controller 12 of the recording information section 9.
36a, a start address (SA) 36b of the RAM 11 of the recording information section 9, and an end address (EA) 36
c, and the parity 37 is an address 36
Is a data configuration obtained by a predetermined algorithm from the bit configuration of FIG.

The data group 34 constructed as described above
Is sent to the RAM controller 12 of the recording information section 9 via the data terminal 16 of the recording information section 9. The RAM controller 12 synchronizes with the header 35 of the data group 34,
Data from the start address (SA) 36b to the end address (EA) 36c is read from the RAM 11,
The read data group 39 is transmitted to the mode controller 18 via the data terminal 16. The data group 39 includes a header 35, read data 38, and parity 37.

The data group 39 is stored in the mode controller 1
8 receives the read data 38 in synchronism with the header 35, receives the read data 38 after performing a parity check on the bit configuration of the parity 37 and the received read data 38. In this manner, starting from the receivable signal 33 from the recording information section 9, the chip select signal CE3 goes low after a series of data transmission / reception (data groups 34, 39) is completed, and the recording information section 9 The reading of a series of data is ended.

(2) When writing data from the mode controller 18 to the RAM 11 of the recording information section 9 From the mode controller 18 to the RAM 11 of the recording information section 9
7, the chip select signal CE3 rises as shown in FIG.
After the power is supplied to the RAM 11 and the RAM controller 12 of the recording information unit 9 via the control terminal 17, the receivable signal 33 is transmitted from the select terminal 17 to the mechanical controller 19 via the data terminal 16 of the recording information unit 9. This is the same as the case of the above (1) reading.

After receiving the receivable signal 33, the mode controller 18 sends the write data group 40 to the recording information section 9 with the header 35 and the parity 37 added thereto.

The write data group 40 includes a header 35,
A write command (CMD) 40a, a write start address (SA) 40b, a write end address (EA) 40c, write data 40d,
This is a group of data including the parity 37.

The write command (CMD) 40a is
This is a command for instructing the RAM controller 12 of the recording information section 9 to write the data into the RAM 11 when it is decoded.

Write start address (SA) 40
b is a start address for writing to the RAM 11 of the recording information section 9, and is a write end address (E ·
A) 40c is an end address for writing.

The write data 40d is stored in the recording information section 9
Start address (SA) 4 in RAM 11
0b and data to be written in the range specified by the write end address (EA) 40c.

The write data group 40 constructed as described above
Is sent to the RAM controller 12 of the recording information section 9, the RAM controller 12 first decodes the write command (CMD) 40a, and writes the write start address (SA) 40b and the write end address (E) to the RAM 11. A) Write the write data 40d into the range specified by 40c.

When the writing is completed, an acknowledgment signal 41 indicating that the writing has been performed on the RAM 11 is sent to the mode controller 18. When the writing to the RAM 11 fails, the acknowledge signal 41 is not sent, but a different signal (not shown) is sent, for example, and the mode controller 18 requests the writing data again.

Upon receiving the acknowledge signal 41, the mode controller 18 changes the chip select signal CE3 from the high level to the low level, and transmits and receives a series of write data (reception enable signal 33, write data 40,
The acknowledgment signal 41) ends.

As described above, the transmission and reception of the recording information section 9 to and from the RAM 11 always perform the data communication by using the receivable signal 33 generated after the lapse of a predetermined time (A) after the power is supplied. Therefore, if an error occurs in the data communication between the control unit 10 and the recording information unit 9 or a parity error occurs in the data, the power is supplied by turning on / off the chip select signal CE3. By turning it on / off, it can be re-transmitted in a so-called reset state.

Also, the timing of power supply to the recording information section 9 can be easily changed by freely changing the ON / OFF timing of the chip select signal CE3.

[0043]

As described above, in the recording medium cassette and the recording / reproducing apparatus for the same according to the present invention, one of a plurality of signal connection terminals is used in common with a power supply terminal, thereby enabling recording. Since the number of terminals for communication connection between the medium cassette and the recording / reproducing device can be reduced,
Since the area of each contact required for connection can be sufficiently ensured even in a limited space, there is an excellent effect that a reliable connection state can be obtained.

In the data communication between the recording medium cassette and the recording / reproducing device, data is transmitted / received in response to each other's response. Therefore, even if an abnormality occurs during the data communication, retransmission is easy. Therefore, an excellent effect that data can be reliably transmitted and received is also provided.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view showing a recording medium cassette and a recording / reproducing apparatus according to the present invention.

FIG. 2 is a schematic perspective view of the recording medium cassette.

FIG. 3 is a schematic cross-sectional view showing an enlarged main part in a state where a terminal of the recording / reproducing apparatus is connected to a contact point of the recording medium cassette.

FIG. 4 is a block diagram showing a structure of the recording medium cassette and a structure of a recording / reproducing apparatus.

FIG. 5 is a timing chart of the recording / reproducing apparatus.

FIG. 6 is a timing chart for reading data from a memory of the recording medium cassette.

FIG. 7 is a timing chart for writing data to a memory of the recording medium cassette.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 recording medium cassette 2 digital VTR main body 3 insertion slot 4, 5, 6, 7 contact 8 connector 9 recording information section 10 control section 11 RAM 12 RAM controller 13 power supply terminal 14 GND terminal 15 clock terminal 16 data terminal 17 select terminal 18 mode Controller 19 Mechanical controller 20 T / T controller 21 Clock signal terminal 22 Data input / output terminal 23, 24, 25, 28, 31 Chip select terminal 26 Clock signal terminal 27 Data input / output terminal 29 Clock signal terminal 30 Data input / output terminal 32 OR gate 33 Reception enable signal 34 Data group 35 Header 36 Address 36a Read command 36b Start address 36c End address 37 Parity 38 Read data 39 Data group 40 Write See data group 40a write command 40b write start address 40c write end address 40d write data 41 Akunourijji signals CE1, CE2, CE3 chip select signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11B 23/30 G11B 15/00 G11B 33/12 305

Claims (4)

(57) [Claims] 1. An outer surface of a cassette case accommodating a recording medium.
A plurality of connection terminals for connecting to external devices are provided on the
The IC provided in the cassette case and the connection terminal
Power supply method to connect and supply power to the IC
And connecting one of the plurality of connection terminals to the chip set of the IC.
Assigned to the common terminal connected to the rect terminal and the power terminal,
The shared end only when selected to drive the IC
Recording medium characterized by supplying power to the
How to supply power to the body cassette. 2. An outer surface of a cassette case containing a recording medium.
A plurality of connection terminals for connecting to external devices are provided on the
The IC provided in the cassette case and the connection terminal
Recording / reproducing devices that use a connected recording medium cassette
And one of the plurality of connection terminals is connected to the chipset of the IC.
Assigned to the common terminal connected to the
The shared end only when selected to drive the IC
Recording power, wherein power is supplied to the
Raw equipment. 3. The operation of the recording / reproducing apparatus, wherein the common terminal operates.
Select the control terminal of the mode controller that controls the mode.
3. The recording of claim 2, wherein the recording is connected.
Playback device. 4. The IC chip according to claim 1, wherein the plurality of connection terminals are connected to a chip of the IC.
Common terminal connected to select terminal and power supply terminal, GND
Terminal, clock terminal, and data terminal.
The recording / reproducing apparatus according to claim 2.