JP3301426B2 - Receiving synchronization method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reception synchronization method and apparatus, and more particularly, to a reception synchronization method capable of accurately performing timing estimation and frequency estimation for synchronization and performing reception synchronization when line conditions are poor. Method and apparatus.

[0002]

2. Description of the Related Art In a mobile radio communication system or a satellite radio communication system of a mobile radio communication system using a TDMA communication system, in order for the reception side to successfully receive the transmission information transmitted from the transmission side, the reception of the reception apparatus is required. Synchronize timing and frequency with reception timing and frequency of received signal
There is a need. Therefore, in the related art, a synchronization signal is multiplexed and transmitted in a radio control channel of transmission / reception control information from the transmission side to the reception side for reception synchronization in the reception apparatus. In the control channel, a CCS (Common Channel Signaling) signal including a synchronization word composed of several tens of symbols is inserted into a certain slot of each frame for each frame composed of a plurality of slots (also referred to as a burst). A signal in which a frequency estimation signal is inserted in a slot (a slot other than the slot in which the CCS signal is inserted) is transmitted from the transmitting side to the receiving side. Control data is inserted in portions other than the synchronization word in the CCS signal.

For each frame received on the receiving side via the control channel, coarse timing estimation is performed when the peak value of the signal obtained by moving average of the received signal is the highest peak value. It is assumed that the obtained, that is, the reception signal (frequency estimation signal) can be detected. A frequency estimation signal is obtained by the detection of the received signal, and it can be said that the frequency estimation signal transmits the frequency of the control signal affected by the line condition of the radio line. Therefore, the detected frequency estimation signal is subjected to a fast Fourier transform (hereinafter, FF).
T (referred to as Fast Fourier Transform), the frequency error is estimated by estimating the frequency (the difference between the frequency set for the control channel on the receiving side for the control channel, and the frequency of the received signal). The frequency of the synchronization word in the CCS signal included in a certain slot in the frame is corrected. Then, the frequency-corrected synchronization word and the synchronization word set for the control channel on the reception side (a synchronization word known on the reception side) are correlated over a predetermined signal range, and the correlation value is determined in advance. By seeing whether or not the threshold value is exceeded, the coarse timing estimation is viewed in more detail. When the threshold value is exceeded, synchronization is established, that is, the time (timing) of the peak correlation value is determined by the transmitting side. And the timing is taken. This timing is used for signal demodulation on the receiving side.

[0004] The conventional reception synchronization method using one frame for synchronization can achieve its intended purpose when the line condition of the radio line is relatively good. However, if the line condition of the wireless line becomes worse than expected by the reception synchronization method, errors in the detection of received signals, frequency estimation and correlation processing increase, and synchronization accuracy decreases. As a result, the desired reception synchronization cannot be achieved.

[0005] Such inconvenience one receive synchronization method capable of solving the European Application published Laid (E P08093
77A2). Referring to FIG.
The reception synchronization method described in the publication will be described. Also in the reception synchronization method described in this EP publication, a synchronization signal is multiplexed between a transmission side and a reception side on a radio control channel of transmission / reception information. The control channel includes a C word including a synchronization word composed of several tens of symbols in a certain slot of each frame for each frame composed of a plurality of slots (also referred to as a burst).
A CS (Common Channel Signaling) signal is inserted, and a signal in which a frequency estimation signal is inserted into a certain slot of each frame is transmitted from the transmission side to the reception side. For each frame received on the receiving side via the control channel, the peak value of the signal obtained by moving average of the received signal received is estimated at the time of the highest peak value, coarse timing is estimated, The reception signal (frequency estimation signal) is detected at the coarse timing. The coarse timing estimation is performed as follows in the reception synchronization method described in the above-mentioned EP publication.

A peak value of a signal obtained by moving-averaging a received signal is measured for two frames (step SD1 in FIG. 12), and a plurality of corresponding peak values are selected for each frame. When the time interval between the respective peak values is an appropriate value, it is estimated that the timing has been obtained at a coarse timing. At this coarse timing, a received signal is detected in the same manner as in the conventional method (step SD).
2). Here, the rough timing cannot be estimated,
If the received signal cannot be detected (not detected in step SD2 in FIG. 12), the same process is performed on the next control channel assigned as the control channel in the same manner as the conventional method (step SD3). .

The coarse timing is estimated, the received signal is detected (detection of step SD2 in FIG. 12), and the frequency estimation signal obtained is subjected to FFT transform to estimate the frequency. The frequency is estimated as follows in the reception synchronization method described in the above-mentioned EP publication. The frequency estimation in the reception synchronization method described in the EP publication is performed for two frames according to a carrier / noise ratio (C / N ratio).
When the frequency is estimated twice, the average is taken and the frequency is estimated (step SD4).

The frequency error of the synchronization word in the CCS signal included in the next slot is corrected based on the estimated frequency error at the time of reception. Then, the frequency-corrected synchronization word and the synchronization word set for the control channel on the reception side (a synchronization word known on the reception side) are correlated over a predetermined signal range (step SD5).

By checking whether or not the peak correlation value exceeds a predetermined threshold value, the coarse timing estimation is further refined, and when the peak correlation value exceeds the threshold value (step (The correlation value of SD6 is large), the transmission side and the reception side are synchronized, that is, the time point (timing) of the peak correlation value is defined as the timing at which the transmission side is synchronized (step SD7). If the peak correlation value does not exceed the predetermined threshold value (small correlation value in step SD6), similar processing to the next control channel assigned as the control channel is started as in step SD3. (Step SD8).

[0010]

However, the above E
In the reception synchronization method described in the P publication, coarse timing estimation is performed by judging the validity of the time interval of the corresponding peak value in two frames, and when valid, the point of time of the peak value is regarded as the timing estimation value. ing. In this timing estimation, when a part of the signal is greatly attenuated due to fading or the like, the timing cannot be estimated, and there is a high possibility that the received signal (frequency estimation signal) will not be detected. Become. For example, in the first frame of the two frames, an appropriate peak value could not be detected, but in the second frame, a peak value could be detected at a timing where the peak value could not be detected in the first frame. Is the case.

In the reception synchronization method described in the above-mentioned EP publication, the frequency is estimated by averaging the frequencies obtained in two frames. When the frequency is estimated by taking the average of the frequencies, each of the frequencies obtained on the time series in the first frame and each of the frequencies obtained on the time series in the second frame differ depending on the deterioration of the line condition. In the case of a frequency distribution of values, the probability of erroneously estimating the frequency increases. For example,
When there is no noise, the frequency data is {0, 0, 0, 3,
0, 0, 0, 0}, and the frequency data when noise is added is {1, 1, 2, 4, 4} in the first frame.
2, 1, 1, 1} and {1, 1, 2, 3, 1, 1, 2, 4} in the second frame. Here, when the estimated value of the frequency is assumed to be estimated as 0, 1, 2, 3, 4, 5, 6, 7 from the beginning of the time-series frequency data, it should be estimated as 3 originally. However, when taking the average of the frequency,
This is because it is estimated as 7. As described above, the reception synchronization method described in the EP publication has a disadvantage that the reception signal (frequency estimation signal) is likely to be undetected, and the probability of erroneous frequency estimation is high. There is an inconvenience that reception synchronization cannot be successfully achieved in the case of deterioration.

[0012] The present invention has been made in view of the circumstances as described above, improve the accuracy of detection and the frequency estimate of the received signal, provides received synchronization method and equipment can improve the reliability of the received synchronization It is intended to be.

[0013]

In order to solve this problem, the present invention is directed to a moving average of a sequence of a control signal including a frequency estimation signal and a synchronization word transmitted from a transmitting side to a receiving side. Reception synchronization for selecting the frequency estimation signal from a predetermined number of peak values detected for each frame, and establishing synchronization on the reception side based on the selected frequency estimation signal and a subsequently detected synchronization word. Regarding the method, the first frame
Predetermined number of values from the top of the peak value in
It synthesizes the corresponding peak value of the timing in arm,
The frequency estimation signal is selected based on the largest combined peak value among the combined peak values.

According to a second aspect of the present invention, there is provided the reception synchronization method according to the first aspect, wherein a frequency estimation signal type is determined based on a maximum combined peak value obtained for the two frames .
Select a candidate for the timing, and determine the timing of the frequency estimation signal .
And selecting the frequency estimation signal corresponding to the timing estimation candidate of the frequency estimation signal in the third frame following the two frames based on the candidate for the frame.

According to a third aspect of the present invention, there is provided the reception synchronization method according to the second aspect, wherein the timing of the frequency estimation signal in the third frame following the two frames is the first.
The frame corresponding to the maximum composite peak value in the frame
For frequency estimation in the second frame of the frame timing
Frequency corrected by the received frequency error estimated by the signal
When the correlation between the synchronization word of the obtained second frame and the synchronization word known as the transmitted synchronization word is larger than a threshold value, in the third frame following the two frames, the correlation degree Fine adjustment is made in consideration of the amount of timing deviation obtained in the calculation, and when the degree of correlation is smaller than the threshold value, the amount of timing deviation is not taken into account in the third frame following the two frames. To
It is characterized by fine adjustment .

According to a fourth aspect of the present invention, a predetermined number of peaks detected for each frame of a moving average of a sequence of a control signal including a frequency estimation signal and a synchronization word transmitted from a transmitting side to a receiving side. select the frequency estimation signal from the value, select
The present invention relates to a reception synchronization method for establishing synchronization on the reception side based on a selected frequency estimation signal and a synchronization word detected subsequently, and a predetermined number of highest-order peak values in a first frame.
Value and detects a maximum of the composite peak value and next highest synthesis peak outermost sized synthetic peak value of the synthetic peak value obtained by synthesizing the peak value timing corresponding to the second frame, the detected above Selecting the frequency estimation signal for each combined peak value based on the largest combined peak value and the next largest combined peak value after the largest combined peak value,
The synchronization of the receiving side is established based on the frequency estimation signal in the selected two frame timing candidates and the synchronization word detected subsequently to the two frequency estimation signals. .

According to a fifth aspect of the present invention, there is provided the reception synchronization method according to the fourth aspect, wherein the maximum combined peak value in the third frame following the two frames and the maximum combined peak value are set next to the maximum combined peak value. Frames corresponding to large composite peak values
The frequency estimation signal is selected in the third frame following the two frames based on the timing , and the frequency estimation signal and the third signal in each selected frame timing candidate are selected. The synchronization on the receiving side is established based on the synchronization word detected following the selection of the frequency estimation signal in the frame of (1).

According to a sixth aspect of the present invention, there is provided the reception synchronization method according to any one of the first to fifth aspects, wherein the peak value is smaller than the maximum peak value in the frame and the maximum peak value, and It is characterized in that a predetermined number of peak values are counted from the maximum peak value.

According to a seventh aspect of the present invention, a predetermined number of peak values detected for each frame of a moving average of a sequence of control signals including a frequency estimation signal and a synchronizing word transmitted from a transmitting side to a receiving side are obtained. A first aspect of the present invention relates to a receiving synchronizer that selects the frequency estimation signal and establishes synchronization on a receiving side based on the selected frequency estimation signal and a synchronization word detected subsequently .
A predetermined number of values from the top of the peak value in the frame and the
Said frequency based on the maximum of the composite peak value of the synthesizing means for synthesizing the corresponding peak value of the timing in the two frames, the synthetic peak values synthesized by said synthesizing means
Detecting means for selecting an estimation signal.

[0020] The invention according to claim 8 relates to the reception synchronizer according to claim 7, wherein a first candidate for a frequency estimation signal is selected based on the maximum combined peak value obtained for the two frames. Detecting means, and a candidate for the timing of the frequency estimation signal selected by the first detecting means.
And a second detecting means for selecting the frequency estimation signal corresponding to a candidate for the timing of the frequency estimation signal in a third frame following the two frames based on the selection. I have.

According to a ninth aspect of the present invention, there is provided the reception synchronizer according to the eighth aspect, wherein the first detecting means detects a reception frequency error based on the maximum combined peak value detected in the two frames. And a frequency estimation signal in a third frame following the above two frames
Is the maximum combination in the first frame.
Second frame at frame timing corresponding to peak value
Received frequency estimated by frequency estimation signal at
When the degree of correlation between the synchronization word of the second frame frequency-corrected by the error and the synchronization word known as the transmitted synchronization word is greater than a threshold value, the third frame following the two frames In the third frame, fine adjustment is made in consideration of the amount of timing deviation obtained in the calculation of the degree of correlation, and when the degree of correlation is smaller than the threshold, the third frame following the two frames Timing estimation means for fine-tuning without taking into account the amount of timing deviation
It is characterized by being configured in.

According to a tenth aspect of the present invention, there is provided the reception synchronizer according to the seventh, eighth or ninth aspect, wherein the synthesizing means includes a first synchronizing means.
Within a frame, in chronological order, at certain symbol intervals
When detecting peak power, the peak value of power
Values and their timing from a higher to a predetermined number number
A memory for storing the peak value and the corresponding frame timing in the next frame.
It is characterized by combining with the power of the power .

[0023] According to the eleventh aspect of the present invention, a predetermined number of peaks detected for each frame of a moving average of a sequence of a control signal including a frequency estimation signal and a synchronization word transmitted from a transmitting side to a receiving side. Select the frequency estimation signal from the values,
The present invention relates to a receiving synchronizer that establishes synchronization on a receiving side based on a detected frequency estimation signal and a subsequently detected synchronization word, and includes a predetermined number of received signals from the highest peak value in a first frame.
Value and the first detection means for detecting a maximum synthesis peak value and next highest synthesis peak outermost sized synthetic peak value of the synthetic peak value obtained by synthesizing the peak value timing corresponding to the second frame And selecting the frequency estimation signal for each of the combined peak values based on the largest combined peak value detected by the first detection means and the next largest combined peak value after the largest combined peak value. And two frame ties selected by the second detecting means.
Synchronization means for establishing synchronization on the receiving side based on the frequency estimation signal in the candidate for the mining and the synchronization word detected subsequently to the two frequency estimation signals is provided.

The invention according to claim 12 relates to the reception synchronization apparatus of claim 1 1, wherein, the third following the above two frames
Th next frame corresponding to a larger synthesis peak value of the largest synthesized peak value and synthetic peak outermost size in the frame
The said frequency estimation signal based on the beam timing 2
A third detecting means for selecting in One of the third frame following the frame, each frame selected by said third detecting means
Of each frequency estimation signal in the frame timing candidate and the frequency estimation signal in the third frame.
Synchronization means for establishing synchronization on the receiving side based on a synchronization word detected after selection is provided.

A thirteenth aspect of the present invention relates to the reception synchronizer according to the eleventh or twelfth aspect, wherein the first detecting means comprises:
Within the first frame, a certain symbol interval in time series
When detecting peak power every time,
Values and their Thailand from the top of the click value to a predetermined number number
A memory for storing timing , and a peak value stored in the memory and a corresponding frame timing in the next frame.
And synthesizing means for synthesizing the power of the power .

[0026]

Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. FIG. 1 is a diagram showing an electrical configuration of a reception synchronizer according to a first embodiment of the present invention, and FIG. 2 is a configuration of a frame received from a transmission device via a control channel in the reception synchronizer. FIG. 3 is a schematic flowchart for executing a reception synchronization procedure of the reception synchronization apparatus. FIG. 4 is a first flowchart obtained by dividing a detailed flowchart for executing the reception synchronization procedure of the reception synchronization apparatus into three parts. FIG. 5 is a diagram illustrating a second flowchart portion obtained by dividing a detailed flowchart for executing a reception synchronization procedure of the reception synchronization device into three, and FIG. 6 is a reception synchronization diagram of the reception synchronization device. FIG. 7 is a diagram showing a third flowchart portion obtained by dividing a detailed flowchart for executing the procedure into three, FIG. 7 is a timing chart of reception synchronization of the reception synchronization device, and FIG. FIG. 6 is a diagram for explaining a correlation determination of a synchronization word in the device.

The reception synchronization equipment of this embodiment enhances the precision of the estimation of detection and the frequency of the received signal relates to ensure synchronization device, as shown in FIG. 1, the antenna and RF circuit 11
, A frequency synthesizer (VCO) 12, a downconverter 13, an A / D conversion circuit 14, a signal strength detector 15, and a memory 16 connected to the signal strength detector 15.
, A C / N determination unit 17, a signal detection determination unit 18, a timing estimation unit 19, a signal extraction unit 20, a memory 21
, A frequency error estimator (FFT) 22, a signal extraction and frequency corrector 23, a memory 24, and a synchronizing word correlator 25.
, A signal detection determination unit 26, and a timing estimation unit 27.

The antenna and RF circuit 11 outputs a high frequency signal (RF) received by an antenna (not shown) or an intermediate frequency signal (IF) obtained by frequency-converting the high frequency signal. The frequency synthesizer 12 supplies the frequency of the control channel to the down converter 13. The downconverter 13 receives the signal from the frequency synthesizer 12, downconverts the signal output from the receiving device to a baseband signal, filters the baseband signal, and outputs the baseband signal. The A / D conversion circuit 14 is connected to the down converter 13 and performs A / D conversion of the baseband signal. The signal strength detector 15 is connected to the A / D conversion circuit 14 and detects the peak value (power) of the received signal. The memory 16 stores the peak value detected by the signal strength detection unit 15 and its timing. The memory 16 has areas used as two buffers Buf0 and Buf1. The C / N determination unit 17 determines the C / N ratio based on the peak value detected by the signal strength detection unit 15.

The signal detection judging section 18 comprises the signal strength detecting section 1
5 to detect whether or not the CCS signal really exists at the frequency being observed. The timing estimating unit 19 is connected to the signal strength detecting unit 15 and the memory 16 and performs rough timing estimation. Signal extraction unit 20
Is connected to the A / D conversion circuit 14 and the timing estimator 19 and extracts a frequency estimation signal. The memory 21 is connected to the signal extracting unit 20 and stores the extracted signal. This memory 21 also has areas used as two buffers Buf0 and Buf1 as in the memory 16. The frequency error estimating unit (FFT) 22 is connected to the signal extracting unit 20 and the memory 21 and outputs the extracted frequency estimating signal to F
The frequency error is estimated by FT conversion and output.

The signal extraction and frequency correction section 23 is connected to the A / D conversion circuit 14, the timing estimation section 19, and the frequency error estimation section 22 to extract the synchronizing word of the CCS signal and output the same from the frequency error estimation section 22. The frequency of the extracted synchronization word is corrected based on the estimated frequency error, and the frequency-corrected synchronization word is output.

The memory 24 includes a signal extraction and frequency correction unit 2
3 and stores the frequency-corrected synchronization word. Further, the synchronizing word correlating unit 25 includes a signal extracting and frequency correcting unit 23.
And the corrected synchronization word connected to the memory 24 and the synchronization word set by the reception synchronization device (a synchronization word known by the reception synchronization device)
Take a correlation with The signal detection unit 26 includes a synchronization word correlation unit 25
And detects whether the CCS signal really exists at the frequency observed from the correlation value and detects the signal.
The timing estimator 27 is connected to the synchronizing word correlator 25 and performs fine timing estimation.

In this embodiment, the digital signal processor 28 includes a signal strength detection section 15, a C / N determination section 1
7, signal detection determination unit 18, timing estimation unit 19, signal extraction unit 20, frequency error estimation unit 22, signal extraction and frequency correction unit 23, synchronization word correlation unit 25, signal detection unit 26, timing estimation unit 27, and signal extraction It also functions as the frequency corrector 29.

The signal detection / judgment unit 18, the frequency error estimating unit 22 and the signal detection / judgment unit 26 are connected to the CPU 32. frequency synthesizer 1 based on the frequency error estimated by the frequency error estimating section 22 Te
2 and control to switch to the next frequency assigned as the control channel when the maximum combined peak value is smaller than the threshold value. Further, a C / N determination unit 17 connected to the signal strength detection unit 15 and determining the carrier / noise ratio is connected to the CPU 32, in order to determine the reliability of the frequency estimation value. The timing estimator 19 and the timing estimator 27 are connected to the CPU 32.
It is used for adjusting the timing of the time base provided in the PU 32. C from C / N judging section 17 /
The N determination information is connected to the CPU 32, which means that the present invention is used especially when the C / N condition is poor. Further, a signal extraction and frequency correction unit 29 connected to the A / D conversion circuit 14 and the frequency error estimation unit 22
The demodulator 30 connected to the signal extracting and frequency correcting unit 29 for demodulating the received signal is not directly related to the present invention.

The reception synchronization procedure in the flowcharts shown in FIGS. 4 to 6 is stored in the ROM constituting the digital signal processor 28, read out from the ROM to the memory (RAM) of the digital signal processor 28, and read out from the digital signal processor 28. 28, the signal strength detection unit 15, the signal detection determination unit 18,
The timing estimator 19, the signal extractor 20, the frequency error estimator 22, the signal extractor / frequency corrector 23, the synonym correlator 25, the signal detector 26, and the timing estimator 27 perform each process of the reception synchronization procedure.

Step SA1 in FIG. 3 corresponds to steps SB1 to SB10 in FIGS. 4 and 5, and step SA2 in FIG. 3 corresponds to step SB11 in FIG. Steps SA3 and S8 in FIG. 3 correspond to step S3 in FIG.
Corresponds to B21. Step SA4 in FIG. 3 corresponds to step SB12 in FIG. 5 and steps SB15 to SB1 in FIG.
7, step SA5 in FIG. 3 corresponds to step SB13 and step SB18 in FIG. Step SA6 in FIG. 3 corresponds to step SB14 and step S14 in FIG.
Step SA7 in FIG. 3 corresponds to step SB20 in FIG.

The process of step SB1 in FIG. 4 corresponds to the signal strength detection unit 15 in FIG. 1, and the process of step SB2 in FIG. 4 corresponds to the signal strength detection unit 15 and the memory 16 in FIG. Steps SB2, SB3, SB5 to 5 in FIG.
The processing in step SB10 corresponds to the timing estimating unit 19 in FIG. Step SB4 in FIG.
Corresponding to Step SB3 and Step SB7 in FIG.
Corresponds to the signal extraction unit 20 that performs processing based on the output of the timing estimation unit 19 in FIG. Step SB11 in FIG. 5 corresponds to the signal detection unit 18 in FIG. Step SB12 in FIG. 5 and steps SB15 to SB17 in FIG. 6 correspond to the frequency error estimator 22 in FIG. Step SB13 and step SB18 in FIG.
The signal detection and frequency correction unit 23 and the synchronizing word correlation unit 2 of FIG.
Corresponding to 5. Step SB14 and Step S in FIG.
B19 corresponds to the signal detection determination unit 26 of FIG.

Next, the processing operation of this embodiment will be described with reference to FIGS. A control signal including a plurality of frames is transmitted from the transmitting device to the receiving synchronization device via the control channel. In a frame of the control signal, for each frame 1 having a plurality of slots (also referred to as bursts) including a plurality of symbols 3, a CCS () including a synchronization word 5 including tens of symbols in a predetermined slot of each frame. (Common Channel Signaling) signal 4 and a frequency estimation signal 6 are multiplexed in a certain slot of each frame.

The signal transmitted via the control channel is received by the antenna and the RF circuit 11. High frequency signal (RF) output from antenna and RF circuit 11
Alternatively, the intermediate frequency signal (IF) is
Is converted into a baseband signal and input to the A / D conversion circuit 14. In successive frames digitized by the A / D conversion circuit 14, digital signals (FIGS.
(1)) is a moving average of a window of a predetermined length (not shown in FIG. 7) (one slot length or slightly shorter time), and a maximum value among peak values of signals obtained from the moving average is obtained. The signal strength detector 15 obtains the peak values from the peak value to the Nth (N = 1, 2,..., N) rank and their timing values (steps SB1 and SB2 in FIG. 4). FIG. 7 shows an example in which N = 7. And (5) of FIG. 7 shows a moving average of the signal strength when the received signal has no noise,
(6) shows the moving average of the signal strength when noise is added to the received signal, and (7) shows the shaded portion in the peak value observation period. Hereinafter, a case where N = 7 will be described.

The signal intensity detector 15 sequentially obtains the peak value from the maximum peak value to the N = 7 rank and its timing value for the first frame (period 50 shown in (2) of FIG. 7). When used (step SB1 in FIG. 4), the peak value and its timing value for respective time it is stored in the buffer Buf 0 of the memory 16 (step SB
2). In the second frame following the first frame (period 51 shown in (2) in FIG. 7), the peak value P ₁₁ and timing values of the first of the first frame (n = 1) is the timing estimate read from the buffer Buf 0 of the memory 16 is supplied to the signal extraction unit 20 by the part 19, the buffer of the second frequency estimation signal frame is extracted memory 21 corresponding to the timing value Buf0
(Step SB3). Then, the signal detection unit 15, by combining the peak value P ₁₁ stored in the timing estimator peak value _{P 21} supplied from 19 and the buffer memory 16 BUF0 stored in the buffer BUF0 memory 16 (step SB4). This first
The processing performed on the first peak value of the first frame and the second frame is performed from the second peak value to the seventh peak value of the first frame and the second frame (steps SB6 to SB6). SB10). For each of the third and subsequent peak values in this processing, the synthesized P _n = P _1n +
_{P 2n (n = 3,4, ......} , 7) is, in the memory 21 B
The larger peak value P _{Buf ((i + 1)% 2} ) stored in one of uf0 and Buf1 (for example, if i = 1, Buf ((i + 1)% 2) means Buf0) (% is (Modulo operator) (step SB9), and when _Pn is large, the larger peak value P
_Pn is stored in the other buffer other than the buffer in which _{Buf ((i + 1)% 2)} is stored, and the buffer that stores the combined peak value in the next loop processing is the one buffer, that is, the two buffers Is switched (step SB10).

When n> 7 (step S
N> N of B6), the maximum peak value max of N = 7
(P _n ) (max (P _n ) means the largest value of P _n , that is, in this example, max (P _n ) =
It is determined by the signal detection determination unit 18 whether P ₆ ) is greater than a predetermined threshold (step SB1).
1). When the maximum peak value max (P _n ) is smaller than the predetermined threshold value (N in step SB11)
O), the process proceeds to step SB21 in FIG. 6 to perform the same processing for the next frequency assigned as the control channel. When it is determined that the maximum peak value max (P _n ) is larger than the predetermined threshold value (YES in step SB11), the maximum peak value m has already been set.
The data (period 52 in FIG. 7) of the frequency estimation signal at the timing (slot) of ax (P _n ) is stored in the memory 21, and the data is subjected to FFT transform by the frequency error estimator 22 to estimate the frequency of the estimation. Error (FFT data 1)
Is obtained (step SB12). Then, the estimated frequency error is supplied to the signal extraction and frequency correction unit 23.

The signal extraction and frequency correction unit 23 generates a synchronizing signal in the CCS signal (period 53 shown in (4) of FIG. 7) included in the slot next to the slot indicated by the timing output from the timing estimation unit 19. and over a predetermined signal range around the synchronizing words (P1 in FIG. 8), together with extracts, the frequency of the synchronization word extracted with frequency error of estimation being supplied from the frequency error estimating section 22 And the frequency-corrected synchronization word is stored in the memory 24. The synchronization word correlator 25 determines in advance the correlation between the synchronization word whose frequency has been corrected and stored in the memory 24 and the synchronization word (a synchronization word known on the receiving side) of the control channel set by the reception synchronization device. The correlation degree and the timing shift Δt are output over the obtained signal range (step SB13). Note that reference numeral 41 in FIG. 8 indicates a timing roughly estimated by detecting the strength of the received signal. Reference numeral 40 denotes a part of the synchronizing word stored in the memory 24, which is developed in a time-series manner.
Indicates its start position. 43, 44, ..., 45 are 4
0 indicates a sequential correlation calculation target portion of 0, and 43a indicates
Indicates the starting position.

In this embodiment, the frequency error is estimated using still another frame (period 56 shown in (2) of FIG. 7), and the synchronization word is correlated. That is, when the correlation value of the obtained correlation is small (the correlation value is small in step SB14), the frequency estimation signal (period 54 shown in ( 3 ) of FIG. 7) after one cycle (the cycle T _{C of the} CCS signal). ) Is extracted by the signal extraction unit 20 and stored in the memory 21, and the stored frequency estimation signal is FFT-transformed by the frequency error estimation unit 22 to obtain the estimated frequency error (FFT data 2) by the frequency error estimation unit 22. (Step SB15). When the correlation value of the obtained correlation is large, that is, when the reliability of Δt is high, the frequency estimation signal after one cycle (T _C ) + Δt taking into account the Δt ((3) in FIG. 7) The period 54) is extracted by the signal extraction unit 20 and stored in the memory 21, and the stored frequency estimation signal is subjected to FFT transformation by the frequency error estimation unit 22 to estimate the estimated frequency error (FFT data 2) by the frequency error estimation unit. 22 (Step SB16).

The estimated frequency error (FFT data 2) (the estimated frequency error obtained in step SB15 or SB16) and the estimated frequency of the frame immediately preceding the frame from which the estimated frequency error was obtained The error (the estimated frequency error obtained in step SB12) and the estimated frequency error obtained by combining the error with the error (the frequency error estimating unit 22) are output to the signal extraction and frequency correcting unit 23 (step S12).
B17).

The signal extraction and frequency correction unit 23 in the synchronization CCS signal contained from the slot of the next indicated by the timing output from the timing estimating section 19 slots into the slots after the 2T _C (slot 55 in Fig. 7) A word is extracted, and the frequency of the extracted synchronizing word is corrected by the estimated frequency error supplied from the signal extracting and frequency correcting unit 23, and the frequency-corrected synchronizing word is stored in the memory 24.

The synchronizing word correlator 25 uses the synchronizing word stored in the memory 24 whose frequency has been corrected and the synchronizing word of the control channel (the synchronizing word known on the receiving side) set by the receiving synchronizer. Is obtained over a predetermined signal range, and the degree of correlation is output (step SB18). When the correlation exceeds the threshold (step SB19 in FIG. 6)
The correlation value is large), and the point in time when the degree of correlation exceeds the threshold value (timing) is taken as the timing with the transmitting side, and the timing on the receiving side is drawn into the timing on the transmitting side to establish the synchronization on the receiving side. (Step SB2
0).

[0046] Further, when the synchronization is established, the signal extracting and frequency correcting section 29 includes the next slot in the slot indicated by the timing output from the timing estimating section 19 in 2 T _C or later slots The control data included in the CCS signal (the slot 55 in FIG. 7 and the subsequent slots) is extracted, and the control included in the CCS signal extracted from the estimated frequency error supplied from the frequency error estimator 22 is extracted. The frequency of the application data is corrected and output.
The demodulator 29 demodulates the control data output from the signal extraction and frequency correction unit 29. If the correlation value does not exceed the predetermined threshold value (small correlation value in step SB19 in FIG. 6), similar processing to the next control channel is started as in step SB11 (step S11).
B21).

As described above, according to the configuration of this embodiment,
Since the peak values corresponding to the timings of the peak values obtained by the moving average of the two frames correspond to each other, and the timing for extracting the frequency estimation signal is obtained at the maximum combined peak value, the timing is obtained. The accuracy of the timing for detecting the signal for frequency estimation can be improved under the reduction of the memory capacity required for the above, which helps to achieve more reliable reception synchronization, and expands the timing extraction to three or more frames. Is also good. Further, a candidate frequency estimated based on a frequency estimation signal obtained in the two frames and a candidate frequency estimated based on a frequency estimation signal obtained in a frame subsequent to the two frames are combined to obtain a frequency. And the synchronization process is performed based on the estimated frequency, and the probability of erroneous frequency estimation can be reduced. Therefore, the frequency estimation accuracy is improved compared to the reception synchronization method described in the above EP publication. obtain. In this frequency estimation, by taking into account the timing shift obtained by the correlation, the frequency estimation accuracy can be further improved. After performing these advantageous processes, the synchronization word is correlated to determine whether or not synchronization can be established, so that reception synchronization can be more reliably achieved.

Second Embodiment FIG. 9 is a diagram showing a first flowchart part obtained by dividing a detailed flowchart for executing a reception synchronization procedure of a reception synchronization apparatus according to a second embodiment of the present invention into three parts, and FIG. FIG. 11 is a diagram showing a second flowchart part obtained by dividing a detailed flowchart for executing the reception synchronization procedure of the reception synchronization apparatus into three parts. FIG. 11 is a detailed flowchart for executing the reception synchronization procedure of the reception synchronization apparatus. It is a figure which shows the 3rd flowchart part divided | segmented into three.

The configuration of this embodiment is significantly different from that of the first embodiment in the following three points. The first point is that in obtaining a rough timing for extracting a frequency estimation signal, in the first embodiment, only a single candidate having a maximum combined peak value is obtained in the first and second frames. In the second embodiment, in the first and second frames, there are two candidates, that is, a maximum combined peak value and a next largest combined peak value after the largest combined peak value. The second point is that when the obtained maximum peak value is larger than the threshold, first, the frequency is estimated by using the maximum composite peak value and the next largest composite peak value after the maximum composite peak value. Frequency error data for the two estimates (hereinafter,
FFT data 1 and FFT data 1 '). Subsequently, in a third frame subsequent to the second frame, the peak value in the third frame corresponding to each of the largest combined peak value and the next largest combined peak value after the largest combined peak value ( Frequency estimation signal)
Of the first embodiment to obtain two estimated frequency error data (hereinafter referred to as FFT data 2 and FFT data 2 '). FFT data 1 and FFT
The second frequency error is estimated by synthesizing the FFT data 1 'and the FFT data 2' while estimating the first frequency error by synthesizing the data 2 with the data 2. The third point is that the CC of the third frame is determined by the two frequency errors.
The purpose of the present invention is to obtain a correlation between the corrected synchronizing word in the S signal and the corrected synchronizing word and the synchronizing word of the control channel (the synchronizing word known on the receiving side) set by the receiving synchronizer. Then, when the larger one of the two correlation values is larger than a predetermined threshold value, the synchronization is established as a timing at which the time point showing the larger correlation value is taken into the transmission side timing.

The first to third points correspond to FIGS. 9 to 1
It is shown in FIG. The first point is configured as follows. That is, FIGS. 9 and 10 show that the memory 16 is provided with three buffers Buf0, Buf1, and Buf2. That is, in step SC3 of FIG. 9, it is shown that the first peak value of the first frame in the second frame is stored in the buffer Buf0, and in step SC4, the first combined peak value is obtained. I have. In step SC5, the second peak value in the second frame is stored in the buffer Buf1.
It is shown to obtain the th composite peak value.

Then, in step SC7, i = 2
Is set to store the third peak value in the second frame in the buffer Buf2. Thus, when the processing enters the first processing loop of the processing loop including steps SC7 to SC12, the second Is stored in the buffer Buf2 in step SC9. It is determined that the third peak value of the second frame stored in step SC9 is combined with the third peak value of the first frame to obtain a third combined peak value in step SC10.
Is shown in

Then, in step SC11, the third combined peak value is compared with the first combined peak value and the second combined peak value (j! = I means j
Is a value other than i. When the third combined peak value is smaller than both the first combined peak value and the second combined peak value (NO in step SC11), the process returns to the beginning of the processing loop, but when the third combined peak value is larger (step SC11). YES) The buffer storing the smallest combined peak value among the first to third combined peak values is set as a temporary buffer for storing the combined peak value in the next loop processing in step SC12.
Is shown in

In step SC12, i = j (P
_BufjSmaller)), P_Bufj= P_n1 o'clock according to
For example, the switching of the storage buffer
The synthesized peak value is stored, and the maximum synthesized peak is stored in Buf1.
The composite peak value next to the value is stored, and the processing of the processing loop is performed.
, The n-th composite peak value of the second frame is
In the state stored in Buf2, Pn becomes P_Buf1
If it is larger than Buf0, the largest combined peak value is recorded.
It is remembered that Buf2 has the next largest peak after the largest combined peak value.
The resulting peak value is stored, and the next processing loop is stored in Buf1.
Stores the (n + 1) th synthesized peak value
Switch each buffer so that_nIs P _Buf0
If it is larger than Buf2, the largest combined peak value is recorded in Buf2.
It is remembered that Buf0 has the next largest peak after the largest combined peak value.
The resulting peak value is stored, and the next processing loop is stored in Buf1.
Stores the (n + 1) th synthesized peak value
Means switching each buffer to be
You. The above is the flowchart portion showing the configuration of the first point.
It is.

After the maximum combined peak value of the N combined peak values and the next largest combined peak value after the maximum combined peak value are obtained as candidates in the two buffers determined by the switching process, the maximum combined peak value is obtained. It is shown in step SC13 that the estimation of the frequency error starts when the peak value is larger than the predetermined threshold value. Step SC1
5. The processing of steps SC17 and SC19 is processing for estimating the frequency error for the maximum combined peak value. That is, after the frequency estimation signal of the buffer corresponding to the largest combined peak value is subjected to FFT transform to obtain frequency error data (FFT data 1) (step SC1).
5) FFT-transforming the frequency estimation signal of the buffer storing the peak value corresponding to the maximum combined peak value in the third frame to obtain frequency error data (FFT data 2)
Is obtained (step SC17). Following this, the FF
The first frequency error is estimated by combining the T data 1 and the FFT data 2 (step SC19). After the frequency estimation signal of the buffer corresponding to the next largest combined peak value after the largest combined peak value is subjected to FFT transform to obtain frequency error data (FFT data 1 ′) (step SC1).
6) FFT-transforming the frequency estimation signal of the buffer that stores the peak value corresponding to the next largest combined peak value after the maximum combined peak value in the third frame to obtain frequency error data (FFT data 2 ′) (Step SC1)
8). Subsequently, the second frequency error is estimated by synthesizing the FFT data 1 'and the FFT data 2' (step SC20). The above is the flowchart portion showing the configuration of the second point.

In step SC21, step SC
The CC of the next frame with the first frequency error estimated in step 19
The synchronization word in the S signal is corrected and the correlation between the corrected synchronization word and the synchronization word of the control channel (the synchronization word known on the receiving side) set by the reception synchronization device is obtained over a predetermined signal range. To obtain a correlation value Corr0 (step SC21).
Further, in step SC22, the synchronization word in the CCS signal of the next frame is corrected by the second frequency error estimated in step SC20, and the corrected synchronization word and the synchronization word (receiving Then, the correlation with the known synchronization word is obtained over a predetermined signal range to obtain a correlation value Corr1 (step SC22). The above is the flowchart portion showing the configuration of the third point.
When the large correlation value obtained in steps SC21 and SC22 is larger than the predetermined threshold value (large correlation value in step SC23), synchronization is established (step SC24). The electrical configuration of the receiving synchronizer of this embodiment is the same as that of the first embodiment.

The reception synchronization procedure in the flowcharts shown in FIGS. 9 to 11 is stored in the ROM constituting the digital signal processor 28, and is transferred from the ROM to the memory (RAM) of the digital signal processor 28 by the digital signal processor 28. By being read and executed by the digital signal processor 28, the signal strength detection unit 15, the signal detection determination unit 18,
Processing of each reception synchronization procedure of the timing estimator 19, the signal extractor 20, the frequency error estimator 22, the signal extraction and frequency corrector 23, the synonym correlator 25, the signal detector 26, and the timing estimator 27 is performed.

The process of step SC1 in FIG. 9 corresponds to the signal strength detector 15 in FIG. 1, and the process of step SC2 is
This corresponds to the memory 16 and the timing estimator 19 in FIG. Step SC3 and step SC5 in FIG. 9 and step SC9 in FIG. 10 correspond to the signal extraction unit 20 and the memory 2 in FIG.
Corresponds to 1. Step SC4 and Step SC in FIG.
6. Step SC10 in FIG. 10 corresponds to the signal strength detector 15 and the memory 16 in FIG. Step S in FIG.
Step C7 and Step SC8, Step SC11 and Step SC12 correspond to the memory 21 of FIG. Step SC13 in FIG. 11 corresponds to the signal detection unit 18 in FIG. Step SC15 to Step SC20 in FIG.
Corresponds to the memory 21 and the frequency error estimator 22 in FIG. Step SC21 and Step SC22 in FIG.
Are the signal detection and frequency correction unit 23, the memory 24,
Corresponds to the synchronous word correlator 25 and the timing estimator 27.
Step SC23 in FIG. 11 corresponds to the signal detection unit 26 in FIG. Steps SC14 and SC25 in FIG. 11 correspond to the CPU 32 and the frequency synthesizer 12 in FIG.

Next, the processing operation of this embodiment will be described with reference to FIGS. 1, 2, and 7 to 11. Down converter 13, A / D from antenna and RF circuit 11
Digital signal processor 28 via conversion circuit 14
Supplying a digital signal to the second embodiment is the same as that of the first embodiment. The digital signal input to the digital signal processor 28 is output to the signal strength detection unit 1.
In 5, the moving average of the signal was obtained while moving the window of a predetermined length with respect to the first frame (the period 50 shown in (2) of FIG. 7) constituting the digital signal. It is also possible to obtain the peak values from the maximum peak value among the peak values of the signal to the Nth rank and store these peak values and their timing values in the buffer BufA of the memory 16 in chronological order (step SC1, FIG. SC2), similar to the first embodiment. In the following description, an example in which N is set to 7 will be described.

When proceeding to the processing of the second frame (period 51 shown in (2) of FIG. 7), the timing estimating unit 1
9 sequentially reads the contents of the buffer BufA of the memory 16 from the beginning and supplies the read contents to the signal extraction unit 20. The signal extraction unit 20 uses the first and second timing values,
A peak value in the second frame corresponding to the timing value is extracted, and the extracted peak value is combined with a corresponding peak value in the first frame, and the buffer Buf of the memory 21 is synthesized.
0, stored in Buf1 (step SC3 to step SC6).

The third combined peak value in the second frame is stored in the buffer Buf2 of the memory 16 (Step SC10). And the third synthesized peak value is
When the third combined peak value is compared with the first combined peak value and the second combined peak value and is smaller than either the first combined peak value or the second combined peak value (NO in step SC11) Returning to the beginning of the processing loop, if it is larger (YES in step SC11), 1
The buffer in which the largest combined peak value of the third to third combined peak values and the largest combined peak value next to the largest combined peak value are left, and the buffer storing the smallest combined peak value is stored in the fourth combined peak value. A buffer for storing the value is set (step SC12). The buffer switching process in step SC12 is performed, for example, by P
_{If Buf0} > P _Buf2 > P _Buf1 , the largest combined peak value of the combined peak values and the largest combined peak value next to the largest combined peak value in the buffer Buf0 and the buffer Buf2 are left as they are, and the buffer B
This is a buffer switching process that can store the combined peak value at the next timing value in uf1. This buffer switching process is performed from the fourth to the seventh. N
When> 7 (step SC8), two candidates, the largest combined peak value within the observation period _Tc and the next largest combined peak value after the largest combined peak value, are stored in the buffer Buf.
0, buffer Buf1, and buffer Buf2.

When the maximum combined peak value is smaller than the threshold value (small in step SC13), a search for a CCS signal is started at the next frequency assigned as a control channel (step SC14). When the maximum combined peak value is larger than the threshold (large in step SC13), FFT conversion is performed on the data in the buffer for each of the largest combined peak value and the next largest combined peak value after the largest combined peak value. To obtain the first frequency error data (FFT data 1) and the second frequency error data (FFT data 1 ') (step SC15, step SC16), and from the timing of the data to the observation period Tc ((2 in FIG. 7)). ) Is performed on the peak value (period 54 shown in (3) of FIG. 7) after the peak value (period 56 shown in FIG. 7), and the third frequency error data (FFT data 2) and the fourth frequency error data (FFT data 2) are obtained. ') (Step SC17, step SC18). Then, the first frequency error estimated by combining the FFT data 1 and the FFT data 2 is obtained (step SC19), and the FFT data 1 ′ and the FF
A second frequency error estimated by synthesizing the T data 2 ′ is obtained (step SC20).

For each of the estimated first frequency error and the estimated second frequency error, the synchronizing word written in the memory 24 (that is, the maximum synthesized peak value and the next largest peak after the maximum peak value) The synchronization word (period 55 shown in (4) in FIG. 7) following the peak value after the observation period _Tc from the value timing is frequency-corrected and the synchronization word corrected and the control channel set by the reception synchronization device are synchronized. Correlations Corr0 and Corr1 with words (synchronization words known on the receiving side) are taken over a predetermined signal period (a in FIG. 8) (step SC21, step SC22).

These two correlation values Corr0, Corr
When the larger one is larger than the threshold value (step SC
23), and synchronization is established (step SC2).
4). Then, when this synchronization is established, the signal extraction and frequency correction unit 29 starts from the slot next to the slot indicated by the timing output from the timing estimation unit 19,
CCS signal contained in T _C after the slot (in FIG. 7 (4)
The control data within the period 55) shown in FIG.
The frequency of the control data included in the CCS signal extracted from the frequency error supplied from the frequency error estimator 22 is corrected and output. The demodulator 29 demodulates the control data output from the signal extraction and frequency correction unit 29. When the larger of the two correlation values Corr0 and Corr1 is smaller than the threshold value (small correlation value in step SC23), the process starts searching for a CCS signal at the next frequency assigned as a control channel (step SC25).

As described above, according to the configuration of this embodiment,
The peak values corresponding to the timings of the peak values obtained by the moving average of the two frames are combined with each other, and the largest combined peak value and the largest combined peak value next to the largest combined peak value are frequency estimation signals. Since the timing for extracting the candidate is obtained, the accuracy of the timing for detecting the frequency estimation signal can be improved while reducing the memory capacity required for obtaining the timing, and more reliable reception synchronization can be achieved. In addition, the timing extraction can be extended to three or more frames.

Further, 2 obtained by the two frames
Estimated based on the frequency data of the candidate estimated based on the two frequency estimation signal candidates and the frequency estimation signal temporally corresponding to the two frequency estimation signal candidates in a frame following the two frames A frequency error is estimated by synthesizing with the candidate frequency data, and a synchronization process is performed based on the estimated frequency error, so that the probability of erroneous frequency estimation can be reduced. The accuracy of frequency estimation can be improved as compared with the method. After performing these advantageous processes, the synchronization word is correlated to determine whether or not synchronization can be established, so that reception synchronization can be more reliably achieved.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there are design changes and the like without departing from the gist of the present invention. Is also included in the present invention. For example, the number of signal strength measurements may be increased or decreased according to the estimated C / N ratio. Further, the threshold value for the correlation value may be changed according to the magnitude of the estimated C / N ratio. By these measures, the time until synchronization can be reduced. Further, the signal extraction and frequency correction unit 23 is divided into a first signal extraction unit and a first frequency correction unit, and the memory 24 is arranged between the first signal extraction unit and the first frequency correction unit. can do. In the first signal extraction unit in this configuration, the signal from the A / D conversion circuit 14 is extracted at the timing from the timing extraction unit 19 and stored in the memory 24.
The first frequency correction unit corrects the frequency of the signal read from the memory 24 with the frequency error from the frequency error estimation unit 22. The signal extraction and frequency correction unit 2
9 may be divided into a second signal extraction unit and a second frequency correction unit. In the second signal extraction unit in this configuration, the signal from the A / D conversion circuit 14 is extracted at a timing determined by the coarse timing from the timing estimation unit 19 and the fine timing from the timing estimation unit 27, and the second frequency is extracted. The frequency of the signal extracted by the correction unit is corrected by the frequency error from the frequency error estimation unit 22.

[0067]

As described above, according to the configuration of the present invention, by combining peak values, the largest combined peak value or the largest combined peak value and the largest combined peak value next to the largest combined peak value are obtained. Since the extraction timing of the frequency estimation signal is obtained based on the timing, the accuracy of the timing of detecting the frequency estimation signal can be improved while reducing the memory capacity required for obtaining the timing, and more reliable While helping to achieve reception synchronization, the timing extraction can be extended to three or more frames. Furthermore, estimation is performed based on one or two candidate frequencies estimated based on one or two frequency estimation signals obtained in the two frames and a frequency estimation signal obtained in a frame subsequent to the two frames. Since the frequency error is estimated by synthesizing the one or two candidate frequency data and performing synchronization processing based on the estimated frequency error, the probability of erroneous frequency estimation can be reduced. Can be improved. In estimating a frequency by combining one candidate frequency and one candidate frequency estimated based on a frequency estimation signal obtained in a frame subsequent to the two frames, a timing shift obtained by correlation is considered. , The accuracy of frequency estimation can be further improved. After performing these advantageous processes, the synchronization word is correlated to determine whether or not synchronization can be established, so that reception synchronization can be more reliably achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing an electrical configuration of a reception synchronizer according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a frame received from a transmission device via a control channel in the reception synchronization device.

[3] Ru FIG der showing a schematic flow chart of the steps reception synchronization of the receiver synchronizer.

FIG. 4 is a diagram illustrating a first flowchart portion obtained by dividing a detailed flowchart for executing a reception synchronization procedure of the reception synchronization device into three parts.

FIG. 5 is a diagram illustrating a second flowchart portion obtained by dividing a detailed flowchart for executing a reception synchronization procedure of the reception synchronization device into three parts.

FIG. 6 is a diagram illustrating a third flowchart portion obtained by dividing a detailed flowchart for executing a reception synchronization procedure of the reception synchronization device into three parts.

FIG. 7 is a timing chart of the reception synchronization of the reception synchronization apparatus .
It is a door.

FIG. 8 illustrates determination of correlation between synchronization words in the reception synchronization apparatus .
FIG .

FIG. 9 is a diagram showing a first flowchart portion obtained by dividing a detailed flowchart for executing a reception synchronization procedure of the reception synchronization device according to the second embodiment of the present invention into three parts.

FIG. 10 is a diagram showing a second flowchart portion obtained by dividing a detailed flowchart for executing a reception synchronization procedure of the reception synchronization device into three parts.

FIG. 11 is a diagram illustrating a third flowchart portion obtained by dividing a detailed flowchart for executing a reception synchronization procedure of the reception synchronization device into three parts.

FIG. 12 is a diagram showing a detailed flowchart for executing a reception synchronization procedure of a conventional reception synchronization method.

[Explanation of symbols]

Reference Signs List 15 signal strength detection unit (part of synthesis unit) 16 memory (part of synthesis unit) 18 signal detection determination unit 19 timing estimation unit (remaining synthesis unit, detection unit, first detection unit, second detection unit) 20) Signal extraction unit (part of estimation unit) 21 Memory (part of estimation unit) 22 Frequency error estimation unit (rest of estimation unit) 23 Signal extraction and frequency correction unit (part of synchronization unit) 24 Memory (synchronization) 25) Synchronization word correlation unit (part of synchronization unit) 26 Signal detection unit (part of synchronization unit) 27 Timing estimation unit (rest of synchronization unit)

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-307730 (JP, A) JP-A-7-321769 (JP, A) JP-A 8-262127 (JP, A) JP-A 8- 307408 (JP, A) JP-A-5-244210 (JP, A) European Patent Application Publication 809377 (EP, A1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04J 3 / 00-3 / 26 H04J 7/00-7/10

Claims (13)

(57) [Claims] 1. A frequency estimating signal transmitted from a transmitting side to a receiving side and a frequency estimating signal from a predetermined number of peak values detected for each frame of a moving average of a sequence of control signals including a synchronization word. A method for selecting and establishing synchronization on the receiving side based on a selected frequency estimation signal and a subsequently detected synchronization word, wherein a predetermined number of values from the top of a peak value in a first frame are determined.
And the corresponding peak value of the timing in the second frame
And synthesizing the signals, and selecting the frequency estimation signal based on the largest combined peak value among the combined peak values. 2. The timing of a frequency estimation signal based on the maximum combined peak value obtained for the two frames .
And selecting the frequency estimation signal corresponding to the frequency estimation signal timing candidate in the third frame following the two frames based on the frequency estimation signal timing candidate. 2. The reception synchronization method according to claim 1, wherein said method is selected. 3. The timing of a frequency estimation signal in a third frame following the two frames is the first frame.
Frame corresponding to the maximum combined peak value in the
Signal for frequency estimation in the second frame at system timing
Frequency corrected by the reception frequency error estimated by
When the correlation between the synchronization word of the second frame and the synchronization word known as the transmitted synchronization word is larger than a threshold value,
In the third frame following the two frames, fine adjustment is made in consideration of the amount of timing shift obtained in the calculation of the degree of correlation, and when the degree of correlation is smaller than a threshold value, In the subsequent third frame, fine adjustment is made without considering the amount of the timing shift.
3. The receiving synchronization method according to claim 2, wherein adjustment is performed . 4. A frequency estimation signal transmitted from a transmission side to a reception side and a predetermined number of peak values detected for each frame of a moving average of a sequence of control signals including a synchronizing word. A method for selecting and establishing synchronization on the receiving side based on a selected frequency estimation signal and a subsequently detected synchronization word, wherein a predetermined number of values from the top of a peak value in a first frame are determined.
When the corresponding peak value of the timing that put the second frame
And the largest combined peak value of the combined peak values obtained by combining the maximum combined peak value and the largest combined peak value next to the largest combined peak value are detected, and the maximum combined peak value and the largest combined peak value detected are detected. The frequency estimation signal for each of the combined peak values is selected based on the next largest combined peak value, and the frequency estimation signal and the two frequency estimation signals in the selected two frame timing candidates are selected . A reception synchronization method, comprising: establishing synchronization on the receiving side based on a synchronization word detected following a signal. 5. A frame timing corresponding to a maximum combined peak value in a third frame following the two frames and a next largest combined peak value after the maximum combined peak value .
The frequency estimation signal is selected in a third frame following the two frames based on the frequency, and each frequency estimation signal in each selected frame timing candidate and the frequency estimation signal in the third frame are selected. 5. The synchronization on the receiving side is established based on a synchronization word detected after the selection of the frequency estimation signal.
The reception synchronization method described. 6. The method according to claim 6, wherein the peak value is a maximum peak value in a frame and a predetermined number of peak values smaller than the maximum peak value and counting from the maximum peak value. 6. The reception synchronization method according to any one of 1 to 5. 7. A frequency estimation signal transmitted from a transmission side to a reception side and a predetermined number of peak values detected for each frame of a moving average of a sequence of control signals including a synchronizing word. What is claimed is: 1. A reception synchronizer for establishing a synchronization on a receiving side based on a selected signal for frequency estimation and a subsequently detected synchronization word, comprising a predetermined number of values from the highest value of a peak value in a first frame.
And the corresponding peak value of the timing in the second frame
And a detecting means for selecting the frequency estimation signal based on the largest combined peak value among the combined peak values combined by the combining means. apparatus. 8. A frequency estimation signal candidate is determined based on the maximum combined peak value obtained for the two frames.
First detection means for selecting , and the frequency estimation signal in a third frame following the two frames based on selection of a candidate for the timing of the frequency estimation signal selected by the first detection means The frequency estimation signal corresponding to the timing candidate of
8. The reception synchronization device according to claim 7, further comprising a second detection unit for selecting . 9. The estimating means for estimating a reception frequency error based on the maximum combined peak value detected in the two frames, a third detecting means following the two frames. Frequency in frame
The timing of the number estimation signal is earlier than the timing in the first frame.
Of the frame timing corresponding to the maximum composite peak value
Estimated by the frequency estimation signal in the second frame
Of the second frame frequency-corrected by the received frequency error
When the degree of correlation between the synchronization word and the synchronization word known as the transmitted synchronization word is greater than a threshold value, in the third frame following the two frames, the timing obtained by the calculation of the degree of correlation is calculated. Fine adjustment taking into account the amount of deviation
Is integer, when the correlation degree is smaller than the threshold, the 2
Timing to fine-tune without considering the amount of timing shift in the third frame following one frame
9. The reception synchronization device according to claim 8, wherein the reception synchronization device is constituted by a communication estimation unit . Wherein said combining means, contact the first frame
And the peak power at certain symbol intervals in time series.
When we detect, it has a memory for storing values and their timing from higher-level of the peak value of power to a predetermined number the number of the corresponding peak value and in the next frame stored in the memory 10. The reception synchronization apparatus according to claim 7 , wherein the power is combined with the power of the frame timing to be synchronized. 11. A frequency estimation signal transmitted from a transmission side to a reception side and a predetermined number of peak values detected for each frame of a moving average of a sequence of control signals including a synchronizing word are used to calculate the frequency estimation signal. What is claimed is: 1. A reception synchronizer for establishing synchronization on a receiving side based on a selected and detected frequency estimation signal and a subsequently detected synchronization word, wherein a predetermined number of values from the highest value of a peak value in a first frame are provided.
And the corresponding peak value of the timing in the second frame
The detected by the first detecting means and, first detecting means for detecting a maximum synthesis peak value and next highest synthesis peak outermost sized synthetic peak value of the synthesized composite peak value bets maximum synthesis peak value and outermost size of the frequency estimation signal based on the next higher synthesis peak value every two synthetic peak value selection synthetic peak
Second detecting means for selecting , and two frame timings selected by the second detecting means.
And a synchronizing means for establishing synchronization on the receiving side based on a frequency estimation signal in a candidate for communication and a synchronization word detected subsequently to the two frequency estimation signals. 12. A frame tie corresponding to the largest combined peak value in the third frame following the two frames and the next largest combined peak value after the largest combined peak value.
A third detecting means for the selecting a frequency estimation signal in said two third frame following the frame based on the timing of each frame timing selected by said third detection means
Synchronization means for establishing synchronization on the receiving side based on each frequency estimation signal in a candidate and a synchronization word detected subsequent to the selection of the frequency estimation signal in the third frame. receiving synchronization apparatus of claim 1 1 wherein. 13. The method according to claim 1, wherein the first detecting means is provided in a first frame.
, The peak power in a time series at certain symbol intervals
When going to detect over the corresponding memory and the peak value stored in the memory and in the next frame for storing values and their timing from higher-level of the peak value of power to a predetermined number the number of 2. A synthesizing means for synthesizing power of a frame timing to be synthesized.
13. The reception synchronization device according to 1 or 12.