JP3299315B2 - Multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system comprising a plurality of processor modules, wherein each processor module expands a plurality of execution units to perform data processing. The present invention relates to a multiprocessor system that enables efficient load distribution control.

2. Description of the Related Art In a multiprocessor system in which a plurality of processor modules each including a CPU and a memory are connected by a bus, a space (executor) is provided between the processor modules.
, And the entire system operates efficiently. It is necessary to distribute the spatial load in the multiprocessor system efficiently.

[0003]

2. Description of the Related Art A space developed in each processor module of a multiprocessor system includes a general space at a user level, a plurality of duplicated servers existing in a system, and a duplicated server existing in one system. There are various.

Conventionally, as a method of distributing these spaces to the processor modules, a method of realizing load distribution by simply equalizing the number of spaces by the mounted processor module or a method of realizing the weight of the space (memory This method employs a method of classifying the space into several types according to the usage amount and the survival time, and realizing load distribution by controlling the number of spaces according to the classified space type.

FIG. 7 shows an example of a space which is distributed and arranged in each processor module according to the former conventional technique.
In the figure, “′” is the space of the standby system. As described above, in the former conventional technique, the load distribution is realized by simply equalizing the number of spaces by the processor module regardless of the space type. FIG. 8 shows an example of a server distributed to each processor module according to the latter conventional technique. As described above, in the latter conventional technique, load distribution among processor modules is realized in units of a space type such as a server.

Here, such a distributed control of the space is executed by the scheduler selecting a processor module from the currently operating processor modules in accordance with a prescribed decision logic and arranging the space. Things.

[0007]

However, the prior art does not consider a fault-tolerant system, and adopts a configuration in which a scheduler provided for each space type controls the distributed arrangement of spaces by its own logic. Therefore, the following problems occur.

(1) When a plurality of related spaces are arranged in a plurality of processor modules, the related spaces may be arranged in different processor modules. When such a phenomenon occurs, a twisting phenomenon occurs, which degrades performance and makes it difficult to control the association between spaces.

(2) An application program that wants to make a correspondence between spaces needs to manage the arrangement and operation state of the processor modules. From now on, the application program cannot easily manage a plurality of processor modules.

(3) In the case where the same server is arranged in a plurality of processor modules and a paired space is arranged for each of them to realize server fault-tolerance, the system load balance when the pairing space is generated. Easily collapses. Also, when a failure occurs,
By arranging the server and the general space in different processor modules, the correspondence between the server and the general space previously associated with each other may be broken. And
At the time of failure recovery, it happens that the same server, which is preferably placed on a separate processor module, is placed on the same processor module.

(4) When the load is distributed by space type, the number of space types is limited, which is not universal. The present invention has been made in view of such circumstances, and has as its object to provide a new multiprocessor system that enables efficient load distribution control of a space.

[0012]

FIG. 1 shows the principle configuration of the present invention. In the figure, 1 is a parent processor module, 2 is a plurality of child processor modules, and 3 is a bus connecting processor modules. Here, one of the child processor modules 2 may be the parent processor module 1.

Reference numeral 10 denotes a PM monitoring mechanism provided in the parent processor module 1, which monitors the occurrence of an IPL or a failure / recovery of the child processor module 2, and 11 denotes a PM definition mechanism provided in the parent processor module 1.
What defines a logical name assigned to the child processor module 2 to indicate a logical processor module.
M management mechanism, which is a PM correspondence table 1 for managing the correspondence between the module ID of the child processor module 2 and the logical name assigned to the child processor module 2
3 and a change unit 14 for changing the management data of the PM correspondence table 13 when a failure occurs in the child processor module 2 or when the failure is recovered. Reference numeral 15 denotes a plurality of execution unit arrangement control mechanisms provided in the parent processor module 1. In this case, the execution body arrangement control to the child processor module 2 is executed.

[0014]

According to the present invention, the PM management mechanism 12 employs a configuration that enables the child processor module 2 to be handled as a logical processor module in accordance with the management data of the PM correspondence table 13.

Then, the execution unit arrangement control mechanism 15 registers the logical name (registered in the PM correspondence table 13 ) for the execution unit.
Adopts a configuration that associates the logical processor module to be executed by associating the logical name), by searching the PM correspondence table 13 and the logical name with the execution of the layout target as a search key, the logical name Specifies the module ID of the child processor module 2 indicated by the child processor module 2 indicated by the specified module ID.
Executables are placed in

For example, the logical name “pm0” is assigned to the child processor module 2 having the module ID “# 001”.
a ”, a logical processor module,
When assigning the logical processor module with the logical name “pm0b” to the child processor module 2 with the module ID “# 002”, “# 00
When the failure occurs in the child processor module 2 of “1” and the child processor module 2 of “# 003” substitutes for the processing, the changing unit 14 sets “# 00”.
The logical name “p” is assigned to the child processor module 2 of “3”.
Since the management data of the PM correspondence table 13 is changed so as to allocate a logical processor module of “m0a”, each execution body arrangement control mechanism 15 receives this change processing, and executes the execution body having the logical name “pm0a”. “# 003”
Is controlled so as to be arranged in the child processor module 2. Thus, the correspondence between the general space and the server that should be executed by the same logical processor module does not break even when a failure occurs or when a failure is recovered.

As described above, the present invention employs a configuration in which the child processor module 2 is displayed in a logical form with respect to the execution body arrangement control mechanism 15.
Can predict the load distribution among the child processor modules 2 even when switching to a duplicated space due to a failure in the space. From this, it is possible to balance the space load between the child processor modules 2 not only at the time of starting up the system and the server, but also after relieving the space failure by the fault-tolerant mechanism.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments. FIG. 2 shows a data structure of the management data of the PM correspondence table 13. As shown in the figure, the PM correspondence table 13 shows that the logical name “pm0a” is assigned to the child processor module 2 having the module ID “# 001”, and the child processor module 2 having the module ID “# 002”. A child processor module 2 having a logical name “pm0b” and a module ID “# 003”
Manages the correspondence between the module ID of the child processor module 2 and the logical name assigned to the child processor module 2 such that the logical name “pm0c” is assigned to the child processor module 2. It is defined as the logical processor module indicated by. Here, the module ID is “# 0
A module to which a logical name is not assigned, such as the child processor module 04 ", is treated as a spare processor module.

The management data in the PM correspondence table 13 is changed by the change means 14 when a failure occurs in the child processor module 2 or when the failure is recovered. FIG. 3 shows an embodiment of a processing flow executed by the changing means 14.

That is, as shown in the processing flow of FIG. 3, first, in step 1, the changing means 14 sends the notification information from the PM monitoring mechanism 10 to the child processor module 2
It is determined whether the notification is a notification of the occurrence of a failure or a notification of a built-in child processor module 2. By the judgment of this step 1,
When it is determined that the notification is a failure occurrence notification of the child processor module 2, next, at step 2, PM is changed to change the correspondence relationship of the logical processor modules allocated to the child processor module 2 having the failure occurrence.
From the correspondence table 13, the logical name assigned to the child processor module 2 in which the failure has occurred is deleted.

Subsequently, in step 3, by referring to the PM correspondence table 13, it is determined whether there is a child processor module 2 having no logical name other than the child processor module 2 to be deleted in step 2. If it is determined that there is a child, the process proceeds to step 4, where the logical name deleted in step 2 is assigned to the found child processor module 2 and registered in the PM correspondence table 13, so that the child The logical processor module assigned to the processor module 2 is assigned to another child processor module 2. On the other hand, when it is determined that the logical processor module does not exist, the process proceeds to step 5 to deactivate the logical processor module assigned to the failed child processor module 2.

On the other hand, if it is determined in step 1 that the notification is a built-in notification of the child processor module 2, then in step 6, a logical processor module is allocated to the built-in child processor module 2. , From the management data of the PM correspondence table 13,
A logical name that is not associated with the active child processor module 2 is searched. That is, a logical processor module that is not associated with the active child processor module 2 is searched.

Subsequently, in step 7, according to the search processing in step 6, it is determined whether or not there is a logical processor module that is not associated with the active child processor module 2, and it is determined that there is. In some cases, the process proceeds to step 8, where the found logical name is assigned to the incorporated child processor module 2 and registered in the PM correspondence table 13, whereby a logical processor module is assigned to the incorporated child processor module 2. Allocate. On the other hand, when it is determined that there is no
Since there are no more logical names to be assigned, the process proceeds to step 9 where the installed child processor module 2 is set as a spare processor module.

In this way, the changing means 14 sets the P when the failure of the child processor module 2 occurs or when the failure is recovered.
The process is performed to change the management data of the M correspondence table 13.

Next, an example of the processing of the present invention will be described with reference to the processing examples shown in FIGS. In the processing example shown in FIG. 4, the five child processor modules 2 identified by the module IDs “# 001” to “# 005”
And a logical processor module with a logical name “pm0a” is allocated to the child processor module 2 of “# 001”, and a logical processor with a logical name “pm0b” is allocated to the child processor module 2 of “# 002”. When a logical processor module with a logical name “pm0c” is allocated to the child processor module 2 of “# 003”, a failure occurs in the child processor module 2 of “# 001”. It is an example of processing when recovery occurs.

At this time, if a failure occurs in the child processor module 2 of “# 001”, a logical processor module with a logical name “pm0a” is assigned to the child processor module 2 of “# 004” functioning as a spare processor module. Is assigned. At this time,
In response to the change processing, the line layout control mechanism 15
An executable having the name “pm0a” is created as a child program of “# 004”.
Control is performed so as to be arranged in the processor module 2. From this, the space operated by the logical processor module “pm0a” is allocated to the child processor module 2 of “# 004” and the processing is continued. Then, when the child processor module 2 of “# 001” recovers, this child processor module 2 is set as a spare processor module.

In the processing example shown in FIG. 5, "# 00
There are three child processor modules 2 identified by module IDs “1” to “# 003”, and “# 00”
The logical name “pm0” is assigned to the child processor module 2 of “1”.
The logical processor module “a” is allocated, the logical processor module “pm0b” having the logical name “pm0b” is allocated to the child processor module 2 of “# 002”, and the logical processor module 2 of “# 003” is logically assigned. When a logical processor module having the name “pm0c” is allocated, “# 00
This is an example of processing when a failure occurs in the child processor module 2 of 1 "and recovery is performed.

At this time, if a failure occurs in the child processor module 2 of "# 001", the logical name "pm0"
The logical processor module “a” is set to the inactive state, and when the child processor module 2 of “# 001” recovers, the logical processor module with the logical name “pm0a” is assigned to the child processor module 2 again. Will be done.

In the processing example shown in FIG. 6, "# 00
There are two child processor modules 2 identified by module IDs “1” and “# 002”, and a logical processor module with a logical name “pm0a” is assigned to the child processor module 2 of “# 001”. , “#
The logical name “pm” is assigned to the child processor module 2 of “002”.
0b "is assigned and the logical processor module with the logical name" pm0c "is set to the inactive state.
This is an example of processing when a failure occurs in the child processor module 2 of “# 001” and recovery is performed.

At this time, if a failure occurs in the child processor module 2 of "# 001", the logical name "pm0"
The logical processor module “a” is set to the inactive state, and when the child processor module 2 of “# 001” recovers, the logical processor module with the logical name “pm0a” is assigned to the child processor module 2 again. Will be done.

As described above, according to the present invention, the child processor module 2 is made to appear logical to the execution unit arrangement control mechanism 15, thereby providing a way to efficiently execute the load distribution control of the space.

[0032]

As described above, according to the present invention,
The arrangement mechanism of various execution units can concentrate on only the load distribution arrangement among the processors of the execution units. And
At the same time, a load distribution arrangement suitable for the entire system is realized.

In addition, even in the case of a space having a duplex configuration in preparation for occurrence of a space failure, the load can be easily distributed in the system after the failure is relieved by arranging the processor module in a logical processor module having rules. become able to.

By associating the logicalized processor modules to be arranged between the arrangement mechanisms of the various execution bodies, it is possible to arrange a plurality of related spaces in a plurality of processor modules. Can be prevented from being distorted in different processor modules.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an explanatory diagram of a PM correspondence table.

FIG. 3 is an embodiment of a processing flow executed by a changing unit.

FIG. 4 is a processing example of the present invention.

FIG. 5 is a processing example of the present invention.

FIG. 6 is a processing example of the present invention.

FIG. 7 is an explanatory diagram of a conventional technique.

FIG. 8 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Parent processor module 2 Child processor module 3 Bus 10 PM monitoring mechanism 11 PM definition mechanism 12 PM management mechanism 13 PM correspondence table 14 Changing means 15 Executing object arrangement control mechanism

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 15/16-15/177 G06F 11/20

Claims (2)

(57) [Claims] 1. A multiprocessor system comprising a plurality of processor modules, wherein each processor module adopts a configuration in which a plurality of execution units are expanded to execute data processing. with it kicked with a split, assigned to the execution body
And PM corresponding table for managing the correspondence between the logical of flop Rosessamoju <br/> Lumpur also used as a logical name to be attached Rina, when a fault occurs or during failure recovery of the processor module,
Changing means for changing management data of the PM correspondence table
And, the management data of the above Symbol PM correspondence table be to see,
The module pointed to by the logical name assigned to the executable
Module ID, and the specified module ID
Multiprocessor system further comprising a running body arranged control Organization for placing the executing entity in the processor module, characterized pointed. 2. In the multiprocessor system according to claim 1, when a number of processor modules equal to or greater than the defined logical name is mounted, processing is performed such that the number of processor modules equal to or more than the defined logical name is treated as a spare processor module. , Features a multiprocessor system.