JP3298709B2 - Even term mixer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog signal mixer, and more particularly, to an analog signal mixer (mixer) which limits a harmonic component of an output signal.

[0002]

An important component used in virtually all wireless transmission and reception systems is the analog signal mixer. The mixer or mixer
It is used in various ways to modulate, demodulate and frequency convert signals. The mixer can be used to upconvert the signal with or without modulation, i.e., convert the frequency of the signal to a higher frequency, and with or without demodulation. , Can be used to down convert the signal, ie, convert the frequency of the signal to a lower frequency.

Referring to FIG. 1, a common prior art mixer configuration is a multiplier mixer, which can be implemented in a number of different ways. The multiplier mixer typically receives a local oscillator (“LO”) signal V ₁ and a radio frequency (“RF”) signal V ₂ and multiplies them to generate an output signal V ₀ . The magnitude and frequency of the output signal V ₀ depends on the magnitude and frequency of each of the input signals V ₁ and V ₂ .
This dependency can be expressed by the following equation.

V ₀ = | V ₁ | · cos (2πf ₁ t) · | V ₂ | cos (2πf ₂ t) = (１ ／) | V ₁ || V ₂ | · ｛cos [2π (f ₁ −f ₂ ) t] + cos [2π (f ₁ + f ₂ ) t]｝ V ₀ = output signal voltage | V ₁ | = magnitude of carrier signal voltage f ₁ = carrier signal frequency (Hertz) | V ₂ | = Referring to modulated signal magnitude f ₂ = modulation signal frequency (Hertz) t = time of the voltage (s) cos [s] = cosine Figure 2 x, one of the conventional mixer configurations in Gilbert multiplier Yes, it is also called a quad mixer. This type of mixer receives a DC bias voltage V _CC via two resistors R _C and a DC
A bias current _IEEE is received. LO signal V ₁ is, each difference is dynamically applied to the parallel differential amplifier having two matched transistors. As shown, the RF signal V ₂
It is differentially applied to another differential amplifier having two matched transistors. As shown, the output signal V ₀ taken across the output of the parallel differential amplifier is a function of the two input signals V ₁ and V ₂ as shown by:

V ₀ = _IE R _C · tanh [V ₁ / (2V _T )] · tanh [V ₂ / 2V _T )] where V ₀ = output signal voltage I _EE = emitter DC supply current (ampere) R _C = collector output resistance (Ω) V ₁ = | V ₁ | · cos (2πf ₁ t) V _T = transistor base-emitter junction forward bias threshold voltage (≒ 25 mV) V ₂ = | V ₂ | · The hyperbolic tangent function of cos (2πf ₂ t) tanh [x] = x Advantages of the Gilbert multiplier-mixer include conversion gain, direct multiplication of the input signal, and good compatibility with monolithic silicon integration techniques. The disadvantages, however, are that the operation has "noise", distortion at signal levels above 2 V _T (unless degeneration is used), and under low voltage conditions, for example, with V _CC below 3 V. The operation may be shabby.

Referring to FIG. 3, in another conventional mixer configuration, for example, a bipolar junction transistor ("BJ
T ") and the like. A BJT in a common-emitter configuration with a collector V _CC and a base V _BB bias voltage receives at its base its LO signal V ₁ and RF signal V ₂ summed. Because the operating characteristics of the transistor are non-linear in nature, the output voltage V ₀ is a function of the input signals V ₁ and V ₂ as follows:

[0007] _{V 0 = V CC -I C R} C = V CC -R C I S e x = V CC -R C I S · [1 + X + X 2/2! + X ^3/3! +. . . ] = K ₀ + K ₁ (V ₁ + V ₂ ) + K ₂ (V ₁ + V ₂ ) ² + K ₃ (V ₁ + V ₂ ) ³ +. . . Incidentally, V _CC = DC power supply voltage (the collector) I _C = collector current (amperes) I _S = BJT saturation current _{(amps) X = (V BB + V} 1 + V 2) / V T V BB = DC supply voltage ( K _C = scalar constant, where C∈ ｛0,1,2,. . . ｝ N! = (N) (n-1) (n-2). . . (1) n
{1, 2, 3,. . . ｝ The advantages of “non-linear device” mixers are conversion gain,
There are ease of design and good noise performance.
However, a major disadvantage is that the unwanted frequency terms, ie, the harmonics, ie, the signal energy at multiples of the frequency resulting from the mixing of the input signals (eg, signal energy at multiples of the frequency of the input signal frequency, and multiples of the input signal frequency) , Sum and difference).

Referring to FIG. 4, another conventional mixer configuration is shown, in this case a diode ring mixer. A ring of four diodes (or sometimes eight diodes) is connected in bridge form to the center-tapped secondary windings of the two transformers, as shown. LO signals V ₁ and RF signal V ₂ is applied to the primary winding of these transformers, and the output signal V ₀ is, as shown, be taken from one center tap of one of these transformers. As with the nonlinear device mixer described above, the output signal V ₀ depends on two input signals V ₁ and V ₂ .

The advantages of the diode ring mixer are:
That is, the performance with respect to noise is good, and the operating frequency range is wide (for example, up to several gigahertz). However, the downside is required LO signal V ₁ of the high level, and a transformer (or hybrid coupler) is a necessary, that it is this arrangement not be suitable too for the monolithic silicon integration technology It is assumed.

[0010]

Accordingly, it is an object of the present invention to provide an improved mixer which incorporates more of the advantages of the prior art mixers described above and which has fewer disadvantages. .

[0011]

SUMMARY OF THE INVENTION A mixer according to the present invention receives and mixes an AC input signal and provides an AC output signal having even and odd terms resulting from the mixing of the input signal. The output signal energy in each of the even terms is greater than the output signal energy in adjacent ones of the odd terms. A first mixing element receives and mixes the AC input signal to provide a first AC mixed signal. A second mixing element receives and mixes the AC input signal to provide a second AC mixed signal. A coupling element connected to the first and second mixing elements receives and combines the first and second AC mixing signals to form A
Provides a C output signal. The AC output signal has even and odd terms resulting from the mixing of the AC input signal, each of the even terms being larger in magnitude than the adjacent one of the odd terms.

In a preferred embodiment of the present invention, each of the first and second mixing elements includes a transistor having two input ports and an output port. One input port receives one of the AC input signals, and the other input port receives another AC input signal via coupling impedance. These two output ports provide the first and second AC mixed signals to a substantially non-reactive impedance (eg, a resistor) and combine therein to provide an AC output signal.

In another preferred embodiment of the present invention, each of the first and second mixing elements has two interconnected transistors, each having an input port and one of the two. Has an output port. One input port receives one of the AC input signals, the other input port receives another AC input signal, and the output port generates one of the AC mixed signals. The connecting element is
A resistor is provided for receiving and combining the AC mixed signal to produce an AC output signal.

A mixer having circuitry in accordance with a preferred embodiment of the present invention preferably has an input that closely approximates the typical characteristic impedance of most video, radio frequency ("RF") and microwave systems. It has an input signal port with impedance and therefore interfaces well with typical, standard video, RF and microwave circuits, devices and appliances.

[0015]

FIG. 5 shows a modeled mixer according to the invention. Each of the two transistors Q _A and Q _B receives two AC input signals from two AC signal sources V ₁ and V ₂ . Transistors Q _A and Q _B
Mixes their respective AC input signals and the two A
Generate C-mixed signals, which are combined at the load, ie, at the output (impedance Z ₀ ), to provide an output voltage V ₀ .

Referring to FIG. 6, transistors Q _A and Q _B can be selectively of several types, ie, bipolar junction transistors (“B
J "), metal oxide semiconductor field effect transistors (" M
OSFET "), junction field effect transistor (" JFE
T "), or a Schottky barrier gate field effect transistor (" MESFET ");
These terminals are connected as shown. However, regardless of which transistor type is used, each transistor can be modeled as shown in FIG. According to this model, each transistor has an input impedance Z _I , across which it applies an input voltage V _I , and an output current generator generates an output current I ₀ , Is a function of the input voltage V _I , ie, I ₀ = f (V _I ). For the above-described transistor type, the relationship between the output current I ₀ and the input voltage V _I can be expressed as follows.

[0017] _{BJT: I 0 = I S ·} esp [V I / V TB] MOSFET: I 0 = B (W / L) (V I -V TM) 2 JFET: I 0 = I DSS (1-V I / V _TJ ) ² MESFET: I ₀ = I _DSM (1−V _I / V _PM ) ² where I _S = BJT saturation current (ampere) I _DSS = JFET drain-source current I with the gate and source short-circuited _DSM = MESFET drain to source current with gate and source shorted V _TB = BJT thermal voltage (≒ 25 mV at 25 ° C.) V _TM = MOSFET threshold voltage V _TJ = JFET pinch-off voltage V _PM = MOSFET pinch-off voltage V _B = MOSFET conduction constant ≒ μC _OX W / (2L) μ = MOSFET channel mobility C _OX = MOSFET gate oxide capacitance (farad) W = MOSFET channel width (Microns) L = MOSFET channel length (microns) Referring to FIG. 8, using the generalized transistor model of FIG. 7 in the mixer model of FIG. 5, the general formula for the output voltage V ₀ is expressed as It is possible.

V ₀ = −Z ₀ [f (V _A ) + f (V _B )] = − Z ₀ [f (V ₁ −V ₂ ) + f (V ₂ −V ₁ )] f (V _A ) + f ( expand the _{V B), f (V a} ) = a 0 + a 1 V a + a 2 V a 2 + a 3 V a 3
^{_{+ A 4 V A 4 ··· f}} (V B) = b 0 + b 1 V B + b 2 V B 2 + b 3 V B 3
+ B ^₄ V _{B 4} ··· Note, a ₀ = 0 th scalar coefficient b ₀ = 0 th scalar coefficients a _m = m th scalar coefficient b _m = m th scalar coefficient m ∈ {1, 2, 3 , 4,. . . ｝ Therefore,

[0019]

(Equation 1)

Suppose that a _n ≒ b _n, where n∈ ｛0,
1, 2,. . . ｝, V ₀ ≒ −Z ₀ [2a ₀ + 2a ₂ (V ₁ −V ₂ ) ² + 2a
₄ (V ₁ −V ₂ ) ⁴ +. . . ] Is obtained. Thus, as will be appreciated from the foregoing, the DC and odd terms of the input signal mixing result, eg, even harmonics, remain, while the odd terms of the input signal mixing result are virtually eliminated. However, even when it is not possible to assume that a _n ≒ b _n , odd terms are substantially suppressed relative to even terms. Because their scalar coefficients are substantially small, ie | a _n
−b _n | << | a _n + b _n |.

As can be seen from the foregoing, if these two input signals have the same fundamental frequency, the mixer according to the invention can be used as a frequency doubler. . In other words, virtually only the even term of the mixing result of the input signal is generated and the quadratic term has a magnitude significance compared to the quartic and higher terms, so that input signals of equal frequency In this case, the mixer of the present invention can function well as a frequency doubler.

Referring to FIG. 9, there is shown a preferred embodiment of a mixer according to the present invention, which comprises two BJT10s.
2 (“Q ₁ ”) and 104 (“Q ₂ ”), and the interconnected collector is connected to a resistor 106 (“R _C ”). The emitter of the first transistor Q ₁ is, resistor 114R ( "R _E1") and the capacitor 114C
(“C _E1 ”) and is connected to the base of the second transistor Q ₂ via a series impedance 114. The emitter of the second transistor Q ₂ is, resistance 116R
Connected "R _E2") and a capacitor 116C ( "C _E2") via a series impedance 116 to the first transistor to Q ₁ base composed. Transistor Q ₁
And Q ₂ at their collectors via a DC voltage source 108 via their shared collector resistance _RC and at their respective emitters a DC current source 110,
Biased by 112. Transistors Q ₁ and Q ₂ are as such passive components, i.e. resistors R _E1 and R _E2 and the capacitor C _E1 and C _E2, are matched to each other. DC current sources 110 and 112 provide equal emitter bias current I _E for transistors Q ₁ and Q ₂ .
Supply. Capacitors C _E1 and C _E2 are connected between the base circuit and the emitter circuit of transistors Q ₁ and Q ₂ by DC.
Giving separation. DC bias voltage V _CC and current I _E
And the passive components R ₁ , R ₂ , R _C , R
Preferred values for _E1 , R _E2 , C _E1 , and C _E2 are as shown in FIG.

One AC input signal V ₁ is connected to a resistor 118
[ "R _1"] (e.g., internal or source resistance of the first AC signal source 122) via, applied to the base of the first transistor Q _1, and the series coupling impedance 1
16 through applied to the second transistor Q ₂ of the emitter. The second AC input signal V ₂ is supplied by a resistor 120 [“R
₂ "] (e.g., internal or source resistance of the second AC signal source 124) via, applied to the second transistor Q ₂ of the base, is applied and through the series impedance 114 to the first transistor to Q ₁ emitter You. As shown, the DC bias signals V _CC and _IE and the AC input signal V ₁
When and V ₂ is applied, the collector current I _C1 and I _C2 of people each for transistor Q ₁ and Q ₂ are generated.
These collector currents I _C1 and I _C2 are generated from a mixture of currents in transistors Q ₁ and Q ₂ , respectively, which are induced from the application of input signals V ₁ and V ₂ . These collector currents I _C1 and I _C2 are coupled at a collector resistance R _C. As a result an AC signal voltage generated across the collector resistor R _C constitutes the output signal V _0.

Referring to FIG. 10, the mixer circuit 1 of FIG.
An AC signal model for 00 is shown, and based on the above description, the AC output signal V ₀ is generated substantially according to the following equation:

[0025] _{V 0 = -R C · (I} C1 + I C2) = -R C I S · {exp [(V BEO + V 1 -V 2) / V T] + exp [(V BEO -V 1 + V 2) _{/ V T]} = -R C} I S · exp [V BEO / V T] · {exp [(V 1 -V 2) / V T] + exp [(V 2 -V 1) / V T]} = _{-R C I S · exp [V} BEO / V T] · 2cosh [(V 1 -V 2) / V T] = -2I E R C · [1+ (V 1 -V 2) 2/2! ^{_{· V T 2 + (V 1}} -V 2) 4/4! ^{_{· V T 4 + (V 1}} -V 2) 6/6!・ V _T ⁶ +. . . _{] ≒ -2I E R C · cosh} [(V 1 -V 2) / V T] Incidentally, R _C = collector resistance value (Ω) I _C1 = Q ₁ collector current (amperes) I _C2 = Q ₂ collector current ( Amps) I _S = BJT saturation current (amps) _IE = emitter current (amps) V _BE0 = base-emitter DC junction voltage V ₁ = carrier (“LO”) signal voltage = | V ₁ | · cos (2πf ₁ t) V ₂ = modulation (“RF”) signal voltage = | V ₂ | · cos (2πf ₂ t) V _T = transistor base-emitter junction forward bias threshold voltage (電 圧 25 m at 25 ° C.)
V) f ₁ = carrier signal frequency f ₂ = modulation signal frequency t = time ^{(seconds) exp {x} = e x} cosh {x} = hyperbolic cosine of x function as will be understood from the foregoing, the output signal V _{The zero} frequency spectrum has even and substantially suppressed odd terms of the result of mixing the input signals V ₁ and V ₂ .
That is, the even terms are Af ₁ + Bf ₂ , Bf ₁ + Af ₂ , |
Af ₁ −Bf ₂ | and | Bf ₁ −Af ₂ |, and the odd terms are Cf ₁ + Df ₂ , Df ₁ + Cf ₂ , |
Cf ₁ −Df ₂ | and | Df ₁ −Cf ₂ |, where (A + B) ∈ ｛2, 4, 6,. . . ｝ And (C +
D) {1, 3, 5,. . . ｝. Furthermore, the limited frequency components in this output signal V ₀ can be generated by discrete reactive components such as capacitors or inductors, or filter functions (eg, high-pass, low-pass,
Transmission line elements typically used to perform bandpass or bandstop (eg, open circuit or short circuit stubs)
It should be understood that this has been achieved without the need to use tuning elements such as.

The mixer according to the present invention has several additional advantages, such as good noise performance, low distortion, low quiescent current conditions and low DC bias voltage (eg, 3V). Below). Furthermore, the mixer according to the invention provides a conversion gain,
And especially one type of activation device (eg NPN BJ
Since only T) is required, it has a design structure suitable for monolithic silicon integration technology. FIG.
Is disadvantageous in that the two input signals V ₁ and V ₂
Is relatively low.

An exemplary comparison of some operating characteristics between a mixer according to the present invention and a conventional Gilbert multiplier (multiplier) mixer is shown in Table 1 below.

TABLE 1 Comparison of Even Term Mixer with Conventional Mixer Gilbert Gilbert Even Term Unit V _CC = 5 V, V _CC = 3 V, V _CC = 3 V Z _O = 50 ohms Z _o = 200 ohms Z _o = 200 ohms Noise value 17 9.45 dB Conversion gain 1.8 0.9 2.4 dB Output level 0.29 0.63 0.53 V _pp (“PldB”) Supply current 8.1 6.35 mA LO-to- RF ≒ 30 ≒ 30 ≒ 6 dB Rejection Referring to FIG. 11, another preferred embodiment of a mixer according to the present invention is shown, which is interconnected substantially as described above and FIG. It has an active component and a passive component illustrated in, as shown, the transistor 202 ( "Q _1"), 204 several passive elements in ( "Q _2") Nobesu circuit 226 (R _B1 ), 23
2 (“C _B1 ”), 228 (“R _B2 ”), 234
(“C _B2 ”) and the DC base bias voltage V _BB .

The second DC voltage source 230 is connected to the base resistor R _B1
And via the R _B2, applying a DC bias voltage V _BB to the transistors Q ₁ and Q ₂ Nobesu. The first AC input signal V ₁ is provided to the base of the first transistor Q ₁ via a series resistor 218 (“R ₁ ”) and via a series coupling capacitor 232 (“C _B1 ”). . 2nd A
The C input signal V ₂ is supplied to the base of the second transistor Q ₂ via a series resistor 220 (“R ₂ ”) and a series coupling capacitor 234 (“C _B2 ”).

Referring to FIG. 12, another preferred embodiment of a mixer according to the present invention is shown, which comprises two NPs.
NBJT 302 (“Q ₁ ”), 304 (“Q ₂ ”), two PNP BJTs 342 (“Q ₃ ”), 344
It has ( "Q _4") and the collector resistor 306 ( "R _C"), which are connected substantially as shown. A DC voltage source 308 applies a DC bias voltage V _CC to the collectors of transistors Q ₁ and Q ₂ via resistor R _C. Transistor Q ₁ Nobesu and emitter, respectively, are connected to the emitter and the transistor Q ₄ Nobesu transistor Q _3. Transistor Q ₂ Nobesu and emitter, respectively, are connected to the emitter and the transistor Q ₃ Nobesu transistor Q _4. The collector of the transistor Q ₃ and Q ₄ is connected to ground. DC current sources 346 and 348 provide equal DC bias current I
The _B, and applied to the node connecting the transistors Q ₁ and Q ₃ Nobesu and emitter to respective transistors Q ₂ and Q ₄ Nobesu and emitter.

First AC input signal V ₁ (eg, LO)
But it is applied to the emitter of the transistor Q ₃ Nobesu and transistor Q _2. A second AC input signal V ₂ (eg, RF) is applied to the base of transistor Q ₄ and the emitter of transistor Q ₁ . According to the previous description of the mixer circuit of FIGS. 9 and 11, the collector current I
_C1 and I _C2 are generated, the currents combining at resistor R _C and generating an output signal voltage V ₀ substantially according to the following equation:

[0032] _{V 0 ≒ -2KI B R C ·} cosh [(V 1 -V 2) / V T] Incidentally, V ₀ = the output signal (V) I _B = base Subaiasu current (A) R _C = collector output Resistance (Ω) V ₁ = carrier (“LO”) signal (V) = | V ₁ | · cos (2πf ₁ t) V ₂ = modulation (“RF”) signal (V) = | V ₂ | · cos ( 2πf ₂ t) V _T = transistor base-emitter junction forward bias threshold voltage (≒ 25 m at 25 ° C.)
V) f ₁ = carrier signal frequency (Hz) f ₂ = modulation signal frequency (Hz) T = time (seconds) K = constant relating to collector current = _ISN / _ISP ≒ ( _ICN · _ICP ) · exp [ V _BEP -V _BEN ) / V
_T ] I _SN = NPN BJT saturation current (A) I _SP = PNP BJT saturation current (A) I _CN = NPN BJT collector current (A) I _CP = PNP BJT collector current (A) V _BEP = PNP BJT base emitter voltage V _BEN = NPN BJT to database emitter voltage exp ^[x] = with reference to e x cosh [x] = x hyperbolic cosine function 13, an exemplary frequency spectrum of the output signal V ₀ is shown ing. Based on the above description, V
₀ frequency spectrum, and a odd term has been suppressed and even terms of the mixing result of the input signals V ₁ and V ₂ (e.g., less than -40 dB). As even terms, Af ₁ + Bf
₂ , Bf ₁ + Af ₂ , | Af ₁ −Bf ₂ | and | Bf ₁
−Af ₂ | and as an odd term, Cf ₁
+ Df ₂ , Df ₁ + Cf ₂ , | Cf ₁ −Df ₂ | and |
Df ₁ −Cf ₂ |, and (A + B) ∈ ｛2
4, 6,. . . ｝ And (C + D) ∈ ｛1,3
5 ,. . . ｝.

The frequency spectrum of the exemplary output signal V ₀ of FIG. 13 has been calculated based on the above description for the preferred embodiment of FIGS. 9 and 10 as follows.

[0034] _{V 0 = -2I E R C ·} cosh [(V 1 -V 2) / V T] = (0.5) · cosh [{0.03162 · cos (2πf 1 t) - 0.01 · cos (2πf ₂ t)｝ / 0.0259] Note that -20d in a 0.03162≡50Ω system
−30 dBm f ₁ = 1 gigahertz = 1 × 10 ⁹ Hz f ₂ = 900 megahertz = 900 × 10 ⁶ Hz in a Bm 0.01Ω50Ω system Relative amplitude (quadratic term |
It is expressed in decibels [“dB”] relative to f ₁ −f ₂ |. ) Are shown in Table 2 below. The odd term is at least 40 dB lower than the quadratic term | f ₁ −f ₂ |.

[0035] Table 2 Section order amplitude _{(dB) | f 1 -f 2} | 2 0 2 | f 1 -f 2 | 4 -31.2 2f 2 2 -14.7 | f 1 + f 2 | 2 0 2f ₁ 2 +3.6 3f ₁ -f ₂ 4 -24.9 2 | f ₁ + f ₂ | 4 -31.2 3f ₁ + f ₂ 4 -24.9 4f ₁₄ -26.9 The preferred embodiment of the present invention described above. A mixer with an example circuit topology has an input signal port with an input impedance that closely approximates the typical characteristic impedance of most video, RF, and microwave signal systems. Thus, such mixers interface well with typical standard video, RF and microwave circuits, devices and appliances. This can be better understood by referring to FIGS. 14A-14C in the following description.

A typical BJT provides a base terminal impedance of several hundred ohms when operated in a common emitter configuration with a collector bias current of a few milliamps. This impedance is too high for efficient power transfer to the base terminal in a typical 50Ω or 75Ω video, RF or microwave signal system.

Referring to FIG. 14A, there is shown a general circuit model used for analyzing the input impedance of a common emitter amplifier. Based on this model, the input impedance Z _in is able to calculate the next as.

[0038] _{Z in = β (r e +} Z e) = β (V T / I C + Z e) In addition, beta = common emitter current gain = f (Ω) = f ( 2πf) r e = intrinsic emitter resistance Z _e = emitter circuit impedance V _T = base-emitter junction forward bias threshold voltage I _C = collector current β = 50, V _T = 0.0259 V, I _C = 2 mA and Z
Assuming that _e = 0 (a typical example operating condition), we have:

Z _in = β (V _T / I _C + Z _e ) = 50 (0.0259 / 0.002 + 0) ≒ 648Ω As can be understood from the foregoing, a common-emitter amplifier operating under typical conditions Is significantly higher than 50Ω, and
Matching is not good for Ω signal sources. At higher frequencies, the transistor current gain β, which is a function of frequency, ie β = f (Ω) = f (2πf), decreases and creates a phase delay. Thus, while it is possible to reduce the input impedance at higher frequencies, the current phase delay introduced by β causes the input of the amplifier to be capacitive. This causes the amplifier to continually be poorly matched to a 50 ohm source. On the other hand, when operated in a common base configuration with a collector bias current of a few milliamps, a typical BJT provides an emitter terminal impedance on the order of a few ohms. This impedance is 5
It is too low for efficient power transfer from a 0 or 75 ohm source.

Referring to FIG. 14B, a general circuit model used for analyzing the input impedance of the common base amplifier is shown. Based on this model, the input impedance Z _in can be calculated as follows.

Z _in = (1 / g _m + Z _b / β) = (V _T / I _C + Z _b / β) where g _m = transconductance of transistor Z _b = base circuit impedance V _T = 0.0259 V, I _C = 2 mA, Z _b = 0, β =
Assuming 50 (typical exemplary operating conditions):
The following results are obtained.

Z _in = (V _T / I _C + Z _b /β)=(0.0259/0.002+0/50)≒12.9Ω As will be understood from the foregoing, operating under typical conditions. The input impedance for the common base amplifier is significantly lower than 50 ohms, so the matching for a 50 ohm source is poor. It is often the case that the input impedance rises at higher frequencies, both due to the effects of both a reduction in the transistor current gain β (as described above) and the presence of the parasitic ohmic base resistance.
Due to the phase delay associated with β (as described above), the rising input impedance appears as inductive. Thus, the input impedance provides a continuously poor match for a 50Ω signal source.

However, for the mixer topology according to the present invention, when operated with a bias current of a few milliamps, the input terminal impedance is almost equal to the video,
It is very close to the typical characteristic impedance of RF and microwave signal systems.

Referring to FIG. 14C, the input impedance of a mixer (eg, shown in FIG. 9) according to a preferred embodiment of the present invention can be calculated as follows.

[0045] _{Z in = V in / I in} = V 1 / (i b + i e) = V 1 / [V 1 / {β (r e + Z s)} + V 1 / (r e + Z s)] = ( _{r e + Z S) / (} 1 + 1 / β) = (V T / I C + Z S) / (1 + 1 / β) V T = 0.0259V, I C = 2mA, Z S = 50, β
= 50 (typical exemplary operating conditions), the following results are obtained.

Z _in = (V _T / I _C + Z _S ) / (1 + 1 / β) = (0.0259 / 0.002 + 50) / (1 + 1/50) ≒ 61.7Ω As can be understood from the above description, The input impedance of the mixer according to the invention is close to the typical 50Ω impedance of the signal source driving the other input. Therefore, if both inputs are driven by such a signal source, the input impedance of either input will be about 62Ω. This represents a standing wave ratio (“SWR”) of 1.23: 1 in a 50Ω system. Therefore, both sources are reasonably matched.

This matching is maintained at moderately high frequencies for two reasons. First, inductive impedance effect observed due to an increase in endogenous emitter resistance r _e is reduced. Because, in order to influence the input impedance, r _e is, as in the case of the common base amplifier, rather than just r _e, r _e and the sum of the source impedance (i.e., r
_e + Z _S ).
Secondly, the reduction in current gain β of the transistor is less impact on the input impedance, the frequency dependence β decreases at higher frequencies, to partially offset the increase in r _e.

Although specific embodiments of the present invention have been described in detail above, the present invention should not be limited to these specific examples, but may be variously modified without departing from the technical scope of the present invention. Of course is possible.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a conventional multiplier (multiplier) mixer.

FIG. 2 is a schematic diagram of a conventional Gilbert multiplier-mixer circuit.

FIG. 3 is a schematic diagram of a conventional nonlinear device mixer circuit.

FIG. 4 is a schematic diagram of a conventional diode ring mixer circuit.

FIG. 5 is a schematic diagram showing an AC circuit model of a mixer configured according to one embodiment of the present invention.

FIG. 6 is a schematic diagram showing terminal configurations for transistors that can be used in a mixer configured according to one embodiment of the present invention.

FIG. 7 is a schematic diagram showing a general AC signal model of a transistor.

FIG. 8 is a schematic diagram showing the circuit model of FIG. 5 using the transistor model of FIG. 7;

FIG. 9 is a schematic diagram illustrating a mixer configured according to one embodiment of the present invention.

FIG. 10 is a schematic diagram showing an AC signal mixing model of the mixer of FIG. 9;

FIG. 11 is a schematic diagram illustrating a mixer configured according to another embodiment of the present invention.

FIG. 12 is a schematic view showing a mixer configured according to still another embodiment of the present invention.

FIG. 13 is a graph showing frequency components of an output signal of a mixer configured based on one embodiment of the present invention.

FIG. 14A is a schematic diagram showing a circuit model used when calculating the input impedance of a common emitter amplifier.

FIG. 14B is a schematic diagram showing a circuit model used when calculating the input impedance of the common base amplifier.

FIG. 14C is a schematic diagram showing a circuit model used when calculating the input impedance of a part of the mixer configured according to one embodiment of the present invention.

[Explanation of symbols]

Q transistor V AC signal source Z ₀ output impedance

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-51-88115 (JP, A) JP-A-2-78305 (JP, A) JP-A-1-202002 (JP, A) 129815 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03D ^7/ 12-7/14

Claims (24)

(57) [Claims] 1. A signal mixer for receiving and mixing first and second AC input signals and providing an even and substantially suppressed odd term of the mixing result of the first and second input signals to an AC output signal. in vessels, a first and a second AC first mixer means and mixing receives an input signal to provide a first AC mixed signal, the
DC-biased and related in one linear operating region
Having a first input impedance associated therewith and
First and second AC input signals are connected to the first input impedance
First mixer means are provided at both ends of the first and second AC mixers for providing a second AC mixing signal.
Second mixer means coupled to said first mixer means for receiving and mixing an input signal, wherein said second mixer means is in a second linear operating region.
A second input input that is DC biased and associated therewith.
The first and second AC inputs
A force signal is received at both ends of the second input impedance.
A second mixer means is provided for receiving and combining the first and second AC mixed signals to provide an AC output signal and coupled to the first and second mixer means. Means are provided,
The C output signal has a first plurality of even terms and a second plurality of odd terms of the result of mixing the first and second AC input signals, and each of the first plurality of even terms is 2. The signal mixer according to claim 1, wherein said second plurality of odd terms are larger in size than adjacent ones. 2. The method of claim 1, wherein the first mixer means has a first series impedance and a first transistor, wherein the first transistor has at least one of the first AC input signals. A first terminal for receiving the first series impedance and a second terminal coupled to the first series impedance.
A signal mixer comprising: a second terminal for receiving a C input signal; and a third terminal for providing the first AC mixed signal. 3. The apparatus of claim 2, wherein said second mixer means comprises a second series impedance and a second transistor, said second transistor being at least a portion of said second AC input signal. And a first terminal for receiving the first A
A signal mixer comprising: a second terminal for receiving a C input signal; and a third terminal for providing the second AC mixed signal. 4. The method of claim 1, wherein the coupler means before
Serial has a resistor that is coupled to the first and second mixer means, said first and second AC mixing signal, respectively, wherein
A signal mixer having first and second AC currents through a resistor , and wherein the AC output signal comprises an AC voltage. 5. A signal mixer for receiving and mixing first and second AC input signals and providing an even and substantially suppressed odd term of the mixing result of the first and second input signals to an AC output signal. A DC bias in the first linear operating region and a first
And a first input impedance having a second opposing end.
Connected to the first transistor and the first AC input signal.
The first end of the first input impedance to take
A primary input circuit connected to the first DC signal and a second
The first to receive at least a portion of an AC input signal;
Secondary connected to the second end of the input impedance
An input circuit and an output for supplying a first AC mixed signal
Preparative and first transistor circuit is provided that includes a DC biased in the second linear operation region and the first及
And a second input impedance having a second opposing end.
A second transistor connected to the second AC input signal;
To receive the first of the second input impedances
A primary input circuit connected to the end, a second DC signal and
To receive at least a portion of the first AC input signal
Connected to the second end of the second input impedance
To provide a secondary input circuit and a second AC mixed signal
A second transistor circuit having an output of the second transistor circuit, the second transistor circuit output being coupled to the first transistor circuit output, and providing the first and second AC mixed signals. A resistor is provided for coupling to the output of the first and second transistor circuits for receiving and providing an AC output signal, wherein the AC output signal is a second one of the mixed result of the first and second AC input signals. It has one plurality of even terms and a second plurality of odd terms,
The signal mixer according to claim 1, wherein each of the first plurality of even-numbered terms is larger than an adjacent one of the second plurality of odd-numbered terms. 6. The first transistor according to claim 5 , wherein
A secondary input circuit having a transistor terminal;
Are connected to it, signal mixer characterized by having a coupling impedance for coupling thereto a said at least a portion received in said second AC input signal. 7. The second transistor according to claim 6 , wherein
A secondary input circuit having a transistor terminal;
A signal mixer coupled thereto and having a coupling impedance for coupling the received at least a portion of the first AC input signal thereto . 8. A signal for receiving and mixing first and second AC input signals and providing an even and substantially suppressed odd term of the mixing result of the first and second input signals to an AC output signal. in mixer, it provided the first transistor having a primary terminal for receiving a first DC signal, and the secondary terminal for receiving a first AC input signal, and a tertiary terminal for providing a first AC mixed signal It is and, provided the primary terminal for receiving a second DC signal, the second transistor having a second terminal for receiving the second AC input signal, and a tertiary terminal for providing a second AC mixed signal is and the tertiary terminal of the second transistor is coupled to a tertiary terminal of the first transistor, wherein the primary <br/> terminal coupled to the secondary terminal of the second transistor, the first transistor of A secondary terminal coupled to the next terminal, and the third transistor is provided which comprises a tertiary terminal, and the primary <br/> terminal coupled to the secondary terminal of the first transistor, the second a secondary terminal coupled to the primary terminal of the second transistor, tertiary terminal and the fourth transistor having a provided, said first and second transistors of the tertiary terminal being coupled to said first and second A resistor for receiving an AC mixed signal and for providing an AC output signal, wherein the AC output signal includes a first plurality of even terms of a mixing result of the first and second AC input signals; And an odd term of
The signal mixer according to claim 1, wherein each of the first plurality of even-numbered terms is larger than an adjacent one of the second plurality of odd-numbered terms. 9. The transistor according to claim 8 , wherein the first, second, third, and fourth transistors include first, second, third, and fourth bipolar junction transistors, respectively. Associated therewith has a base-emitter junction forward bias threshold voltage, and each of the first and second bipolar junction transistors has associated therewith a first base-emitter voltage, a base current and a second Having a collector current and each of the third and fourth bipolar junction transistors has associated therewith:
It has a second base-emitter voltage and a second collector current, and the AC output signal is _{approximately, V 0 ≒ -2I B R C} (I CN / I CP) · exp [(V BEP -V BEN ) / V _T ] · cash [(v ₁ −V ₂ ) / V _T ] where V ₀ = voltage value of AC output signal _IB = base current value R _C = resistance value of resistor V ₁ = first AC input Signal voltage value V ₂ = second AC input signal voltage value V _T = base-emitter junction forward bias threshold voltage value I _CN = first collector current value I _CP = second collector current value V _BEP = first voltage Two base-emitter voltage values V _BEN = first base-emitter voltage value exp [(V _BEP −V _BEN ) / V _T ] = (V _BEP −V _BEN ) / exponential function of V _T cosh [(V ₁ −V ₂ ) / V _T ] = [(V ₁ −V ₂ ) / V _T ] given by the equation of the hyperbolic cosine function A signal mixer. 10. Receiving first and second AC input signals
Mixing together and the mixing result of the first and second input signals
The even and substantially suppressed odd terms of the AC output signal
In the given signal mixing method,First DC biased signal in first linear operating region
First and second to opposite ends of the input impedance of the mixer
Input AC input signal The first and second AC input signalsTo the first signal mixer
InMixing to give a first AC mixing signal,Second signal DC biased in the second linear operating region
First and second to opposite ends of the input impedance of the mixer
Input AC input signal The first and second AC mixed signalsTo the second signal mixer
MixedAnd second ACmixtureGive the signalCombining the first and second AC mixed signals to form an AC output signal;
Give a number,  Each of the above steps, wherein the AC output signal is
A first plurality of results of mixing the first and second AC input signals;
Having an even term and a second plurality of odd terms, and
Each of the first plurality of even terms is the second plurality of odd terms.
A signal characterized by being larger in magnitude than its neighbors
Mixing method. 11. The method of Claim 1 0, wherein the first signal mixing
Mixing the first and second AC input signals in a combiner to provide a first AC mixed signal; inputting at least a portion of the first AC input signal to a first terminal of a first transistor; Inputting the second AC input signal to a first series impedance coupled to a second terminal of the first transistor, and outputting the first AC mixed signal from a third terminal of the first transistor. Signal mixing method. 12. The method of claim 1 1, wherein the second signal mixing
Mixing the first and second AC input signals in a combiner to provide a second AC mixed signal; inputting at least a portion of the second AC input signal to a fourth terminal of a second transistor; An AC input signal is input to a second series impedance coupled to a fifth terminal of the second transistor, and the second AC mixed signal is output from a sixth terminal of the second transistor. Signal mixing method. 13. The method of claim 1,0In the first and second
Two ACmixtureSignalJoinAnd ACoutputStep to give signal
IsThe first and second AC mixed signals are the first and second AC mixed signals, respectively.
Receiving AC current, Coupling the first and second AC currents at a resistor; The AC output signal is provided as an AC voltage at the resistor.
Pay,  A signal mixing method comprising: 14. Mixing the first and second AC input signals;
And an even number term of the result of mixing the first and second input signals;
A signal mixture for providing a substantially suppressed odd term to the AC output signal.
The first AC input signal to the first transistor circuit.onceInput times
Enter the road,The first transistor circuit is in a first linear operation
DC biased in the region and first and second opposed ends
A second input impedance associated with the first input impedance
One transistor, and the first transistor
The next input circuit is the first end of the first input impedance.
Department,  The first DC signal and at least a portion of the second AC input signal
Of the first transistor circuitsecondaryInput to the input circuit,Previous
The first transistor secondary input circuit is connected to the first input impedance.
-Connected to the second end of the dance,  A first AC mixed signal from an output terminal of the first transistor circuit;
And outputs the second AC input signal to the second transistor circuit.onceEntering
Input to the power circuit,The second transistor circuit is a second linear
DC biased in the operating region and the first and second pairs
Associated with a second input impedance having an opposite end
A second transistor, and the second transistor
The primary input circuit of the second input impedance
Connected to one end,  A second DC signal and at least a portion of the first AC input signal
And the second transistor circuitsecondaryInput to input circuit
AndThe second transistor secondary input circuit includes the second input
Connected to the second end of the impedance,  From the second output terminal of the second transistor circuit, the second AC mixed
Output the combined signal, and register the first and second AC mixed signals.
Input to the first and second AC input signalsOf the mixed resultFirst plural
Output signal having an even term and a second plurality of odd terms
ToFrom the resistanceOutputting, comprising the above steps, wherein the first plurality of even terms
Each of which is greater than an adjacent one of the second plurality of odd terms.
A signal mixing method having a large size. 15. The method of claim 1 4, the step of inputting at least part of said first DC signal and the second AC input signal to the secondary input circuit of the first transistor circuit, said second AC input signal The signal mixing method according to claim 1, wherein said at least a part of said first transistor circuit is input to a coupling impedance having a part of said first transistor circuit. 16. The first AC input signal according to claim 15 , wherein the step of inputting the second DC signal and at least a part of the first AC input signal to a secondary input circuit of the second transistor circuit is performed. The signal mixing method according to claim 1, wherein said at least a part of said signal is input to a coupling impedance having a part of said second transistor circuit. 17. Mixing the first and second AC input signals and
The even and real terms of the result of mixing the first and second input signals.
Providing an AC output signal with qualitatively suppressed odd terms
Signal mixing method, Connect the primary terminal of the first transistor to the secondary terminal of the third transistor
Input the first DC signal to the node connected to the terminal, Secondary terminal of the first transistor and a fourth transistor
Input the first AC input signal to the primary terminal of A first AC mixed signal from a tertiary terminal of the first transistor
And output The primary terminal of the second transistor is connected to the fourth transistor
Input a second DC signal to a node connected to the secondary terminal, A secondary terminal of the second transistor and the third transistor
Input the second AC input signal to the primary terminal of the A second AC mixed signal from the tertiary terminal of the second transistor
And output Inputting the first and second AC mixed signals to a resistor; First plurality of mixing results of the first and second AC input signals
Output signal having an even term and a second plurality of odd terms
Is output from the resistor, Having the above steps, wherein the first plurality of even terms
Each of which is greater than an adjacent one of the second plurality of odd terms.
A signal mixing method having a larger size. 18. The transistor according to claim 17 , wherein the first, second, third, and fourth transistors include the first, second, third, and fourth bipolar junction transistors, respectively. Has a base-emitter junction forward bias threshold voltage associated therewith, and each of the first and second bipolar junction transistors has associated therewith a first base-junction transistor. An emitter voltage, a base current, a first collector current, and each of the third and fourth bipolar junction transistors has a second base-emitter voltage and a second collector current associated therewith. the has, and the step of outputting the AC output signal is _{approximately, V 0 ≒ -2I B R C} (I CN / I CP) · exp [(V BEP -V BEN) / V T] · cosh _{[(V 1 -V 2) /} V T Incidentally, V ₀ = voltage value of the AC output signal voltage value I _B = base over scan current value R _C = voltage value V ₂ = the second AC input signal of the resistance value of V ₁ = first AC input signal in the resistance of V _T = Base-emitter junction forward bias threshold voltage value I _CN = first collector current value I _CP = second collector current value V _BEP = second base-emitter voltage value V _BEN = first base Exponential function of the emitter voltage value exp [(V _BEP −V _BEN ) / V _T ] = (V _BEP −V _BEN ) / V _T cosh [(V ₁ −V ₂ ) / V _T ] = [(V ₁ −V ₂ ) / V _T ], wherein the AC output signal is output according to a hyperbolic cosine function. 19. Receiving first and second AC input signals
And mixing, and the mixing result of the first and second input signals
Output having even and substantially suppressed odd terms
In a signal mixer that supplies a signal, First and second AC inputs to provide a first AC mixed signal
A first mixer means for receiving and mixing the force signals;
And DC biased in the first linear operating region, and
A primary terminal and a secondary terminal for receiving the second AC input signal
And a tertiary terminal for supplying the first AC mixed signal.
First transistor and the first AC input Receiving a signal
Take the primary terminal and couple to the first transistor primary terminal
A second transformer having a secondary terminal and a tertiary terminal
First mixer means having a resistor, Coupled to the first mixer means, wherein the first and second
Receiving and mixing an AC input signal to form a second AC mixed signal
And DC biased in the second linear operating region.
Second mixer means, Coupled to the first and second mixer means, wherein the first
And receiving and combining the second AC mixed signal and the AC output
Combiner means for providing a signal; Wherein the AC output signal is the first and second A
A first plurality of even-numbered terms and a second plurality of mixed results of the C input signal
And the first plurality of even numbers
Each of the terms being adjacent to the second plurality of odd terms
A signal mixer characterized in that it is even larger. 20. The second mixer according to claim 19, wherein:
The means A primary terminal and a secondary terminal for receiving the first AC input signal
And a tertiary terminal for supplying the second AC mixed signal.
A third transistor, A primary terminal for receiving the second AC input signal;
A secondary terminal connected to the primary terminal of the transistor and a tertiary terminal
A fourth transistor having a transistor and A signal mixer comprising: 21. Receiving first and second AC input signals
And mixing, and the mixing result of the first and second input signals
Output with even and substantially suppressed odd terms
In a signal mixer that supplies a force signal, DC biased in the first linear operating region and the first A
A primary input circuit for receiving a C input signal, a first DC signal and
And a secondary input receiving at least a portion of the second AC input signal
Circuit and an output for providing a first AC mixed signal
First transistor circuit, DC biased in the second linear operating region and
A primary input circuit for receiving an AC input signal, and a second DC signal;
And receiving at least a portion of the first AC input signal.
A second input circuit and an output terminal for supplying a second AC mixed signal.
A second transistor circuit having the second transistor circuit.
The output terminal of the transistor circuit is connected to the output terminal of the first transistor circuit
A coupled second transistor circuit, Receiving the first and second AC mixed signals and providing an AC output
The first and second transistor times to supply a signal.
A resistance coupled to the road output end, Wherein the AC output signal is the first and second A
A first plurality of even terms and a second plurality of
It has several odd terms, and the first plurality of even terms
Each of which is one more than an adjacent one of the second plurality of odd terms
The layer size is large, The first and second transistor circuits are first and second, respectively.
Having a second bipolar junction transistor, each of which
These are associated with base-emitter junction forward vias.
A threshold voltage, and
The output signal is almost V ₀ ≒ -2IR · cosh [(V ₁ -V _Two ) / V _T ] Note that V ₀ = Voltage value of AC output signal I = current value of each of the first and second DC signals R = resistance value of resistor V ₁ = Voltage value of first AC input signal V _Two = Voltage value of the second AC input signal V _T = Base-emitter junction forward bias threshold
Hold voltage value  cosh [(V ₁ -V _Two ) / V _T ] = (V ₁ -V _Two ) / V _T Hyperbolic cosine of A signal mixer provided according to the formula: 22. Receiving first and second AC input signals
And mixing, and the mixing result of the first and second input signals
Output with even and substantially suppressed odd terms
In a signal mixing method for providing a force signal, First DC biased signal in first linear operating region
Inputting first and second AC input signals to the mixer; The second AC input signal to the secondary terminal of the first transistor
And inputs the first AC input signal to one of the second transistors.
Input to the next terminal, and from the secondary terminal of the second transistor
To the primary terminal of the first transistor.
From the tertiary terminal of the first transistor.
Outputting the first and second C-mix signals.
Mixing the AC input signal in the first signal mixer
1st AC Provide a mixed signal, Second signal DC biased in the second linear operating region
Inputting the first and second AC input signals to a mixer; The first and second AC inputs in the second signal mixer
Providing a second AC mixing signal by mixing the force signals; Combining the first and second AC mixed signals to produce an AC output signal
Supply the Each of the above steps, wherein the AC output signal is
A first plurality of evens of the result of mixing the first and second AC input signals;
A number term and a second plurality of odd terms, and
Each of the plurality of even-numbered terms is adjacent to the second plurality of odd-numbered terms.
Characterized by being much larger than those in contact
Signal mixing method. 23. mixing the first and second AC input signals;
And an even number term of the result of mixing the first and second input signals;
Providing an AC output signal having a substantially suppressed odd term
Signal mixing method, The first DC biased transistor in the first linear operating region
Input the first AC input signal to the primary input circuit of the transistor circuit
And A first DC signal to a secondary input circuit of the first transistor circuit;
And at least part of the second AC input signal, A first AC mixed signal from an output terminal of the first transistor circuit;
Output A second DC biased transformer in the second linear operating region.
The second AC input signal to the primary input circuit of the transistor circuit.
type in, A second DC signal to a secondary input circuit of the second transistor circuit;
And at least a part of the first AC input signal.
And A second AC mixed signal from an output terminal of the second transistor circuit;
Output Inputting the first and second AC mixed signals to a resistor; First plurality of mixing results of the first and second AC input signals
Output signal having an even term and a second plurality of odd terms
Is output from the resistor, Having the above steps, wherein the first plurality of even terms
Is greater than the adjacent one of the second plurality of odd terms.
The first and second transistor circuits are larger in size.
Paths are first and second bipolar junction transistors, respectively.
And that Each has a base emi associated with it
With forward bias threshold voltage
And outputting the AC output signal,
Almost, V ₀ ≒ -2IR · cosh [(V ₁ -V _Two ) / V _T ] Note that V ₀ = Voltage value of AC output signal I = current value of each of the first and second DC signals R = resistance value of resistor V ₁ = Voltage value of first AC input signal V _Two = Voltage value of the second AC input signal V _T = Base-emitter junction forward bias threshold
Hold voltage value cosh [(V ₁ -V _Two ) / V _T ] = (V ₁ -V _Two ) / V _T of
Hyperbolic cosine Outputting the AC output signal according to the following equation:
Signal mixing method. 24. Receiving first and second AC input signals
And mixing, and the mixing result of the first and second input signals
Output with even and substantially suppressed odd terms
In a signal mixing method for providing a force signal, First DC biased signal in first linear operating region
Inputting first and second AC input signals to the mixer; The second AC input signal to the secondary terminal of the first transistor
And inputs the first AC input signal to one of the second transistors.
Input to the next terminal, and from the secondary terminal of the second transistor
To the primary terminal of the first transistor.
And the third terminal of the first transistor
Outputting the first AC mixed signal
Mixing the first and second AC input signals in a mixer
Providing a first AC mixing signal; Second signal DC biased in the second linear operating region
Inputting the first and second AC input signals to a mixer; Applying the first AC input signal to the secondary terminal of the third transistor
And input the second AC to the primary terminal of the fourth transistor.
Input a force signal and from the secondary terminal of the fourth transistor
To the primary terminal of the third transistor.
And the third terminal of the third transistor is connected to the third terminal.
And outputting the second AC mixed signal.
Mixing the first and second AC input signals in a combiner
2nd AC Provide a mixed signal, Combining the first and second AC mixed signals to produce an AC output signal
Supply the Each of the above steps, wherein the AC output signal is
A first plurality of evens of the result of mixing the first and second AC input signals;
A number term and a second plurality of odd terms, and
Each of the plurality of even-numbered terms is adjacent to the second plurality of odd-numbered terms.
Characterized by being much larger than those in contact
Signal mixing method.