JP3297951B2 - VTR device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VTR suitable for application to, for example, an editing system.

[0002]

2. Description of the Related Art FIG. 7 shows an example of the configuration of an editing system using a digital VTR. In the figure, 1 is a digital VTR on the master side, 2 is a digital VTR on the slave side, and 3 is a monitor connected to the VTR 2 side.

[0003] Digital video data DVs are supplied from a VTR 1 to a VTR 2 in a serial interface format (see SMPTE259M). VT
When R2 is in the edit mode, for example, video data D
The servo operation is performed by obtaining a servo reference signal based on the synchronization signal detected from Vs.

[0004]

When the VTR 2 is in the edit mode and the video data DVs is not supplied from the VTR 1 to the VTR 2, the servo lock cannot be performed. Therefore, for example, in reproduction in the edit mode, the monitor 3
However, there is a problem that the reproduced image displayed on the display is disturbed.

In view of the above, the present invention provides a VTR device capable of performing servo lock even when there is no input video data.

[0006]

Means for Solving the Problems To solve the above problems,
For example, the VTR device according to the present invention has an external input or an internal output.
Playback or recording operation based on these synchronization signals.
A VTR device, based on a synchronization signal,
A servo reference signal forming means for forming a signal;
Internal synchronization signal generation means for generating a synchronization signal, and external input
Video data and a synchronization signal from the
Internal synchronization signal generation means based on whether or not video data is detected
From the internal output synchronization signal from the
Output one of the period signals to the servo reference signal forming means
Synchronous switching means, and the synchronous switching means includes
Before turning on the power of the TR
Internal output is selected for a certain period, and external output is used for other periods.
A switching control signal that selects the input is supplied and synchronized
The switching means detects video data from an external input.
The synchronization signal detected from the external input,
When no video data is detected from the
The feature is that the synchronization signal is selected.
is there. In the VTR device according to the present invention, the first synchronization
The conversion means is a serial-type first data supplied from the outside.
Digital video data or internally generated serial type
Switch off one of the second digital video data
Data switching means for selecting based on the switching control signal.
External or internal clock from the output data of
Clock detecting means for detecting the clock and data switching means.
Data detection to detect the presence or absence of video data from output data
Output means and an external or
One of the internal clocks is detected by the data detection means
Clock switching means for selecting based on the result;
Output data of the data switching means based on the output of the data switching means.
Synchronization detection means for detecting a synchronization signal from the data.
The first digital video data is detected by the data detecting means.
Output, select an external clock and
Means for detecting second digital video data
Clock switch to select the internal clock
Control means, and the data switching means is connected to the power supply of the VTR device.
A certain period of time before the
Switching system for selecting 2 digital video data
A control signal is supplied . Departure
In the VTR device according to the present invention, the second synchronization switching means is external.
Digital video data in serial format supplied from the
Data to the first digital video data in parallel format.
Serial / parallel conversion means for converting
The first digital video output from the parallel conversion means
Data or a second data in parallel format generated internally.
Control signal for switching one of digital video data
Data switching means for selecting based on the
External or digital data in serial format
Means clock detection means for detecting the internal clock, and external
From digital data in serial format supplied by
Data detection means for detecting the presence or absence of video data;
Of the external or internal clock detected by the clock detection means.
Either one is selected based on the detection result of the data detection
Clock switching means, and the output of the clock switching means.
Synchronization signal from output data of data switching means based on force
Synchronization detecting means for detecting the
External serial video data is detected
Time, select an external clock and use the data detection
External video data in serial format is not detected.
The clock, select the internal clock.
Switching means, and the data switching means is provided with the VTR device.
For a certain period of time before power-on to playback or recording,
Switching to select second digital video data
A control signal is supplied. Book
In the VTR apparatus according to the present invention, the first or second synchronization
The conversion means uses a clock even if there is no video data input.
Keeps outputting the sync signal periodically as long as
Characterized by having a flywheel function.
You.

[0007]

According to the VTR device of the present invention, the external input or
Is played or recorded based on the internal output and these sync signals.
When the recording operation is performed, the synchronization switching means includes the VTR device.
Period before the power is turned on to the playback or recording operation
During this period, select the internal output, and during other periods, select the external input.
A switching control signal is supplied to select
The signal generation means generates an internal synchronization signal. Synchronous switching
Means detects video data and synchronization signal from external input
And based on the detection of the video data.
Internal output synchronization signal from external synchronization signal generation means or external
One of the synchronization signals detected from the input is used as the servo reference
The signal is output to the signal forming means. Based on this
Then, the synchronization switching means detects video data from an external input.
When issued, selects the synchronization signal detected from the external input
When no video data is detected from the external input,
The synchronization signal of the internal output is selected. The servo
In the reference signal forming means, the synchronization signal thus selected is
A servo reference signal is formed based on the servo reference signal. For example, the first
FIG. 1 shows an example of the data switching means in the synchronous switching means.
Switch 14 provides an externally supplied switch.
First real digital video data (external input)
Force) or a second digit in serial form generated internally
One of the video data (internal output) is switched
The selection is made based on the control signal SCW. This switching control
The signal is read or recorded when the power of the VTR device is turned on.
Select the internal output for a certain period of time before
Is a signal for selecting an external input. Also,
Switching is performed in the PLL circuit 16 which is an example of the clock detecting means.
External or internal clock from the output data of switch 14.
Is detected. Further, a PL which also serves as a data detecting means
In the L circuit 16, the output data of the changeover switch 14
The presence or absence of video data is detected. One of clock switching means
In a changeover switch 17 as an example, a PLL circuit 16
Either the detected external or internal clock is applied.
The selection is made based on the detection result of the PLL circuit 16.
Done. In the synchronization detection circuit 20, the changeover switch 17
From the output data of the changeover switch 14 based on the output
Detect the synchronization signal. Then, the PLL circuit 16
When one digital video data is detected,
And the PLL circuit 16 selects the second clock.
When digital video data is detected, the internal clock
The changeover switch 17 is controlled so as to select a switch. This
Then, for example, an example of a servo reference signal forming unit
In the path of the synchronization signal supplied to the signal processing circuit 22
With the flywheel means 21 interposed, external synchronization
Even if there is no signal, the signal processing circuit 22
Means that the synchronization signal is continuously supplied. Therefore,
From the power-on of the VTR device to the playback or recording operation
For a certain period of time before the
A quasi-signal can be formed. After a certain period of time
When video data is detected, the
Form a servo reference signal based on the synchronization signal
Can be. Video data is also detected after a certain period of time.
If no signal is output, the signal is output based on the synchronization signal of the internal output.
Since the reference signal can be formed,
Servo lock is possible from the state where the
It is possible to obtain effects such as prevention of disturbance of reproduced images due to servo disturbance.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG.
An example will be described. This example Ri example Der applied to a digital VTR apparatus for recording and reproducing digital video data is obtained by using the first synchronous switching means.

In FIG. 1, reference numeral 11 denotes an input terminal to which serial digital video data DVsi in a serial interface format (see SMPTE259M) is externally supplied. The video data DVsi supplied to the input terminal 11 is supplied to a processing block 12. In the processing block 4, conversion to NRZ data, descrambling, and the like are performed, and 10-bit parallel data and a parallel clock are output.

That is, the video data DVsi is supplied to the fixed terminal on the a-side of the changeover switch 14 via the cable equalizer 13 for compensating for the transmission loss in the coaxial cable. The serial digital video data output from the changeover switch 14 is supplied to a serial / parallel conversion circuit (S / P conversion circuit) 15 and is 10-bit as 4: 2: 2 parallel video data (see CCIR601 and RP125). It is converted into parallel format digital video data DVp.

The serial digital video data output from the changeover switch 14 is supplied to a PLL circuit 16 as clock detecting means. The PLL circuit 16 detects the edge of the video data and performs the detection at 270 MHz.
z clock (not shown) is output and 27M
Hz parallel clock CKp is output. Also, P
The LL circuit 16 detects the presence or absence of digital video data in serial format, and outputs a data detection signal SD.

In the processing block 12, conversion to NRZ data, descrambling, and the like are also performed as described above, but are not shown for simplicity.

The parallel clock CKp output from the PLL circuit 16 of the processing block 12 is supplied to a fixed terminal on the a side of the changeover switch 17, and the parallel clock output from the changeover switch 17 is supplied to the processing block 18. The parallel digital video data DVp output from the S / P conversion circuit 15 of the processing block 12
Is supplied to the processing block 18 and processed using the parallel clock output from the changeover switch 17.

That is, the digital video data DVp in the parallel format is supplied to the data deleting circuit 19. FIG. 2 shows a data stream of the digital video data DVpi, and includes EAV (End of Active Video),
AV (Start of Active video) is a timing reference signal as is well known. The data deletion circuit 19 deletes data corresponding to digital line blanking from EAV to SAV. The output data of the data deletion circuit 19 is converted into 10-bit parallel data by the signal processing circuit 2.
2 is supplied.

The digital video data DVp in the parallel format is supplied to a synchronization detection circuit 20. In the synchronization detection circuit 20, the synchronization signals (F,
V, H) are extracted, and the flywheel circuit 21
Supplied to In the flywheel circuit 21, the synchronization signals (F, V, H) are processed and the frame synchronization signals CF are processed.
0, a vertical synchronizing signal VD, and a horizontal synchronizing signal HD (shown in FIGS. 3A to 3C), and these synchronizing signals CF0, VD,
HD is supplied to the signal processing circuit 22.

Here, the flywheel circuit 21 has a flywheel function. The flywheel function utilizes the property that the input synchronization signal is periodic. When the input signal is continuous, the synchronization signal is continuously output from a circuit composed of a counter, and if the input signal is temporarily Even if the signal disappears, the synchronization signal is continuously output as long as the clock is supplied (see Japanese Patent Application No. 4-119170).

In the signal processing circuit 22, the synchronization signals CF0, V
D and HD are processed to form a servo reference signal SSCF (shown in FIG. 3D), and this servo reference signal SSCF is supplied to the servo circuit 23. In the servo circuit 23, drum, reel servo, and the like are performed according to the servo reference signal SSCF. FIG. 3D shows an example of a four-field sequence of the 525 system, which is different in the case of an eight-field sequence of the 625 system.

In the signal processing circuit 22, the 10-bit parallel video data supplied from the processing block 18 is signal-processed to form recording data DREC. More specifically, encoding operations such as shuffling, bit reduction, error correction, and channel coding are performed. The recording data DREC formed by the signal processing circuit 22 is supplied to a rotating magnetic head 24 and recorded on a magnetic tape (not shown). In addition, 25 is a rotating drum and 26 is a drum motor.

Further, the rotating magnetic head 24 is made of a magnetic tape.
The reproduction data DPLY reproduced in step (1) is subjected to each decoding operation in the signal processing circuit 22 and supplied to the data insertion circuit 27 as 10-bit parallel data. The signal processing circuit 22 includes a timing generator as described above, and the frame synchronization signal CF0 and the horizontal synchronization signal HD output from the timing generator are supplied to the data insertion circuit 27.

In the data insertion circuit 27, digital line blanking data of EAV to SAV is inserted into the 10-bit parallel data, and parallel digital video data DVpo of 4: 2: 2 parallel video data (see CCIR601 and RP125) is obtained. It is formed. The digital video data DVpo in the parallel format is supplied to a parallel / serial conversion circuit (P / S conversion circuit) 28.

The P / S conversion circuit 28 converts the digital video data DVso into serial digital data according to a serial interface format (see SMPTE259M). Although not described above, the parallel clock CKpo output from the timing generator of the signal processing circuit 22 is
The data is supplied to the data insertion circuit 27 and the P / S conversion circuit 28.

The digital video data DVso in serial format output from the P / S conversion circuit 28 is led to an output terminal 30 via a driver 29 of a coaxial cable.

The digital video data DVso in serial format output from the P / S conversion circuit 28 is supplied to a fixed terminal on the b side of the changeover switch 14. The changeover switch 14 is supplied with a changeover control signal SCW from a system control microcomputer (not shown) via a terminal 31. The changeover switch 14 is connected to the b side for a certain period after the power is turned on, and is connected to the a side during other periods. You. Synchronized with DVso
Switch 14 to a state where external input can be detected from the state
Is forcibly switched.

The parallel clock CKpo output from the timing generator of the signal processing circuit 22 is supplied to a fixed terminal on the b side of the changeover switch 17. This is the change-over switch 17 is supplied as a data detection signal SD switching control signal outputted from the PLL circuit 16 of the processing block 12, when the video data is detected by the PLL circuit 16 is Ru is connected to the a side. Clock detected from external input
CKpo (synchronous signal) is selected and the clock signal C
To form a servo reference signal based on Kpo.
You. If no video data is detected, the connection is made to the b side. Reproduction or recording operation from power-on of the VTR device
Not only for a certain period of time before
Servo based on clock signal (internal synchronization signal) CKpo
This is so that a reference signal can be formed.

This embodiment is configured as described above, and the operation will be described below.

First, a case where serial digital video data DVsi is supplied to the input terminal 11 will be described with reference to the timing chart of FIG.

When the power switch is turned on at time t1, the video data DVsi is supplied to the PLL circuit 16 and video data is detected. At time t6 immediately after time t1, the changeover switch 17 moves to the a side. Connected. Therefore, the video data DV output from the PLL circuit 16
The parallel clock CKp synchronized with si is the switch 1
7 and supplied to the processing block 18, and the processing block 18 is supplied with the video data DVp obtained by subjecting the video data DVsi to S / P conversion, and is extracted from the video data DVp by the synchronization detection circuit 20. EA
The synchronizing signals CF0, VD, HD are output from the flywheel circuit 21 based on V, SAV (F, V, H).
That is, the flywheel circuit 21 outputs synchronization signals CF0, VD, and HD synchronized with the video data DVsi.

Further, from time t2 after power-on to time t3
During a certain period of time, the changeover switch 14 is connected to the b side by the changeover control signal SCW from the system control microcomputer. The PLL circuit 16 has video data DVso
Is supplied, the video data is continuously detected, and the changeover switch 17 remains connected to the a side. Therefore, the video data DVso output from the PLL circuit 16
Clock CKp synchronized with the switch 17
, And the processing block 18 is supplied with video data DVp obtained by subjecting the video data DVso to S / P conversion. The EAV extracted by the synchronization detection circuit 20 from the video data DVp is supplied to the processing block 18. ,
Flywheel circuit 2 based on SAV (F, V, H)
1 outputs synchronization signals CF0, VD and HD. That is, the flywheel circuit 21 outputs the video data DV.
Synchronization signals CF0, VD, HD synchronized with so are output.

After the lapse of time t3, the changeover switch 1
4 is connected to the a side. Since the video data DVsi is again supplied to the PLL circuit 16, the video data is continuously detected, and the changeover switch 17 remains connected to the a side. Therefore, the parallel clock CKp synchronized with the video data DVsi output from the PLL circuit 16 is supplied to the processing block 18 via the changeover switch 17, and the processing block 18 performs S / P conversion of the video data DVsi. Video data DVp
Is supplied to the flywheel circuit 21 in the same manner as described above.
From the synchronization signal CF0, which is synchronized with the video data DVsi.
VD and HD are output.

When the serial digital video data DVsi is supplied to the input terminal 11 in this way, the synchronization signals CF0, VD, HD synchronized with the video data DVsi from the flywheel circuit 21 after the time t3 have elapsed.
Is continuously output, the servo is locked to the synchronous system of the video data DVsi.

Next, a case where serial digital video data DVsi is not supplied to the input terminal 11 will be described with reference to the timing chart of FIG.

When the power switch is turned on at time t1,
Since no video data DVsi is supplied to the PLL circuit 16, no video data is detected, and the changeover switch 17 remains connected to the b side. Therefore, the parallel clock CKpo is supplied to the processing block 18 via the changeover switch 17, but the processing block 18 is not supplied with the video data DVp and the flywheel circuit 2
The synchronization signals CF0, VD, HD output from 1 are in an undefined state.

Also, from time t2 after power-on to time t3
During a certain period of time, the changeover switch 14 is connected to the b side by the changeover control signal SCW from the system control microcomputer. The PLL circuit 16 has video data DVso
Is supplied, video data is detected, and at time t4 immediately after time t2, the changeover switch 17 is connected to the a side. Therefore, a parallel clock CKp synchronized with the video data DVso output from the PLL circuit 16 is supplied to the processing block 18 via the changeover switch 17, and the video data DVso is sent to the processing block 18 by the S.
/ P-converted video data DVp is supplied, and the flywheel circuit 21 generates the synchronization signals CF0, VD, and CV based on the EAV and SAV (F, V, H) extracted by the synchronization detection circuit 20 from the video data DVp. HD is output. That is, the flywheel circuit 21 outputs synchronization signals CF0, VD, and HD synchronized with the video data DVso.

After the elapse of the time point t3, the changeover switch 1
4 is connected to the a side. Since the video data DVsi is not supplied to the PLL circuit 16, no video data is detected, and the switch 17 is connected to the b side at time t5 immediately after time t3.

From the time point t3 to the time point t5, no video data DVp is supplied to the processing block 18,
Since the free-run parallel clock CKp output from the PLL circuit 16 is supplied to the processing block 18 via the changeover switch 17, the flywheel circuit 21 outputs the synchronization signals CF0, CF0, synchronized with the video data DVso by the clock CKp. VD and HD continue to be output.

Further, after the time point t5, the parallel clock CKpo is supplied to the processing block 18 via the changeover switch 17, so that the flywheel circuit 21 outputs the synchronization signals CF0, CF0, synchronized with the video data DVso by the clock CKpo. VD and HD continue to be output.

As described above, when the digital video data DVsi in the serial format is not supplied to the input terminal 11, after the elapse of the time t3, the flywheel circuit 21 synchronizes with the video data DVso by the free-run clock CKp or the clock CKpo. Synchronization signal CF0, V
Since D and HD are continuously output, the servo is locked to the synchronous system of the video data DVso.

As described above, in this embodiment, the input terminal 11
Even if video data DVsi is not supplied to the servo, the synchronizing signals CF0, VD, HD synchronized with the video data DVso continue to be output from the flyhole circuit 21, so that the servo is locked to the synchronization system of the video data DVso. In addition, the reproduced image is not disturbed by the servo disturbance.

Next, a second embodiment of the present invention will be described with reference to FIG. In the example of FIG. 1, the so-called board-through switching is performed in a serial mode by the changeover switch 14 of the processing block 12, but in this example , the board-through switching is performed in the parallel mode using the second synchronous switching means . This is done in a state. 6, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this example, the S / P of the processing block 12
The output signal of the cable equalizer 13 is supplied to the conversion circuit 15 and the PLL circuit 16. The parallel digital video data DVp output from the S / P conversion circuit 15 is supplied to a fixed terminal on the a side of the changeover switch 32, and the data insertion circuit 27 supplies a fixed terminal on the b side of the changeover switch 32. The output parallel digital video data DVpo is supplied.

A switching control signal SCW is supplied from a terminal 31 to the changeover switch 32, and is connected to the b side for a certain period after the power is turned on (see the period between t2 and t3 in FIGS. 4 and 5).
In other periods, it is connected to the a side. This changeover switch 3
2 is supplied to the processing block 18 in parallel format.

This embodiment is constructed as described above, and the detailed description of the operation is omitted.
Is not supplied, the synchronization signal CF synchronized with the video data DVpo from the fly-hole circuit 21 is output.
0, VD, and HD continue to be output. Therefore, the servo is locked to the synchronous system of the video data DVpo, and the servo image does not cause a disturbance in the reproduced image.

In the above embodiment, the changeover switch 17 switches between the parallel clock CKp output from the PLL circuit 16 and the parallel clock CKpo output from the timing generator of the signal processing circuit 22. This is because the PLL error when no signal is input is large. Suppose that V constituting the PLL circuit 16 is
If the free-run frequency of the CO (voltage controlled oscillator) is crystal-accurate, only the parallel clock CKp output from the PLL circuit 16 can be used, and the switch 17 can be omitted.

In the above-described embodiment, the changeover switches 14 and 32 are connected to the b-side for a certain period immediately after the power is turned on. What is necessary is just to control the changeover switches 14 and 32 to be connected to the b side.

[0045]

According to the VTR device of the present invention ,
Playback based on internal input or internal output and their synchronization signals
Or, when performing a recording operation,
And the synchronization signal and the video data.
From the synchronization signal of the internal output or the external input
Generates a servo reference signal for one of the detected synchronization signals
Synchronization switching means for outputting to the means,
The playback or recording operation from the power-on of the VTR device
Select the internal output for a certain period of time before
During this period, a switching control signal for selecting an external input is supplied.
The synchronous switching means supplies video data from an external input.
When the synchronization signal is detected, the synchronization signal detected from the external input
If no video data is detected from the external input
In this case, the synchronization signal of the internal output is selected. this
Depending on the configuration, playback or playback from the power on of the VTR device
Is based on the internal synchronization signal for a certain period before the recording operation.
Accordingly, a servo reference signal can be formed. One period
After a lapse of time and video data is detected,
Servo reference signal based on synchronization signal detected from external input
No. can be formed. Also, after a certain period of time,
If no video data is detected, the
The servo reference signal can be formed based on the
Servo lock is enabled from a state in which the power of the VTR device is turned on, and effects such as prevention of disturbance of reproduced images due to servo disturbance can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a VTR apparatus according to the present invention.

FIG. 2 is a diagram illustrating a data stream of digital video data in a parallel format.

FIG. 3 is a diagram showing a synchronization signal and a servo reference signal.

FIG. 4 is a timing chart for explaining an operation when digital video data DVsi is supplied.

FIG. 5 is a timing chart for explaining an operation when digital video data DVsi is not supplied.

FIG. 6 is a configuration diagram showing a second embodiment of the VTR apparatus according to the present invention.

FIG. 7 is a diagram illustrating a configuration example of an editing system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Input terminal 12, 18 Processing block 14, 17, 32 Changeover switch 15 Serial / parallel conversion circuit (S / P conversion circuit) 16 PLL circuit 19 Data deletion circuit 20 Synchronization detection circuit 21 Flywheel circuit 22 Signal processing circuit 23 Servo circuit 27 data insertion circuit 28 parallel / serial conversion circuit (P / S conversion circuit) 30 output terminal

Continuation of the front page (51) Int.Cl. ⁷ identification code FI H04N 5/95 D (58) Investigation field (Int.Cl. ⁷ , DB name) G11B 15/467 H04N 5/7826 H04N 5/91 H04N 5 / 95

Claims (4)

(57) [Claims] An external input or an internal output and their synchronous signals
Device that performs playback or recording operation based on the
Thus, a server for forming a servo reference signal based on the synchronization signal
Reference signal forming means, and an internal synchronization signal generating means for generating the internal output synchronization signal.
And when detecting video data and sync signals from external inputs
The internal synchronization based on whether or not the video data is detected.
Synchronization signal of internal output from signal generation means or external input
One of the synchronization signals detected from the servo reference signal
Synchronization switching means for outputting to the signal forming means, wherein the synchronization switching means includes
For a certain period before the playback or recording operation, the internal output
Select the external input during the rest of the time
Switching control signal is supplied, and the synchronous switching means detects video data from an external input.
Is selected, select the synchronization signal detected from the external input.
And, when from the external input is not detected video data,
It is characterized in that the internal output synchronization signal is selected.
VTR device to be used . 2. The synchronization switching means according to claim 1, wherein said synchronization switching means comprises a serial first digital video signal supplied from outside.
Video data or a second internally generated serial format
One of the digital video data is controlled by the switching control.
Data switching means for selecting based on a control signal, and an external or internal clock based on output data of the data switching means.
Clock detection means for detecting lock; and presence or absence of video data from output data of the data switching means.
Data detection means for detecting absence, and external or internal data detected by the clock detection means.
One of the clocks is detected by the data detecting means.
Clock switching means for selecting the data based on the result of the switching, and data switching based on the output of the clock switching means.
Detection means for detecting a synchronization signal from output data of the means
A first digital video data by the data detecting means.
When an external clock is detected, select the external clock,
The second digital video data is output by the data detecting means.
When the data is detected, select the internal clock
The clock switching means is controlled as described above, and the data switching means is connected to the VTR device from power-on to reproduction or recording operation.
The second digital video data for a certain period before
2. The VTR device according to claim 1, wherein a switching control signal for selection is supplied . 3. The synchronous switching means includes a serial digital video data supplied from an external device.
Data to the first digital video data in parallel format
A serial / parallel converter for converting, and a first output from the serial / parallel converter.
Digital video data or internally generated parallel
Format of the second digital video data
Data switching means for selecting based on the switching control signal
And a serial digital video supplied from the outside.
Clock that detects an external or internal clock from
Means for detecting digital data in serial format supplied from the outside.
Data detection means for detecting the presence or absence of video data from the data
When, by external or internal detected by said clock detecting means
One of the clocks is detected by the data detecting means.
Clock switching means for selecting the data based on the result of the switching, and data switching based on the output of the clock switching means.
Detection means for detecting a synchronization signal from output data of the means
And a serial format video from the outside by the data detecting means.
When video data is detected, the external clock is
Select and external serial connection by the data detection means.
When no video data of the format is detected,
Controlling the clock switching means to select a clock
However , the data switching means may switch from turning on the power of the VTR device to reproducing or recording operation.
The second digital video data for a certain period before
2. The VTR device according to claim 1, wherein a switching control signal for selection is supplied . 4. The synchronization detecting means according to claim 2, wherein said synchronization detecting means has a flywheel function of continuously outputting a synchronization signal as long as a clock is supplied even when video data is no longer input. The VTR device as described.