JP3296293B2 - Integrated circuit failure analysis apparatus and failure analysis method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a failure analysis device and a failure analysis method for an integrated circuit, and more particularly to a failure analysis device and a failure analysis method for a memory LSI.

[0002]

2. Description of the Related Art Conventional LSI failure analyzers include, for example, KLA-Tencor of the United States and Inspex.
The products manufactured by the company are famous, but these devices can analyze the case where the number of defects per wafer is about tens of thousands.

As a memory LSI failure analysis apparatus for the purpose of elucidating the cause of failure and improving the yield, Japanese Patent Application Laid-Open No. H08-205702 discloses a memory LSI failure analysis apparatus.
There is an apparatus described in Japanese Patent Application Laid-Open No. 7-072206, which is an expert system in which the know-how of a process engineer, a circuit engineer, and a layout engineer is mounted on a personal computer.

[0004]

However, the conventional failure analyzer has mainly two problems. One problem is that the upper limit of the number of defects that can be analyzed is low, in other words, the number of defects that can be analyzed per day is small because the analysis process takes a long time.

The capacity of a dynamic random access memory (hereinafter referred to as DRAM) assumed in a conventional failure analyzer is 16 megabits or 64 megabits, and the number of DRAM chips manufactured on one wafer is about several hundreds. And the diameter of the wafer is 200 mm.

If the defective density is 10 p. p. m. That is, even if 10 out of 1 million elements are defective, the number of defectives exceeds 100,000 per wafer, and sufficient analysis cannot be performed with the conventional apparatus.

In recent years, the speed of increasing the capacity and density of memories has been increasing more and more.
It is necessary to cope with failure analysis of a DRAM of 56 megabits or more.

In addition, it is certain that the wafer size will be increased to a diameter of 300 mm. In this case, the number of defects to be analyzed increases synergistically.

Assuming that the capacity is quadrupled and the number of chips is increased by a factor of 2.5 by increasing the wafer size, the number of defects is increased by a factor of ten. In this case, the number of wafers that can be analyzed is reduced to 1/10 or less of the conventional one, and the production yield is reduced due to delay in finding the cause of the defect.

The second is an operational problem. For example, operating a distributed memory LSI failure analyzer at night,
In the morning, if an analysis engineer attempts to output the analysis results before going to work, even after the equipment operator starts operation at midnight, one of the analysis computers may be operated for some reason. In order to deal with troubles such as stopping and disturbing distributed processing, or troubles such that analysis processing does not end in the morning when analysis technicians arrive at work, equipment operation status must be monitored all night. Must.

Particularly, in the case of an apparatus using distributed processing, the possibility of occurrence of a trouble increases as the number of machines increases, and as a result, the labor for monitoring increases.

On the other hand, Japanese Patent Laid-Open Publication No. 3-28267 discloses an example of an automatic data collection and distribution system.

However, it cannot be conceived from this publication how to apply this to the memory failure analysis processing, particularly how to handle the data after the distributed processing.

It is an object of the present invention to provide an integrated circuit failure analysis apparatus and a failure analysis method that can reduce the time required for analysis processing and can perform automatic operation at night.

[0015]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a test means for testing an integrated circuit, and a chip unit which disperses the result data tested by the test means into a plurality of pieces.
A dispersion analysis means for performing failure analysis of position, characterized in that it comprises a integrated analysis means for performing failure analysis of the wafer units integrating the results of the analysis in this dispersion analyzer.

According to another aspect of the present invention, there is provided a first process for testing an integrated circuit, and a second process for distributing the result data tested in the first process to a plurality of units and performing a failure analysis on a chip basis . Process and the results analyzed in this second process
And a third process of performing a failure analysis on a wafer-by-wafer basis .

According to the present invention and other aspects of the present invention, failure data is analyzed by distributing the test result data into a plurality of pieces, and the analyzed results are integrated to further analyze the failure.

[0018]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a configuration diagram of a first embodiment of an integrated circuit failure analysis device according to the present invention.

The integrated circuit failure analyzer includes a memory test system 11, a data collection / distribution machine 12, and n (n
Is a positive integer equal to or greater than 2) distributed analysis machine groups 13 and an integrated analysis machine 14, each of which is mutually connected to a network.

FIG. 2 is a configuration diagram of the memory test system 11. The memory test system 11 has a storage device 41.

FIG. 3 is a configuration diagram of the data collection / distribution machine 12. The data collection / distribution / distribution machine 12 includes a storage device 52
, A transmission variable 53, an operation variable 54, and a clock 55.

FIG. 4 is an explanatory diagram showing the contents of the transmission variable 53 and the operation variable 54. Transmission variables 53 include WAIT (standby), START (start), ON (transmitted),
The operation variable 54 includes OFF (not transmitted) and END (end), and the operation variable 54 includes OFF (data waiting state) and ON (data analysis is being performed).

Next, the operation of each section will be described. First, the operation of the memory test system 11 will be described. FIG.
5 is a flowchart showing the operation of the memory test system 11.

In the memory test system 11, first, a memory LSI to be analyzed is selected (S1).

Next, an electrical test is performed on the memory LSI to be analyzed (S2), and the result is output to its own storage device 41 as bitmap data (S2).
3).

Next, it is checked whether or not the tests on all the memory LSIs have been completed (S4). If the tests have not been completed, the process returns to step S1 and the same processes are repeated.

On the other hand, when the tests of all the memory LSIs are completed in the process S4, the process is completed.

Next, the operation of the data collection / distribution machine 12 will be described. FIG. 6 shows a data collection / distribution machine 12
9 is a flowchart showing the operation of the collection and delivery processing.

In the data collection / distribution machine 12,
Two types of processing are performed: collection and distribution of bitmap data output from the memory test system 11, and distribution of the collected and distributed data to the dispersion analysis machine 13. These two types of processing are performed independently.

The data collection and delivery processing is executed according to the following processing procedure. First, the user creates a list of bitmap data to be collected and distributed (S11), and stores the list in the storage device 52 of the data collection and distribution machine 12.

Next, data is selected from the data list stored in the storage device 52 (S12), and the data is compared with data in the storage device 41 of the memory test system (S13). It is checked whether or not it has been acquired (S13).

If it has been acquired, it is checked whether or not all the data on the list has been acquired (S15). If not, the process returns to step S12 to repeat the same operation.

On the other hand, if the data has not been acquired yet in step S13, the data is acquired from the memory test system 11 by the file transfer protocol (S1).
4) Return to the processing S12.

When all data on the list has been acquired in step S15, the collection and delivery processing ends.

Next, the operation of the distribution processing of the data collection / distribution machine 12 will be described. FIG. 7 is a flowchart showing the operation of the distribution process of the data collection / distribution machine 12.

The distribution processing of the data collected and distributed from the memory test system 11 to the distribution analysis machine 13 is performed by searching for a distribution analysis machine 13 in a data waiting state in which the analysis processing is not performed, and transmitting the data to the distribution analysis machine 13. Perform in.

In order to grasp the state of the dispersion analysis machine 13, an operation variable 54 and a transmission variable 53 are set for each dispersion analysis machine, and the values of these variables are referred to and updated. It is determined whether or not is analyzing or has ended the analysis and is waiting for the next data.

As described above, the transmission variables 53 and the operation variables 54 of each dispersion analysis machine 13 are all on the data collection / distribution / distribution machine 12, and the dispersion analysis machine 13 refers to and updates these via a network. .

The data distribution process is executed in the following procedure.

First, the operation variable of each dispersion analysis machine 13 is set to ON (during data analysis) (S21).

Next, the distribution analysis machine 13 at the data transmission destination
And a directory of the integrated analysis machine 14 to which the analysis result is to be transmitted (flow is omitted).

Next, with reference to the list of bitmap data and the operating variables 54 of each dispersion analysis machine 13, for the machines whose operating variables are ON, the transmission variables 53 are set.
To OFF (not transmitted) (S22).

Next, it is checked whether or not there is a dispersion analysis machine 13 in which the operation variable 54 is OFF (data waiting state) (S23), and whether all the operation variables 54 are ON or the undistributed data is If not, enter "monitoring mode". That is, the process returns from step S23 to S22.

During the monitoring mode, the operating variable 54 is checked at any time to search for a machine that is OFF.

Next, at step S23, the operation variable 54 is set to OF.
If there is a distribution analysis machine 13 in F (data waiting state), it is next checked whether there is undistributed data (S2).
4) If there is undistributed data, it enters the "transmission mode" and transmits data to the machine 13 waiting for the data (S26).

Next, after the transmission, the transmission variable 53 of the machine 13 is turned ON (transmitted). And processing S22
And the same operation is repeated.

On the other hand, when there is no undistributed data in the process S24, the operation variables of all the distributed analysis machines 13 become OF
It is checked whether or not it has become F (S25), and all are OFF.
If not, the process returns to step S22, and the same operation is repeated.

Then, if the operating variables of all the distributed analysis machines 13 are turned off in the processing S25, the distribution processing ends.

Next, the operation of the dispersion analysis machine 13 will be described. FIG. 8 is a flowchart showing the operation of the dispersion analysis machine 13.

In the dispersion analysis machine 13, failure analysis at the chip level of the data transmitted from the data collection / distribution / distribution machine 12 is performed, and the result is analyzed by the integrated analysis machine 14.
Send to

The flow of these processes is as follows.
First, the own operation variable 54 stored in the data collection / distribution machine 12 is rewritten to OFF (data waiting state) (S31).

Next, reference is made to the own transmission variable 53 stored in the data collection / distribution machine 12 (S32).

Then, the transmission variable 53 is ON (transmitted)
If (S33), the operation variable 54 is rewritten to ON (during data analysis) (S34), and the analysis process is started (S33).
35).

When the analysis is completed, the analysis result is transmitted to the integrated analysis machine 14 (S36), and the operation variable is rewritten to OFF (S31).

On the other hand, if the transmission variable is not ON in step S33, it is checked whether the transmission variable is END (S3).
7).

If the transmission variable is OFF in step S33, the process returns to step S32 because the transmission variable is not END (end) in step 37, and the same operation is repeated.

At step S33, the transmission variable is set to END (end).
If, the transmission variable is END (end) in process 37, and the analysis process ends.

Next, the operation of the integrated analysis machine 14 will be described. The integrated analysis machine 14 collects the results of the analysis performed by the dispersion analysis machine group 13, integrates all chip failure data, and then performs failure analysis at the wafer level.

Next, a second embodiment of the present invention will be described. FIG. 9 is a configuration diagram of the second embodiment.

The second embodiment has, in addition to the first embodiment, a schedule management unit 21 for automatically operating the apparatus. The other configuration is the same as that of the first embodiment (FIG. 1), and thus the same reference numerals are given and the description is omitted.

Next, the operation of the schedule management section 21 will be described. FIG. 10 is a flowchart showing the operation of the schedule management unit 21.

In the schedule management section 21, first, the start time and the end time of the analysis processing are set (S4).
1).

Further, the transmission variable is set to WAIT (standby) (S42), and the operation variable 54 is initialized to ON (during data analysis) (S43).

In the data collection / distribution machine 12,
It monitors its own internal clock 55 until the start time set above reaches (S44).

Next, it is checked whether or not the start time has come (S45). If not, the built-in clock 55 is checked until it does (S44).

Then, when the start time comes in the process S45, the transmission variable is set to START (start) (S4).
6) If the end time does not come next (S47), a data distribution process is executed (S48).

If the end time is reached in step S47, all transmission variables 53 are set to END (end) (S4).
9), the process ends.

Each dispersion analysis machine 13 monitors its own transmission variable 53 stored in the data collection / distribution machine 12, and turns off its own operation variable when it becomes START.

After that, the transmission variable 53 is monitored, and when the transmission variable 53 is turned on, the own operation variable 54 is turned on, and then the data analysis process is started.

The subsequent processing is the same as that of the dispersion analysis machine 13 described in the first embodiment. Further, the transmission variable 53 is monitored as needed even after the processing is started, and if this is set to END (end), the processing is immediately ended.

Next, a third embodiment of the present invention will be described. FIG. 11 is a configuration diagram of the third embodiment.

The third embodiment has, in addition to the distributed memory LSI failure analyzer described in the first or second embodiment, a hang-up judging unit 31 for automatically operating the device. ing. Other configurations are the same as those of the first and second embodiments (FIGS. 1 and 9), and thus the same reference numerals are given and the description is omitted.

FIG. 12 is a block diagram of the hang-up judging section 31. The hang-up determination unit 31 has a counter 61.

Next, the operation of the third embodiment will be described. FIG. 13 is a flowchart showing the operation of the third embodiment.

The hang-up judging unit 31 monitors the state of each dispersion analysis machine 13 and regards the dispersion analysis machine 13 as having hung up when it has been in the “analyzing” state for a certain period of time or longer.

The subsequent data transmission to the hung-up distribution analysis machine 13 is stopped so that the distribution processing is not performed.

The determination of the hang-up is performed as follows using the operating variable 54.

The hang-up judging section 31 first sets a judgment threshold (S51). Next, the counter 61 prepared for each dispersion analysis machine 13 is initialized (S52).

Next, the distribution analysis machine 13 to be determined is selected (S53). Then, the operation variable 54 of the dispersion analysis machine 13 is checked (S54).

Next, it is checked whether or not the operation variable 54 is ON (S55). If it is not ON, the counter of the dispersion analysis machine 13 is cleared to 0 (S56). Then, the process returns to step S53, and the same operation is repeated.

On the other hand, the operation variable 54 is turned on in the processing S55.
, The counter of the distributed analysis machine 13 is set to 1
The number is increased (S57).

Next, it is checked whether or not the counter value has exceeded the threshold value (S58). If not, the process returns to step S53 and the same operation is repeated.

On the other hand, if the counter value exceeds the threshold value in step S58, it is determined that the variance analysis machine 13 has hung up (S59), and the variance analysis machine 1
3 is excluded from the dispersion analysis machine group 13 (S60).

The result of this determination (S60) is transmitted to the data distribution / collection machine 12. The data distribution / collection machine 12 does not transmit data to the distribution analysis machine 13 determined to have hung up.

[0085]

According to the present invention, a test means for testing an integrated circuit, a dispersion analysis means for distributing the result data tested by the test means to a plurality of pieces and performing a failure analysis, and an analysis means for the dispersion analysis means Since the integrated circuit failure analysis device is configured to include the integrated analysis means for integrating the results and performing failure analysis, the time required for the analysis processing can be reduced.

Further, the provision of the time setting means and the judgment means enables automatic operation at night.

According to another aspect of the present invention, there is provided a first process for testing an integrated circuit, a second process for distributing the result data tested in the first process to a plurality of components and performing a failure analysis, Since the failure analysis method includes a third process of integrating the results analyzed in the second process and performing a failure analysis,
The time required for the analysis processing can be reduced.

Further, by having the twelfth processing and the thirteenth processing, automatic driving at night becomes possible.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of an integrated circuit failure analysis device according to the present invention.

FIG. 2 is a configuration diagram of a memory test system 11.

FIG. 3 is a configuration diagram of a data collection / distribution / distribution machine 12.

FIG. 4 is an explanatory diagram showing contents of a transmission variable 53 and an operation variable 54;

FIG. 5 is a flowchart showing an operation of the memory test system 11;

FIG. 6 is a flowchart illustrating an operation of a collection and distribution process of the data collection and distribution machine 12.

FIG. 7 is a flowchart illustrating an operation of a distribution process of the data collection / distribution machine 12.

FIG. 8 is a flowchart showing the operation of the dispersion analysis machine 13.

FIG. 9 is a configuration diagram of a second embodiment.

FIG. 10 is a flowchart showing the operation of the schedule management unit 21.

FIG. 11 is a configuration diagram of a third embodiment.

FIG. 12 is a configuration diagram of a hang-up determination unit 31.

FIG. 13 is a flowchart showing the operation of the third embodiment.

[Explanation of symbols]

 11 Memory Test System 12 Data Collection / Distribution Machine 13 Distributed Analysis Machine Group 14 Integrated Analysis Machine 21 Schedule Management Unit 31 Hang-Up Judgment Unit 53 Transmission Variable 54 Operation Variable 61 Counter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 29/00 G01R 31/28 H01L 21/66

Claims (14)

(57) [Claims] 1. A test means for testing an integrated circuit, and a chip which disperses the result data tested by the test means into a plurality of pieces.
An integrated circuit failure analysis apparatus, comprising: a dispersion analysis unit that performs a failure analysis on a unit basis; and an integrated analysis unit that integrates results analyzed by the dispersion analysis unit and performs a failure analysis on a wafer basis . 2. The variance analysis means is a data collection / distribution means for collecting / distributing data to be collected / distributed from the test means, a data distribution means for distributing data from the data collection / distribution means to a plurality of data, and the distribution means. 2. The integrated circuit failure analysis device according to claim 1, further comprising a plurality of analysis means for performing failure analysis on each of the data. 3. The data collection / distribution means includes a data list storage means in which a list of data to be collected is stored, and result data for acquiring the result data from the test means in accordance with the data list stored in the data list storage means. 3. The integrated circuit failure analysis device according to claim 2, further comprising an acquisition unit. 4. The data distribution means monitors a status of operation of each of the plurality of analysis means, and a selection means for selecting the analysis means to which the data is to be distributed according to a monitoring result of the status monitoring means. The integrated circuit failure analysis device according to claim 2, further comprising: 5. The analysis means has a transmission monitoring means for monitoring whether or not data has been transmitted from the data distribution means. After the transmission monitoring means has confirmed that the data has been transmitted, a fault is detected. The integrated circuit failure analysis device according to claim 2, wherein analysis is performed. 6. A variance analysis means further comprising a time setting means for setting a start time and an end time of the analysis by the variance analysis means, wherein the variance analysis means performs the analysis according to the start and end times set by the time setting means. Claim 1 characterized by the above-mentioned.
5. The integrated circuit failure analysis device according to any one of 5. 7. The variance analysis unit further includes a determination unit that determines whether each analysis unit hangs up, and the variance analysis unit includes an analysis unit that is determined to hang by the determination unit. 7. The integrated circuit failure analysis apparatus according to claim 1, wherein the analysis is continued without being performed. 8. A first process for testing an integrated circuit, and distributing the result data tested in the first process to a plurality of chips.
An integrated circuit failure analysis method, comprising: a second process for performing a failure analysis on a unit basis; and a third process for integrating a result analyzed in the second process and performing a failure analysis on a wafer basis . 9. The second processing includes a fourth processing for collecting and delivering the data tested in the first processing, a fifth processing for distributing the data collected and distributed in the fourth processing to a plurality of processings, and a fifth processing. 9. The integrated circuit failure analysis method according to claim 8, further comprising: a sixth processing for performing failure analysis on each of the data distributed in the processing. 10. The fourth process is a seventh process for storing a list of data to be collected, and an eighth process for obtaining data tested in the first process according to the data list stored in the seventh process. The integrated circuit failure analysis method according to claim 9, further comprising : 11. The fifth processing includes a ninth processing for monitoring an operation state of each of the plurality of analyzes, and a tenth processing for selecting an analysis to which the data is to be distributed according to a monitoring result in the ninth processing. The method according to claim 9 or 10, wherein 12. The sixth processing includes an eleventh processing for monitoring whether data has been transmitted in the fifth processing, and it has been confirmed in the eleventh processing that the data has been transmitted. The failure analysis is performed later.
An integrated circuit failure analysis method according to any one of the above. 13. A twelfth process for setting a start and end time of the analysis in the second process, wherein the analysis is performed in accordance with the start and end times set in the twelfth process. 13. A method according to claim 8, wherein
An integrated circuit failure analysis method according to any one of the above. 14. A thirteenth process for determining whether each analysis in the second process hangs up, and
14. The integrated circuit failure analysis method according to claim 8, wherein in the second processing, the analysis is continued while excluding the analysis determined to be hung in the thirteenth processing.