JP3292895B2 - Charge pump circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit for generating a high voltage higher than a power supply voltage.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a configuration of a conventional charge pump circuit. The output side of the inverter I ₁ clock φ is input is connected to the input terminal and the gate of the transistor to Q ₁ inverter I _2. The output side of the inverter I ₂ is connected to the node N _L via a series circuit of a capacitor charge pump C _P and transistor Q _2, the node N _L
It is grounded through the load capacitor C _L. A connection portion between the capacitor charge pump C _P and transistor Q ₂ node N
_CP is connected to the gate of the transistor Q _2, is connected to the power source V _C via the transistor Q _1. Transistor Q ₂ functions as a rectifying element to _switch from node N _CP to node N _L
Current flows in one direction.

Next, the operation of this charge pump circuit will be described. When clock φ goes low, transistor Q
₁ is turned on, the one terminal serving node N _CP capacitive charge pump C _P, voltage V _CC of the power supply V _C is applied through the transistor Q _1, the node N _CP is V _CC -V _TH ... (1) V _TH is charged with a voltage of the threshold voltage of the transistor Q _1.

[0004] Next, when the clock φ becomes H level, the voltage V _CC becomes the other side terminal connected to the power supply V _C of the capacitor charge pump by the inverter I ₂ of the second stage C _P, one side of capacitor C _P charge pump voltage terminals, the capacitive coupling C _P charge pump is supplied to the node N _L via 2V _CC -V _TH ... (2), and the transistor Q _2. Then the node N _L output voltage V _L at the rises according to the capacitance ratio between the capacitance C _P charge pump and the load capacitance C _L.

Next, the output voltage V of the charge pump circuit
_L is, in order to explain why increases according to the capacitance ratio between the capacitance C _P charge pump and the load capacitance C _L, determine the rise [Delta] V _L of the output voltage V _L by one clock phi.
When the transistor Q ₂ is turned on, the charge pump capacitance C
Charge stored in _P flows into the load capacitance C _L through the transistor Q _2. Voltage V _CP at this time node N _CP
Is −ΔV _CP , the transistor Q ₂
When the threshold voltage is ignored, the following equation is established. V _CP −ΔV _CP = V _L + ΔV _L (3)

Since the amount of charge is equal before and after the transistor Q ₂ is turned on, the following equation is established according to the law of conservation of charge. _{ΔV CP × C P = ΔV L} × C L ... (4) _{Therefore, ΔV L = {C P /} (C P + C L)} × (V CP -V L) ... a (5).

From equation (5), assuming that the initial voltage of the output voltage V _{L at} the node N _L is 0 V, the output voltage V _L (n) after applying n clocks is V _L (n) = V _CP − _{V CP × {C L / (} C P + C L)} n ... a (6). (5) than, increment [Delta] V _L of the output voltage depends on the capacity ratio of the capacitance C _P charge pump and the load capacitance C _L, the voltage difference between the voltage V _CP of the node N _CP and the output voltage V _L Dependent. The output voltage V _L from the addition (6) becomes a voltage V _CP of the final node N _CP.

[0008]

Since the conventional charge pump circuit is configured as described above, the output voltage V
_In order to configure a charge pump circuit capable of increasing _L in a short time, the increase ΔV _L of the output voltage by one clock φ may be increased. As it is sufficient to increase the capacitance C _P or voltage difference V _CP -V _L charge pump in order the
This is clear from equation (5). However, if you increase the capacitance of the capacitor for the charge pump C _P, there is a problem that the degree of integration of circuits is reduced. An object of the present invention is to provide a charge pump circuit in which the output voltage can be increased in a short time without increasing the charge pump capacity in view of such a problem.

[0009]

A charge pump circuit according to a first aspect of the present invention charges a capacitive element according to a clock, and
Charge pump circuit that outputs high voltage according to the charging voltage of
One end of the road when the clock is in the first state.
When the clock is charged to a constant voltage and the clock is in the second state
The voltage at the other end changes according to the clock.
A first capacitor element that changes the voltage at the one end to a first voltage
And a first switching signal based on the clock
A first switch for outputting the first voltage as a first output voltage;
A first switch circuit stage having a switch circuit;
Are connected in series to the switch circuit stages of
One end is charged to the constant voltage when the battery is in the first state.
When the clock is in the second state,
A first output voltage of the first switch circuit stage is provided.
The voltage at the one end changes to a second voltage.
And a delay stage for delaying the first switching signal
And the second switching signal delayed by the delay stage
A second switch for outputting the second voltage as a second output voltage;
And a second switch circuit stage having a switch circuit .

A charge pump circuit according to a second aspect of the present invention charges a capacitive element in response to a clock, and charges the capacitive element in accordance with the charge voltage.
In a charge pump circuit that outputs high voltage
One end is charged so as to have a constant voltage according to the
And the constant voltage after the capacitive element is charged.
The constant according to the voltage applied to the other end of the capacitive element
And a switch circuit that outputs a voltage higher than the voltage.
A first channel having a plurality of switch circuit stages connected in series
Charge pump stage and more than the first charge pump stage
A second charge in which said switch circuit stages are connected in series
The output voltage of the pump stage and the second charge pump stage
A control electrode to be supplied and the first charge pump at one end.
Output voltage is supplied from the
Having a conducting electrode that also outputs a high voltage
And an element .

[0011]

[0012]

In the charge pump circuit according to the first invention, the first
Switch circuit stage and the first switch circuit stage
And a second switch circuit stage connected to
A first switch signal based on a clock causes a first switch.
A first output voltage is output from the
Switching signal delayed by the delay stage by the second switching signal.
A second output voltage is output from the second switch circuit stage.
You.

Thus, the second switch circuit stage is
Switching with a delay compared to the switching operation in the 1 switch circuit stage
Operating, the first output voltage is applied to the second switch circuit.
The voltage is stable because it is less affected by the stage,
Since the second switch circuit stage operates, the second switch
The circuit stage can also stably output the second output voltage.
Become so.

In the charge pump circuit according to the second invention,
First charge in which a plurality of switch circuit stages are connected in series
A pump stage and more charge stages than this first charge pump stage.
A second charge pon having switch circuit stages connected in series
And a second stage is provided on the control electrode.
The output voltage of the charge pump stage is supplied.
The output voltage of the energy pump stage is supplied, and high voltage is
A switching element having a conducting electrode for output.
You.

Thus, the control electrode of the switching element
Is also controlled by the first charge pump stage,
Control of output voltage value and operation timing of charge pump circuit
And the second charge pump stage is easier than the first charge pump stage.
The number of connection of the switch circuit stage of the charge pump stage of 2 is large
Therefore, the control electrode of the switching element is
High voltage can be supplied and output of charge pump circuit
High voltage can be output.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments. FIG. 1 shows the basics of the charge pump circuit according to the present invention.
FIG. 3 is a circuit diagram showing a configuration for explaining the principle . Input side and the transistor Q ₃ on the output side of the inverter I ₁ clock φ is input inverter I _2, the transistor Q ₄
Is connected to each gate. The power supply V _c is the transistor Q ₃
And it is grounded through a series circuit of a transistor Q ₅ and a transistor Q _7. The series circuit of the transistor Q ₅ and the transistor Q ₇ is a series circuit of the transistors Q ₆ and the transistor Q ₈ is connected in parallel.

The transistor Q ₅ the gate thereof to the connection portion of the transistors Q ₆ and the transistor Q _8, the gate of the transistor Q ₆ is connected to the connection portion of the transistor Q ₅ and a transistor Q _7. The gate of the transistor Q ₇ is connected to the gate of the transistor Q ₈ through an inverter I _3. A switch circuit SW is constituted by the transistors Q ₅ , Q ₆ , Q ₇ , Q ₈ and the inverter I ₃ . The output side of the inverter I ₂ via the charge pump capacitor C _P1 is connected to the connection portion serving node N _CP1 of the transistor Q ₃ and the transistor Q ₅ and Q _6, a series circuit of an inverter I ₄ and the inverter I ₅ It is connected to the gate of the transistor Q ₇ through. Transistor Q ₆ and Q
Connections and ₈ are connected to a power supply V _C via a series circuit of a charge pump capacitor C _P2 and the transistor Q _4.
A node N _{CP2, which} is a connection between the transistor Q ₄ and the charge pump capacitance C _P2 , is connected to the node N _L via the transistor Q ₂ , and the node N _L is grounded via the load capacitance C _L.

Next, the operation of the charge pump circuit thus configured will be described. In the initial state where clock φ is at L level, transistors Q ₃ and Q ₄ are both turned on,
The charge pump capacitors C _P1 and C _P2 are connected to transistors Q ₃ ,
_Charged by the voltage V _CC of the power supply V _C via Q ₄ , the voltages V _CP1 and V _CP2 of the nodes N _CP1 and N _CP2 are _{calculated as} follows: V _CP1 = V _CC −V _TH (7) V _CP2 = V _CC − V _TH (8) (where V _TH is the threshold voltage of each of the transistors Q ₃ and Q ₄ ).

[0019] The gate voltage of the transistor Q ₇ is L level, the gate voltage of the transistor Q ₈ is H level, both in the off state, the transistor Q _6, Q _7, transistor Q _5, Q ₈ is in both turned Therefore, the electrode of the charge pump capacitor C _P2 on the side not connected to the node N _CP2 is at L level, and the voltage V N of the node N _CP1 is
It is electrically disconnected from _CP1 .

[0020] Then the clock φ becomes H level, the voltage V _CP1 of the node N _CP1 by the voltage of the H level, 2
It rises to V _CC -V _TH . On the other hand, the gate voltage H level of the transistor Q _7, the gate voltage of the transistor Q ₈ becomes L level, the transistor Q _6, Q ₇ is turned on, the transistors Q _5, Q ₈ is turned off, the charge pump The electrode of the capacitor C _{P2 on} the side not connected to the node N _CP2 is connected to the node N _CP1 via the transistor Q _6.
Connected to 2V _CC -V _TH . Thereby, the node N
Voltage V _CP2 of _CP2 is by capacitive coupling, 3V _CC -2V _TH
To rise. The transistor Q ₂ is turned on is given a voltage V _CP2 of the node N _CP2 at its gate, it will provide a voltage at the node N _CP2 to the node N _L. Then, the output voltage V _{L is changed} to the charge pump capacitances C _P1 and C _P1.
P2 combined capacity is a _{C P1 × C P2 / (C} P1 + C P2) of increasing in accordance with the capacitance ratio of the load capacitance C _L.

As described above, by providing a plurality of charge pump capacitors each having a small unit capacitance without increasing the unit capacitance of the charge pump capacitor, the output voltage can be reduced in a short time without lowering the degree of circuit integration. Can be enhanced. In this embodiment, two charge pump capacitors C _P1 and C _{P1
Although P2} is connected in series via the switch circuit SW, three or more charge pump capacitors may be connected in series in multiple stages via the switch circuit. And
When n charge pump capacitors are provided, the charge voltage of the last stage charge pump capacitor is V _CC + n (V _CC −V _TH ).
Becomes

FIG. 2 shows a charge pump circuit according to the present invention.
FIG. 2 is a circuit diagram illustrating a configuration of an example . The output side of the inverter I ₁ clock φ is input, and the gates of the transistors Q ₃ and the transistor Q _3A, is connected to the input side of the inverter I _2. A power source V _C is the transistor Q _3, a transistor Q _5, is grounded via a series circuit of a transistor Q _7, the series circuit of the transistor Q ₅ and the transistor Q _7, the transistor Q ₆ and the transistor Q ₈
Are connected in parallel. Transistor Q ₆ and Q
₈ connecting portion of the (Q ₅ and Q _7), the transistor Q
₅ (Q ₆ ), and the gate of transistor Q ₇ is connected to the gate of transistor Q ₈ via inverter I ₃ . Transistors Q ₅ , Q ₆ , Q ₇ , Q ₈
Constitute a switch circuit SWa and by an inverter I _3. The output side of the inverter I ₂ is connected to the connection portion of the transistors Q ₃ and Q ₅ and Q ₆ through the capacitor charge pump C _P1, the transistor Q ₇ via a series circuit of an inverter I ₄ and the inverter I ₅ Connected to the gate.

The power supply V _C is grounded via a series circuit of the transistors Q _3A , Q _5A and Q _7A . Connection of the transistor Q ₆ and Q ₈ is connected via a charge pump capacitor C _P2 transistor Q _3A and the transistor Q _5A, a connecting portion between Q _6A. Inverter I ₃
The output side of the is connected to the gate of the transistor Q _8, is connected to the gate of the transistor Q _7A via a series circuit of an inverter I _4A and the inverter I _5A. The series circuit of the transistor Q _5A and the transistor Q _7A is a series circuit of a transistor Q _6A and the transistor Q _8A are connected in parallel. The connection between the transistors Q _6A and Q _8A (Q _5A and Q _7A ) is connected to the gate of the transistor Q _5A (Q _6A ). The gate of the transistor Q _7A is connected to the gate of the transistor Q _8A through an inverter I _3A. Constitute a switch circuit SWb by transistors _{Q 5A, Q 6A, Q 7A} , Q 8A and inverter I _3A. Transistors Q _6A and Q
Connection between _8A is connected to node N _L via a conductive electrode of the transistor Q _2, the node N _L is grounded through the load capacitor C _L.

The output side of the inverter I ₁₁ clock φ is input is connected to the input side of the inverter I _12, to the gates of the transistors _{Q 19, Q 29, Q 39} . Power supply V _C
Is the transistor Q ₁₉ (Q ₂₉ , Q ₃₉ ) and the transistor Q ₁₅
(Q ₂₅ , Q ₃₅ ) and the transistor Q ₁₇ (Q ₂₇ , Q ₃₇ ) are grounded via a series circuit. Transistor Q
The series circuit of ₁₅ (Q ₂₅ , Q ₃₅ ) and transistor Q ₁₇ (Q ₂₇ , Q ₃₇ ) includes a series connection of transistor Q ₁₆ (Q ₂₆ , Q ₃₆ ) and transistor Q ₁₈ (Q ₂₈ , Q ₃₈ ). Circuits are connected in parallel.

The connection portion of the transistors Q ₁₆ and (Q _26, Q ₃₆₎ and the transistor _{Q 18 (Q 28, Q 38} ) is connected to the gate of the transistor _{Q 15 (Q 25, Q 35} ), the transistor Q ₁₅ ( Q ₂₅ , Q ₃₅ ) and transistor Q ₁₇ (Q ₂₇ , Q ₃₇ )
Is connected to the gate of the transistor Q ₁₆ (Q ₂₆ , Q ₃₆ ). The gate of the transistor _{Q 17 (Q 27, Q 37} ) is connected to the gate of the transistor Q ₁₈ via the inverter _{I 13 (I 23, I 33} ) (Q 28, Q 38). Transistor Q ₁₅ (Q ₂₅ , Q ₃₅ ), Transistor Q ₁₆ (Q ₂₆ , Q
_36), the transistor _{Q 17 (Q 27, Q 37} ), the transistor _{Q 18 (Q 28, Q 38} ) and the inverter _{I 13 (I 23, I 33} )
Form a switch circuit SWc (SWd, SWe).

The output side of the inverter I ₁₂ is connected to the inverter I ₁₄
And the transistor Q via a series circuit of an inverter I ₁₅
Is connected to the gate _17, it is connected to the connection portion of the transistors Q ₁₉ and the transistor Q _15, Q ₁₆ through capacitive charge pump C _P11. Connection of the transistor Q ₁₆ and Q ₁₈ via the charge pump capacitor C _P12, is connected to the connection portion of the transistors Q ₂₉ and the transistor Q _25, Q _26. The output side of the inverter I ₁₃ is connected to the gate of the transistor Q _18, is connected to the gate of the transistor Q ₂₇ via a series circuit of an inverter I ₂₄ and the inverter I _25. Connection of the transistor Q ₂₆ and Q ₂₈ is connected to the connection portion of the transistors Q ₃₉ and the transistor Q _35, Q ₃₆ through a charge pump capacitor C _P13. The output side of the inverter I ₂₃ is connected to the gate of the transistor Q _28, is connected to the gate of the transistor Q ₃₇ via a series circuit of an inverter I _34, and an inverter I _35. Connection of the transistor Q ₃₆ and Q ₃₈ is connected to the transistor Q ₂ gate (control electrode).

Next, the operation of the charge pump circuit will be described. When clock φ is at L level, transistor Q
₃ , Q _3A , Q ₁₉ , Q ₂₉ and Q _{39 all} turn on. The switch circuit SWa, SWb, SWc, SWd, transistor Q ₅ of _{SWe, Q 8, Q 5A,} Q 8A, Q 15, Q 18, Q 25, Q 28,
When Q ₃₅ and Q ₃₈ are turned on, the charge pump capacitance C _P1 ,
C _P2 , C _P11 , C _P12 , and C _P13 are charged to the voltage of V _CC -V _TH by the voltage V _CC of the power supply V _C. Next, when the clock φ goes high, the transistors Q ₃ , Q _3A , Q ₁₉ , Q
_29, Q ₃₉ are both turned off.

The switch circuits SWa, SWb, SWc, SWd
, SWe transistors Q ₆ , Q ₇ , Q _6A , Q _7A , Q ₁₆ ,
Q ₁₇ , Q ₂₆ , Q ₂₇ , Q ₃₆ , Q ₃₇ are turned on. This connects the charge pump capacitors C _P1 and C _P2 in series,
The charge pump capacitors C _P11 , C _P12 and C _P13 are connected in series. Thereby, the source of the transistor Q _2, i.e. the connection of the transistor Q _6A and Q _8A is given a voltage of _{V CC +2 (V CC -V TH} ).

On the other hand, the gate of the transistor Q ₂ has V _CC +
A voltage of 3 (V _CC -V _TH ) is provided. Therefore, the gate of the transistor Q _2, source voltage V _CC, and the become sufficiently higher voltage than the threshold voltage of the transistor Q _2, the output voltage V _L has decreased by the threshold voltage of the transistor Q ₂ no, thereby charging the load capacitance C _L is a voltage of V _CC +2 given to the source of the transistor _{Q 2 (V CC -V TH)} . Thus, the output voltage can be increased in a short time.

[0030]

According to the charge pump circuits according to the first and second aspects of the present invention, the output voltage can be increased in a short time by providing a plurality of capacitance elements without increasing the unit capacitance of the capacitance elements. Further, the degree of integration of the circuit is not reduced. Further, by increasing the number of capacitors connected in series via the switch circuit, excellent effects such as an increase in output voltage in accordance with the number of capacitors can be achieved.

Further, according to the charge pump circuit of the second aspect, the voltage of the control terminal of the switching element becomes sufficiently higher than the threshold voltage of the switching element, and the output voltage of the switching element is the threshold. Since the voltage is output as a voltage that does not decrease due to the value voltage, the output voltage can be increased in a short time.

[Brief description of the drawings]

FIG. 1 shows the basic principle of a charge pump circuit according to the present invention.
FIG. 3 is a circuit diagram showing a configuration for explanation .

FIG. 2 is a circuit diagram showing a configuration of an embodiment of a charge pump circuit according to the present invention.

FIG. 3 is a circuit diagram showing a configuration of a conventional charge pump circuit.

[Explanation of symbols]

_{Q 2, Q 3, Q 4} , Q 5, Q 6, Q 7, Q 8 transistor _{I 1, I 2, I 4} , I 5 inverter V _C power C _P1, C _P2 capacitor charge pump C _L load capacity

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Yoshikazu Miyawaki 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Machinery Co., Ltd. LSI Research Institute (72) Inventor Takeshi Nakayama 4-chome Mizuhara, Itami-shi, Hyogo No. 1 Mitsubishi Electric Corporation, within LSI Laboratories (56) References JP-A-63-316510 (JP, A) JP-A-54-105723 (JP, A) JP-A-63-287360 (JP, A)

Claims (2)

(57) [Claims] 1. A charge pump circuit for charging a capacitive element according to a clock and outputting a high voltage according to the charged voltage, wherein one end is charged to a constant voltage when the clock is in a first state.
And the voltage at the other end when the clock is in the second state.
Changes in response to the clock, so that
A first capacitor whose voltage changes to a first voltage;
The first voltage is changed by a first switching signal based on lock.
A first switch circuit that outputs a first output voltage.
A first switch circuit stage, and a first switch circuit stage connected in series with the first switch circuit stage.
When the clock is in the first state, one end is connected to the constant voltage.
When the clock is in the second state
The other end receives the first output voltage of the first switch circuit stage.
The voltage at the one end changes to the second voltage
And a second capacitor element for delaying the first switching signal.
And a second switching signal delayed by the delay stage
To output the second voltage as a second output voltage.
A second switch circuit stage having a second switch circuit;
A charge pump circuit comprising the. 2. A capacitor is charged according to a clock, and the capacitor is charged.
In a charge pump circuit that outputs a high voltage according to the charging voltage, one end is charged to a constant voltage according to the clock.
And the constant voltage after the capacitor is charged.
Depending on the voltage and the voltage applied to the other end of the capacitive element.
It consists of a switch circuit that outputs a voltage higher than a certain voltage.
A plurality of switch circuit stages to be formed are connected in series.
A charge pump stage and a greater number of said switch circuits than said first charge pump stage.
A second charge pump stage in which the road stages are connected in series, and a control system to which an output voltage of the second charge pump stage is supplied.
A control electrode, and one end of the output voltage of the first charge pump stage.
Pressure is supplied, and a voltage higher than the constant voltage is supplied from the other end.
And a switching element having a conducting electrode for outputting.
A charge pump circuit, characterized in that that.