JP3291112B2 - Charge pump circuit and PLL circuit using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit and a PLL circuit using the same, and more particularly, to a charge pump circuit usable in a high frequency range and a PLL using the same.
It relates to an L circuit.

In recent years, in the field of communications, high-frequency signals have been used with the development of optical communications and the like. To handle high-frequency signals, a high-frequency clock synchronized with them is required.

In general, a PLL circuit is used to synchronize a signal and a clock. As the frequency of a signal increases, the PLL circuit is required to operate at a high frequency with good responsiveness.

[0004]

2. Description of the Related Art FIG. 9 shows a configuration diagram of a conventional PLL circuit. The PLL circuit 60 includes a voltage controlled oscillator (VCO) 61,
Frequency divider 62, phase comparator 63, charge pump circuit 6
4, a loop filter 65. The output of the VCO 61 becomes a reproduced clock and is supplied to a frequency divider 62 to be divided. After the frequency division by the frequency divider 62, the phase comparator 6
3 is supplied. The reference clock is supplied to the phase comparator 63, the signal from the frequency divider 62 is compared with the reference clock, and a non-inverted clock (up signal UP) and a non-inverted clock of a level corresponding to the phase difference are generated. The inverted clock (down signal DWN) is output.

[0005] The clock generated by the phase comparator 63 is supplied to a charge pump circuit 64.

In the charge pump circuit 64, the phase comparator 6
An output signal O corresponding to the level fluctuation of the clock 3 is output and supplied to the VCO 61 via the loop filter 65.

FIG. 10 shows a configuration diagram of a conventional charge pump circuit 64.

A conventional charge pump circuit 64 is a PFD 6
Inverted up signal UPi and the inverted down signal DWNi supplied from 3 depletion type MOS transistor _{Tr 6 1, Tr 62, Tr} 63, Tr 64 and an enhancement type MOS transistor _{Tr 65, Tr 66, Tr 67} , Tr 68
More becomes inverted input circuit 64a, it is entered through a 64b, and switching control of the respective output transistor Tr _69, Tr _70, had gained an output signal.

[0009]

However [0007], the conventional charge pump circuit input buffer circuit 64a, 64b and the output transistor Tr _69, which is composed of Tr _70, the output transistor Tr _{6 9,} Tr ₇₀ gate - drain There has been such a problem that the rise of the output signal is delayed due to the inter-capacitance and the response of the output signal becomes dull.

Further, the PLL circuit constituted by such a charge pump circuit has a problem that response is slow and cannot be used for high-speed switching used in an optical communication system or the like.

The present invention has been made in view of the above points, and has as its object to provide a charge pump circuit that can respond to an input signal at high speed.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention. FIG. 1 shows a principle diagram of claim 1. The capacitive element 1 is charged and discharged according to the input signal, and supplies the input signal.

The switching element 2 is connected via the capacitive element 1
Input signal is supplied as a control signal,
The switching operation is performed in the same manner to output an output signal.

[0014] The clamping means 3 is a switching element 2
Clamps the output signal output from the
Bias gate 2

According to a second aspect of the present invention, a constant voltage is clamped in place of the output signal in the clamp means 3, and the switching element 2 is biased by the constant voltage.

A third aspect of the present invention is a voltage controlled oscillator 41 for controlling a reproduced clock signal frequency in accordance with the output signal, and a signal which is synchronized with the reproduced clock signal of the voltage controlled oscillator 41 and the reproduced clock signal. 3. A PLL comprising: a phase comparator for detecting a phase difference from a reference clock synchronized with a signal to be supplied, and supplying a phase difference signal corresponding to the phase difference as an input signal of the charge pump circuit according to claim 1 or 2. It constitutes a circuit.

[0017]

According to the first and second aspects, the output signal is clamped by the clamp means in accordance with the output signal or the power supply voltage,
Since the switching of the switching operation control signal when the switching element is turned off can be prevented by charging the capacitive element, the response of the output signal to the input signal can be improved.

According to the third aspect, since the response of the charge pump circuit in the PLL circuit is improved, it is possible to improve the clock operation of the reproduced clock and the ability to follow the reference clock.

[0019]

FIG. 1 shows a configuration diagram of a charge pump circuit according to a first embodiment of the present invention. Charge pump circuit 1 of the present embodiment
Reference numeral 1 denotes an up-side circuit 12 and a down-side circuit 13.

The up-side circuit 12 charges up a signal in accordance with the rise of the input signal, and the down-side circuit 13 charges up a signal in accordance with the fall of the input signal.

The up side circuit 12 includes an input circuit 14, a capacitor C ₁ corresponding to the capacitive element ₁ , a switching element 2
Transistor j ₄ corresponding to, composed of clamp circuit 15, which corresponds to the clamping means 3.

The input signal S _UP is supplied to the input terminal T _IN1 of the up-side circuit 12. Input terminal T _IN1 is input circuit 1
4 through is connected to one end of the capacitor C _1. The input circuit 14 includes enhancement (E) type MOS transistors Tr ₁ and Tr ₂ and depletion (D) type MOS transistors Tr ₃ and Tr ₄ , and constitutes an E / D type inversion buffer circuit.

The output of the input circuit 14 is supplied to the gate of the transistor j ₄ via the capacitor C _1. Transistor j
₄ consists of enhancement type MOS transistors,
The source high potential side voltage V ₁ is applied, and the drain is connected through an output transistor j6 of the down-side circuit 13 to the low potential side voltage V _2.

The clamp circuit 15 has an output terminal T
_OUT is connected.

The clamp circuit 15 is a depletion type M
OS transistor j₁, J_TwoAnd enhancement type M
OS transistor j_ThreeIt is composed of Transistor j
₁Is the high-potential side voltage V₁Connected to the drain
Transistor j for generating constant current _TwoConnected to the drain of
An output signal is supplied to the gate.

The drains of the transistors j ₂ of the transistor j ₁ is connected to the gate of the transistor j ₄ through the rectifier transistor j _3. Clamp circuit 1
5 clamps the output signal and biases the gate of the transistor j4 with a voltage according to the output signal.

The down side circuit 13 includes an input circuit 16, a capacitor C ₃ corresponding to the capacitive element 1, a switching element 2
Transistor j ₅ corresponding to, comprised of transistors j ₅ corresponding to the clamping means 3.

The input circuit 16 is the same configuration as the input circuit 14, depletion type MOS transistors Tr _5, Tr ₆
And enhancement type MOS transistors Tr ₇ , Tr ₈
Constitutes an inversion buffer. An input terminal T _IN2 is connected to the input circuit 16, and an input signal S _IN2 obtained by inverting the input signal S _IN1 of the up-side circuit 12 is supplied to the input terminal T _IN2 . Input signal S _IN2 supplied to the input terminal T _IN2 is supplied to one end of the capacitor C ₃ through the input circuit 16. The other end of the capacitor C ₃ is connected to the gate of the transistor j _6.

The drain of the transistor j ₆ is connected to the drain of the transistor j ₄ of the up-side circuit 12, and the low potential side voltage V ₂ is applied to the source. The gate of the transistor j ₆ the low potential side voltage V ₂ is applied through the clamp transistor j _5.

[0030] clamping transistor j ₅ has a drain connected to the gate of the transistor j _6, source and gate are connected to the low potential side voltage V _2, to clamp a voltage corresponding to the low potential side voltage V _2, are bias the gate of the transistor j _6.

The output of the charge pump circuit 11 is a connection point P ₀ between the transistor j ₄ and the transistor j _6, and the connection point P ₀ is a low-pass filter 17 forming a loop filter.
Supplied to The low-pass filter 17 includes a resistor R ₁ ,
It is composed of R ₂ and a capacitor C _2, and cuts the high frequency component of the supplied signal and supplies it to the output terminal T _OUT . A signal from which the high-frequency component has been removed through the low-pass filter 17 is supplied to the clamp circuit 15, and the clamp circuit 15 clamps the input signal to a level corresponding to the output.

FIG. 3 is a diagram for explaining the operation of the first embodiment of the present invention.
Show. In the figure, (A) shows the input signal S _IN1, (B) is input
The output signals b and (C) of the circuit 14 are the charge pump circuit 1
1 and the transistor j_FourGate voltage c,
(D) is the input signal S_IN2, (E) are the outputs of the input circuit 16
The signal d, (F) is the transistor j₆Shows the gate voltage e of
You.

According to this embodiment, since the gate voltage of the transistor j ₄ is biased in accordance with the output signal σ,
The gate of the transistor j ₄ - source, gate - drain can be held in a state of being charged to an appropriate value corresponding to the continuous output signal σ a, the gate voltage c as shown in FIG. 3 (C) during the switching operation of the transistor j ₄ for never rises dull, without causing a delay in the operation of the transistor j _4, therefore, does not occur delays in response of the output sigma, it can cope with high-speed signals.

FIG. 4 shows a configuration diagram of a second embodiment of the present invention. The charge pump circuit 21 of the present embodiment includes the up circuit 2
2, a down circuit 23.

The up circuit 22 is an input circuit 24, the capacitive element 1 and comprising a capacitor C _11, the transistor j ₁₁ more as a switching element 2, the clamp circuit 25 becomes a clamp means 3 is constituted by the output resistor R _11.

The input circuit 24 is a depletion type MOS
Is constituted by the transistors Tr ₂₁ and an enhancement type MOS transistor Tr _22, it constitutes an input buffer, up input signal supplied to the input terminal T _IN21 UP
Is input. The output of the input circuit 24 is supplied to the gate of the transistor j ₁₁ via a capacitor C _11.

Transistor j₁₁Is the high voltage on the source side
V₁And the drain is connected to the resistor R ₁₁Via the output terminal
T_OUT2It is connected to the.

Further, the gate of the transistor j ₁₁ is connected the clamp circuit 25 is controlled in accordance with the output signal of the bias of the gate.

The clamping circuit 25 is a depletion type M
OS transistors Tr ₂₃ , Tr ₂₄ , Tr ₂₅ , enhancement type MOS transistors Tr ₂₆ , Tr ₂₇ , Tr ₂₈ ,
Capacitor C _13, the Schottky diode first clamping circuit and a depletion-type MOS transistor Tr _29, Tr ₃₀ consisting of D _S1, enhancement type MOS transistor _{Tr 31, Tr 32, Tr 33} , a second clamp consisting of resistor R ₂₁ is composed of the circuit, while being performed amplitude controlled by the Schottky diode D _S1 at a timing corresponding to the input UP signal by the first clamping circuit, a gate voltage of the transistor j ₁₁ is biased, and by the second clamping circuit, The bias voltage is supplied while being controlled to a predetermined value corresponding to the output voltage.

The down side circuit 23 includes a depletion type MOS transistor Tr ₃₄ , an enhancement type MOS transistor
Schottky diode D _S2 constituting the inverting input circuit 23a consisting of transistor Tr _35, a capacitor C ₁₂ constituting the capacitive element 1, transistor j ₁₂ constituting the switching element j _12, resistor R _12, the clamping means 3, depletion type MOS transistor Tr _36, made of an enhancement type MOS transistor Tr _37, Tr _38, the down signal DWN is an inverted signal of the up signal uP is supplied, the timing circuit for controlling the timing of the supply of the gate voltage of the transistor j _12, di Prescription type MOS
A transistor Tr ₃₉ and enhancement type MOS transistors Tr ₄₀ and Tr ₄₁ are provided. The constant voltage V ₁ and the down signal DWN are supplied to the transistor j _{12 to control} the source potential of the transistor j ₁₂ at a timing corresponding to the down signal DWN. .

FIG. 5 is a diagram for explaining the operation of the second embodiment of the present invention. In the figure, (A) is an UP input signal supplied to the terminal T _IN22 , (B) is an inverted down signal DWNi supplied to the terminal T _IN22 , (C) is a bias voltage Vref, Vref ′ and a gate signal c, (D) shows the voltage d waveforms of the gate of the transistor j _12.

According to this embodiment, the up-side circuit 22 and the down-side circuit 23 cancel out high-frequency components, and an output signal as shown by σ is obtained as an output signal.

[0043] At this time, since it is charged the gate voltage by the clamp circuit 25, as shown in FIG. 5 (C), when the switching operation of the transistor j ₁₁ because never dull the rising of the transistor occurs, the output σ According to the present embodiment, no delay occurs, and the reference voltage level Vref ′ of the bias signal level can be set by the bias circuit, and the output is adjusted by adjusting the bias signal level to an appropriate level as shown in FIG. No variation occurs in the signal σ.

FIG. 6 shows a configuration diagram of a third embodiment of the present invention. The charge pump circuit 30 according to the present embodiment includes an up-side circuit 31 and a down-side circuit 32. The outputs of both circuits are added to form an output signal.

The up-side circuit 31 includes a capacitor C _{31 as} the capacitive element 1, a transistor j _{21 as the} switching element 2, an output resistor R ₃₁ , and a clamp circuit 32 as the clamp means 3.

The clamp circuit 32 is first clamp circuit 32a for controlling the biasing of the transistor j ₂₁ in accordance with the output signal sigma, and, at the inversion timing of up signal UPi which is an inverted signal of the up signal UP, the output signal sigma composed of the second clamp circuit 32b for controlling the biasing of the transistor j ₂₁ in accordance with the level.

The first clamp circuit 32a depletion type MOS transistor _{Tr 42, Tr 43, Tr 44} , enhancement type MOS transistor Tr _45, Tr _46,
Consists of resistors R _31, R _32, R ₃₃ to adjust the current variation due to variation in transistor Tr ₄₂ to Tr _46, the output σ
A voltage corresponding to the supplied to the gate of the transistor j _21.

The second clamp circuit 32b is depletion type MOS transistor Tr _46, Tr _47, enhancement type MOS transistor Tr _48, Tr _49, resistor R ₃₄ to adjust the current variation due to variation in transistor Tr _46, Tr _47, R ₃₅ , Inverted up signal input capacitor C
_33, composed of the amplitude limiting Schottky diode D _S11.

The down-side circuit 33 includes a capacitor C ₃₂ forming the capacitive element 1, a transistor j ₂₂ forming the switching element 2, an output resistor R ₃₂ , a (Schottky) diode DS ₁₂ forming the clamping means 3, and an enhancement type. MOS transistor _{Tr 5 0, Tr 51, Tr} 52, consists of a capacitor C _34, the inverted down signal DWNi is supplied an inverted signal of the down signal DWN, the transistor j
_A depletion type MOS transistor T for controlling the timing of supply of _twelve gate voltages;
r ₅₃ , enhancement type MOS transistor Tr ₅₄ ,
Consists tr _55, a constant voltage V ₁ is supplied, composed of a circuit for controlling the source potential of the transistor j _12.

According to this embodiment, substantially the same operation as in the second embodiment can be performed, and the response of the output signal to the input signal can be improved.

In the first to third embodiments, the MO
Although the circuit is configured using the S transistor, it can be configured using a transistor such as an MES type or a HEMT. The use of the MES type, the HEMT, and the like enables further increase in speed, and a signal of several GHz is used. Also, good responsiveness can be obtained.

FIG. 7 shows a block diagram of one embodiment of the PLL circuit of the present invention. The PLL circuit 40 includes a voltage controlled oscillator (VC
O) 41, a frequency divider 42, a phase comparator 43, a charge pump circuit 44, and a loop filter 45. VC
The output of O41 becomes a reproduction clock and is supplied to a frequency divider 42 to be frequency-divided. After being frequency-divided by the frequency divider 42, it is supplied to the phase comparator 43. The reference clock is supplied to the phase comparator 43, the signal from the frequency divider 42 is compared with the reference clock, and a non-inverted clock (up signal UP) and a non-inverted clock of a level corresponding to the phase difference are generated. The inverted clock (down signal DWN) is output.

The clock generated by the phase comparator 43 is supplied to a charge pump circuit 44. The charge pump circuit 44 includes the charge pump circuits 11, 21, and 30 described in the first to third embodiments of the present invention.

The charge pump circuits 11, 21 and 30 output the output signal O corresponding to the fluctuation of the clock level as described above, and are supplied to the VCO 41 via the loop filter 45.

As described above, the charge pump circuit 44 of the PLL circuit 40 of this embodiment is connected to the charge pump circuit 1 described above.
By using 1, 21 and 30, the response of the output signal of the charge pump circuit 44 to the output of the phase comparator 43 can be improved, so that the PLL lock operation can be performed accurately.

FIG. 8 shows a configuration diagram of an application example of the PLL circuit 40. This application example shows a configuration of an optical communication system. The optical signal transmitted from the transmitter 51 is transmitted by the optical fiber 52 and supplied to the receiver 53.

In the receiver 53, the light transmitted through the optical fiber 52 by the light detector 54 is converted into an electric signal.
5 to an AGC 56, and a clock regenerator 57,
The data is supplied to the data identification circuit 58 and the like.

The clock regenerator 57 generates a clock synchronized with the electric signal by the PLL circuit 40 based on the supplied electric signal and supplies the clock to the data identification circuit 58. The data identification circuit 58 demodulates data based on the clock supplied from the clock regenerator 57.

In the above system, by using the above-described PLL circuit 40, a clock locking operation can be accurately performed on a supplied signal, and errors in data identification are reduced.

[0060]

As described above, according to the first and second aspects of the present invention, it is possible to prevent the switching operation control signal of the switching element from being lowered by the clamp means and the capacitive element. It can be improved.

According to the third aspect, by using the charge pump circuits of the first and second aspects in a PLL circuit, high-speed tracking can be performed. Therefore, locking and following can be performed at high speed in the PLL circuit, and a high-frequency clock generation can be performed. It has features such as being able to respond to

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of a first embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 4 is a configuration diagram of a second embodiment of the present invention.

FIG. 5 is an operation explanatory view of a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a third embodiment of the present invention.

FIG. 7 is a configuration diagram of a PLL circuit using the charge pump circuit of the present invention.

FIG. 8 is a configuration diagram of a communication system using the PLL circuit of the present invention.

FIG. 9 is a configuration diagram of a PLL circuit.

FIG. 10 is a configuration diagram of a conventional charge pump circuit.

[Explanation of symbols]

First storage capacitor 2 switching element 3 the clamping means 11 a charge pump circuit 14, 16 Input circuit C _1, C ₃ capacitors j _4, j ₆ output transistor 15 clamp circuit J ₅ clamping transistor

Continuation of the front page (56) References JP-A-2-11021 (JP, A) JP-A-2-155309 (JP, A) JP-A-5-227012 (JP, A) JP-A-63-206815 (JP) , A) JP-A-1-200719 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03L 7/093

Claims (3)

(57) [Claims] A capacitive element that is charged and discharged in response to an input signal; and the input signal is supplied as a control signal via the capacitive element, and performs a switching operation in accordance with the control signal to output an output signal. A switching element to be output and the output signal output from the switching element.
Ramp to bias the gate of the switching element.
A charge pump circuit, characterized in that it comprises a clamping means that. 2. The charge pump circuit according to claim 1, further comprising means for controlling an amplitude of a signal for biasing said switching element. 3. The charge pump circuit according to claim 1 or 2, a voltage controlled oscillator for controlling a reproduced clock in accordance with an output signal of the charge pump circuit, and a reproduced clock signal of the voltage controlled oscillator and a reference. And a phase comparing means for detecting a phase difference from a clock and supplying a phase difference signal corresponding to the phase difference to the charge pump circuit.