JP3290992B2 - Flexible FPGA input / output architecture - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Field of the Invention The present invention relates to a field programmable gate array (FPGA) architecture. More specifically, the present invention relates to an FPGA having flexible input / output capability.

2. Prior Art In recent years, field programmable gate array integrated circuits have been established as important products in electronics. Typically, such integrated circuit architectures include an array of logic function modules designed for users to perform many types of logic functions. Programmable interconnect architecture, including multiple interconnects that are pre-interconnected, is superimposed on an array of logic function modules, allowing custom connections between one input and output of the logic function module become. A plurality of input / output (I / O) modules are typically located near the periphery of the array on the integrated circuit and transfer logic signals from the array to off-chip circuit nodes and further to the array. I / O modules can be connected to inputs and outputs of logic function modules via a programmable interconnect architecture.

The above elements of a typical FPGA may be selectively connected to each other with user-programmable interconnect elements by a user. User programmable interconnect elements can take several forms, such as temporarily programmable antifuses, transistors, and RAM cells.

Examples of transistor interconnect elements based on FPGA features are disclosed to people in US Pat. No. 4,870,302. Products embodying this type of architecture are available from Xilinx I in Santiago, California.
nc). In this architecture, the transistors controlled by the RAM cells are selectively turned on, forming an interconnect between the logic function modules. Another example can be found in U.S. Pat. No. 5,187,393, which uses EPRAM or EEPRAM, by El Gamal et al. However, the flexibility of those architectures, such as being reprogrammable, is offset by the relatively high resistance of the transistors performing the interconnect.

Some examples of embodiments of antifuses based on the FPGA architecture are described in U.S. Pat.
No. 745, U.S. Pat.No. 4,873,459 by El Gamar et al.
No. 5,073,729 to Greene et al., US Pat. No. 5,083,083 to El Ayat et al., And US Pat. No. 5,132,571 to McCorm et al.

The I / O architecture of traditional FPGA devices is typically 2
One of the three forms. In a first configuration, illustrated in U.S. Pat. No. 4,758,745, a plurality of I / O modules are located on an integrated circuit, preferably around the periphery of the integrated circuit. Each I / O module is located by the end user and may form either an input module or an output module with appropriate programming. Examples of representative I / O modules can be found in U.S. Pat. No. 5,017,813 by Gallyth et al. And U.S. Pat. No. 5,083,083 by El Ayat et al.

Typically, an I / O module is directly connected to an I / O pad and includes an input pad and an output pad, as well as the control circuitry that determines whether the module functions as an input module or an output module. I have. Since the input nodes, output nodes, and at least one control node of the I / O module are connected to individual conductors of a general interconnect architecture of the integrated circuit, the I / O module comprises:
It may be connected to a logic function module arranged on the integrated circuit. In a prior art architecture embodied in an FPGA product designed by Actel Corporation, the interconnect conductors for the input, output and control nodes of the I / O module have two to four rows of an array.

A second form of conventional FPGA I / O architecture utilizes only output conductors and buffered input conductors on I / O pads on an integrated circuit. The output and input conductors extend a fixed distance into the array of logic function modules and are sufficient to provide a single logic function module, typically located at the periphery of the integrated circuit. An example of such an architecture is described on page 212 of the 1994 Quick Logic Data Book of Santa Clara, California.

Used in FPGAs and other devices, while conventional techniques are possible to provide an arrangement in which the logic function modules of the integrated circuit are provided with inputs and outputs can be obtained
There is room for improvement in the I / O architecture.

It is an object of the present invention to provide a more flexible FPGA and a user programmable I / O architecture for integrated circuit devices than conventional architectures.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an FPGA and a user programmable I / O architecture for an integrated circuit device which eliminates having to provide I / O modules in fixed locations.

Another object of the present invention is to provide an FPGA and other user-programmable integrated circuit devices that provide multiple splitting and interconnecting options and variations on horizontal and vertical routing conductors for input, output and control signals. To provide an I / O architecture.

It is another object of the invention to provide an I / O architecture for FPGAs and user programmable integrated circuit devices having reduced programmable interconnect elements to reduce capacitance and increase speed. It is.

SUMMARY OF THE INVENTION It is an object of the present invention to provide FPGAs and I / Os for user-programmable integrated circuits that include directly connected user-programmable interconnect elements of selected routing conductors that allow unused routing conductors to be used for interconnection. O to provide an architecture.

It is an object of the present invention to provide an FPGA and user programmable integrated circuit I / O architecture that couples to one or more of the output buffers to provide increased output drive.

BRIEF DESCRIPTION OF THE INVENTION In accordance with the present invention, there is provided a flexible I / O architecture for use in FPGAs and user-programmable integrated circuit devices.

In a first embodiment of the present invention, an input / output architecture is provided for a field programmable gate array integrated circuit device. Such an FPGA includes a plurality of logic function modules arranged in an array of rows and columns. Each module has at least one input conductor and at least one output conductor. However, more typically, each module has multiple input conductors and multiple output conductors.
The interconnect architecture is mounted on the logic function module and includes a plurality of interconnect conductors that can be used in connection with the inputs and outputs of the logic function module by programming user-programmable interconnect elements.

The I / O architecture of the present invention employs multiple input / output kernels. Each input / output kernel is connected to an I / O pad of the integrated circuit, the input buffer holding a data input connected to one of the I / O pads and a data output connected to the input buffer conductor, and an output buffer. A data input connected to the buffer data conductor, a data output connected to the I / O pad, and an enable input connected to the output buffer enable conductor. The input buffer conductor and the output buffer conductor extend in the column direction or the row direction.

According to the present invention, some different of the input buffer data conductors and the output buffer data conductors have different numbers of columns or rows extending. User-programmable interconnect elements may be used to connect between the inputs and outputs of the logic function module and between the input buffer data conductors and the output buffer data.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a typical FPGA including one aspect of the I / O architecture according to the present invention. In the present invention, the I / O conductors extend at different lengths into the array of logic function modules and can be connected to the inputs and outputs of different numbers of logic function modules in the row or column direction.

FIG. 2 is a more detailed block diagram of the architecture of FIG. 1, showing a pair of columns of an array and a single vertically oriented I / O kernel.

FIG. 3 is a more detailed block diagram of the architecture of FIG. 1, showing a single pair of columns of the array and a single horizontally-oriented I / O kernel.

FIG. 4 is a more detailed partial block diagram of the FPGA shown in FIG. 1, illustrating the ability to connect to an increased drive output buffer according to the present invention.

FIG. 5 is a more detailed block diagram of a portion of the FPGA array as shown in FIG. 1, where the entire enable signal is directed both horizontally and vertically along both the rows and columns of the array. 1 illustrates an embodiment of the invention.

FIG. 6a illustrates a feature of the present invention in which the input conductors for different output buffers extend in different directions in the array.
FIG.

FIG. 6b is a block diagram of an FPGA showing features of the present invention in which the output conductors of different input buffers extend in different directions in the array.

FIG. 7 shows that the input and output buffers are generic interconnects (ge
FIG. 1 is a block diagram of an FPGA connected to a neral interconnect and showing a feature of the present invention that provides great flexibility in allocating I / O in the FPGA.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS It will be appreciated by those skilled in the art that the following description of the present invention is illustrative only and is not limited in any way. Such skilled persons will readily recognize other embodiments of the present invention. Although disclosed by such artisans herein with reference to directions defined by the terms row and column of the logic function module, such terms rotate the frame 90 degrees in either direction. It is also understood that the

FIGS. 1-3 show block diagrams of a typical FPGA array that further includes one aspect of the I / O architecture of the present invention. According to this aspect of the invention,
Dedicated I / O conductors extend different distances of the logic function module and are connectable to inputs and outputs of different numbers of logic function modules in either the row or column direction.

The present invention provides a user-programmable integrated circuit environment,
Works in a typical FPGA environment. Logic function module 12−
Arrays 1 to 12-18 are located in an integrated circuit. One of ordinary skill in the art can readily appreciate that the embodiment shown in FIG. 1 is merely exemplary, and that any number of logic function modules 12 may be located on a single integrated circuit die. In an actual integrated circuit manufactured according to the concepts of the present invention, there may be hundreds or thousands of such logic function modules 12 in the array 10.

There are many well-known logic function module 12 designs available for the present invention. A typical, but not all, specific list is U.S. Patent Nos. 4,758,745, 4,910,917.
No. 5,055,718, and those disclosed or claimed in pending application Ser. No. 08 / 332,550, filed Oct. 28, 1994. Specific logic function modules selected for actual implementation of the invention in silicon
It is understood by those skilled in the art that design choice 12 is a major issue.

For those skilled in the art, logic function modules 12-1 to 12-18
It is understood that the functions performed by any one of the following are typically not predefined by the manufacturing process, but rather can be programmed. Logic function module 12-1
Methods and circuits for programming ~ 12-18 functions are well known in the art and are outside the scope of this disclosure.

Each of the logic function modules 12-1 to 12-18 is shown to have many inputs. For illustrative purposes, each of the logic function modules 12-1 to 12-18 is shown to have five inputs 14-1 to 14-5 (labeled in modules 12-13), It extends downward from the block representing the logic function module. In an actual integrated circuit, each logic function module 12-1
The number of inputs 14 for ~ 12-18 is determined by the type of module used, and the inputs may extend in other directions or in more than one direction to facilitate interconnection.

It is also shown that each of the logic function modules 12-1 to 12-18 has several outputs. For illustrative purposes, each of the logic function modules 12-1 to 12-18 is shown to have three outputs 16-1 to 16-3 (labeled in module 12-1), which are It extends to either the right or left side of the block representing 12-1 to 12-18. In an actual integrated circuit, the outputs 16-1 to 16-3 may also extend in other directions or in more than one direction to facilitate interconnection.

Interconnect architecture is logical function module 12-1
Superimposed on an array of ~ 12-18. The interconnect architecture consists of a plurality of horizontal and vertical interconnect conductors. In order to make the drawings clear and easy to understand, the horizontal and vertical interconnect conductors are
Although shown passing between 12-18, for those skilled in the art, the actual layout of the integrated circuit according to the present invention was disclosed or claimed in U.S. Pat. No. 5,132,571 to McCollum et al. It can be appreciated that a "sea of modules" architecture may be employed. There, the interconnect conductors may be disposed directly on the logic function modules 12-1 to 12-18 in one or more metal interconnect layers.

As will be appreciated by those skilled in the art, individual interconnect conductors in an interconnect architecture may run the length or width of the array; some may be of some length as is known to those skilled in the art. May be divided.
One of the various types of user-programmable interconnect elements is that the segments of the interconnect conductor include other segments as well as inputs 14-1 and outputs 16-1-16 of the logic function modules 12-1-12-18. -3 may be used to connect. Well-known examples of such elements include antifuses, transistors, RAM cells, non-volatile memory cells, and the like. The operation and programming of such elements, including the circuitry for implementing programming and defining the particular connections to be made, are known to those skilled in the art and will not obscure the disclosure herein. Do not repeat to avoid.

In the description of the embodiment of FIG. 1, the horizontal and vertical interconnect conductors are grouped into channels that are described as multiconductor lines running between the logic function modules 12-1 to 12-18 in the horizontal and vertical directions. Indicated by For example, a group of five vertical interconnect conductors, collectively identified by reference numeral 18, is a logic function module pair 12
-3 and 12-4, 12-9 and 12-10, 12-15 and 12-16 are shown running down the array. Similarly, a group of five horizontal interconnect conductors, collectively identified by reference numeral 20, comprises the logic function module pair 12-7 and 12-7.
-13, 12-8 and 12-14, 12-9 and 12-15, 12-10 and 12-
16, 12-11 and 12-17 and running across the array between 12-12 and 12-18. The number of interconnects used in a practical embodiment of the invention is a matter of design choice.

As can be seen from FIG. 1, the interconnect elements that can be programmed by many users (as indicated by small circles, labeled 22) are the intersections of horizontal and vertical interconnect conductors. Intersections, intersections of horizontal interconnect conductors with inputs of logic function modules,
And at the intersection of the vertical interconnect conductor and the output of the logic function module. Thus, the 25 intersections formed by the merging of the five vertical interconnect conductors 18 and the five horizontal interconnect conductors 20 are all anti-intersections such as other intersecting interconnect conductors. Fuse (anti
fuses).

Those skilled in the art will recognize that the extent to which intersections are provided by antifuses is a matter of design choice, and in many cases 100% placement is not desired.

In addition, the five vertical interconnect conductors 18 are logic function modules 12-3 and 12-4, 12-9 and 12-10, 12-15 and 12
Logic function module 12-traversing outputs 16-1 to 16-3 and approaching vertical interconnection conductor 18 from the left side
3. Outputs from logic function modules 12-4, 12-10 and 12-16 that cross outputs 16-1 to 16-3 from 12-9 and 12-15 and approach the vertical interconnect conductor 18 from the right. 16
It is shown crossing -1 to 16-3. Each of these intersections is also arranged with user programmable interconnect elements.

The five horizontal interconnect conductors 20 also have inputs 14-1 to 14-5 of the logic function modules 12-7 to 12-12, and the logic function module approaching the five horizontal interconnect conductors 20 from above.
It is shown traversing inputs 14-1 to 14-5 of 12-7 to 12-12. Each of these intersections is also present by a user-programmable intersection element.

Throughout this disclosure, the term "I / O kernel" is used. As used herein, "I / O kernel" refers to an I / O unit that connects to one I / O pad on an integrated circuit. As shown in FIG. 1, there are two such I / O kernels. The first I / O kernel is most clearly defined with reference to FIG.
And an output buffer 28. The data input of input buffer 26 is connected to I / O pad 24 and output buffer 28
Is also connected to the I / O pad 24. The output of input buffer 26 is connected to data output conductor 30. The input of output buffer 28 is connected to data input conductor 32. Finally, as shown in FIG. 1, the output buffer 28 includes an enable input conductor 34 and a slew control input conductor 36. The enable input conductor 34 places the output of the output buffer 28 in a high impedance state and disables it, as is known to those skilled in the art, for example, when an I / O kernel is used as an input of an integrated circuit. Used to Various ways of implementing the functions of the enable input 34 and the slew control input 36 are known to those skilled in the art and will not be described further here.

The second I / O kernel is most apparent with reference to FIG. 3, and includes an I / O pad 38, an input buffer 40, and an output buffer 42. The data input of input buffer 40 is connected to I / O pad 38, and the data output of output buffer 42 is also connected to I / O pad 38. With respect to the first kernel, the output of input buffer 40 is connected to data output conductor 44 of the I / O kernel. The input of the output buffer 42 is connected to the data input conductor 46 of the I / O kernel. Finally, output buffer 42 also includes an enable input conductor 48 and a slew control input conductor 50. 2 shown in the figure
The number of such I / O kernels used in an actual integrated circuit manufactured in accordance with the concepts of the present invention is merely exemplary, and the number of such I / O kernels is a matter of design choice. This is what the traders recognize. Such a person skilled in the art will recognize that this device is more flexible than conventional devices using dedicated I / O modules assigned to a limited area around the integrated circuit die.

An important aspect of the present invention is that the data output conductors 30 and 44 of the input buffers 26 and 40, respectively, the data input conductors 32 and 46 of the output buffers 28 and 42, respectively, and the output buffer of each I / O kernel in the architecture of the present invention. It relates to the characteristics and routing of one or more of the enable through control input conductors 28 and 42. The properties and routing of these lines form a powerful and flexible I / O structure, as detailed below.

The interface between the inputs 14-1 to 14-5 and the outputs 16-1 to 16-3 of the logic function modules 12-1 to 12-8 and the I / O kernel according to this aspect of the present invention is the first
2 showing the vertical details of the array showing the I / O kernel of FIG. 2 and FIG. 3 showing the horizontal details of the array showing the second I / O kernel.

According to a preferred embodiment of the present invention, the data input / output conductors 32, 30, 40, and 44 are easily arranged using user programmable elements. Complete deployment clearly provides maximum connectivity, but also adds capacitive loading. Partial placement of these conductors is desirable to achieve the required circuit characteristics. As can be seen from the discussion of FIG. 1, the enable and slew control input conductors 34 of the output buffers 28 and 42 of each I / O kernel in the architecture of the present invention.
36, 48 and 50 can be connected to Vcc or ground via user programmable interconnect elements. The respective enable input conductors 34 and 48 of the output buffers 28 and 42 are connectable to the logic function modules 12-1 to 12-18 of the array 10, but the respective slew rate control inputs 36 and 50 of the output buffers 28 and 42. Can only be connected to Vcc or ground tracks.

Referring to FIG. 4, another aspect of the present invention is illustrated. This aspect of the invention allows for a collective connection of the output buffers for increased drive according to the invention.

In FIG. 4, two representative logic function modules 12
-1 and 12-2 are shown. Unnecessary details of the architecture have been omitted to facilitate understanding of this aspect of the invention. Logic function modules 12-1 and 12-2
Are three output buffers 12-1a, 12-1b, and 12-1c, respectively.
It is shown to have 12-2a, 12-2b, and 12-2c, respectively. These output buffers drive logic function module output lines 52, 54, 56, 58, 60, and 62, respectively. The parts of the two output kernels are I / O pads 6
It is shown to include output buffers 64 and 66 that drive 8 and 70. With input conductor 72 to output buffers 64 and 66
74 is the logic function module output line 52, 54, 56, 58, 60
Cross 62. Intersections are user programmable interconnect elements 76, 78, 80, 82, 84, 86, 8 indicated by open circles
8, 90, 92, 94, 96, and 98 are fully installed.

The provision of the output buffer input conductors 72 and 74 of the two output buffers in the same area of the integrated circuit that can be programmably connected to one and the same node of one of the logic function modules 12-1 and 12-2 has particular advantages. By connecting the inputs of the two output buffers to the same drive signal, an output having high drive performance can be formed.

As shown in FIG. 4, the user-programmable interconnect elements 80 and 92 are programmed (indicated by solid circles). Thus, the logic function module 12-2's output buffer 12-2b drives the inputs of both output buffers 64 and 66. The user couples I / O pads 68 and 70, resulting in an output node with high drive performance. For example, each output buffer
If 64 and 66 are capable of driving 12 mA, they can be combined to provide a 24 mA output drive.

Also, as shown in FIG. 4, enable input lines 100 and 102 of output buffers 64 and 66 are shown to intersect line 104. User programmable interconnect elements 106 and 108 (indicated by solid circles) are programmed to allow control of output buffers 64 and 66 from a single line 104. One skilled in the art will recognize that the enable signal on line 104 can come from a variety of sources. Line 104 may be a general interconnect line, as well as a special enable line as disclosed herein, one output of an input buffer in an I / O kernel, ground or a fixed voltage such as Vcc. The source of such signals is not part of the present invention, but rather is part of the circuit design imposed on the integrated circuit architecture that is part of the present invention.

FIG. 5 is a more detailed block diagram of a portion of the array 10 as shown in FIG. 1, wherein aspects of the present invention allow the global enable signal to be routed both horizontally and vertically along both the rows and columns of the array. Is shown. FIG. 5 is FIG.
A very similar configuration, with any number of user programmable interconnect elements at the intersection of global enable line 110 and the enable input of any output buffer for which global enable is desired, A "broken" global enable line 110 has been added that can be used to enable the output buffer of the I / O kernel.

Global enable line 110 is shown traversing the periphery of array 10 in both row and column directions. Global enable line 110 is shown traversing both the top and bottom of array 10 in the row direction and traversing the left and right sides of the array in the column direction. Those skilled in the art will recognize that the global enable lines 110 need not occupy all four sides of the array 10 and may occupy two or three sides and are within the scope of the present invention.
Those skilled in the art will also recognize that global enable line 110 need not be located around array 10 as long as the enable input of the buffer is connectable to it. Such a global enable line 10 also serves as an array 10 for clock signal routing, etc.
It can be used for other functions.

Referring again to FIG. 1, another aspect of the invention is that the connection made from the output of the logic function module to the input conductor of the output buffer, even if the input conductor of the output buffer runs in the same direction as the output conductor of the logic function module. Even with a single user programmable interconnect element.

Although the data input conductor 46 of the output buffer 42 runs in the row direction of the array, the output conductors of the logic function modules 12-1 through 12-18 have the same configuration. From the discussion of FIG. 1, it can be seen that branch 112 of data input conductor 46 and branch 114 of enable input conductor 48.
Will extend in the column direction between the logic function modules 12-7 and 12-8, forming their intersection with the output conductors. These intersections are provided using interconnect elements that can be programmed by the user. Similarly, branch 116 of data input conductor 46 and branch 118 of enable input conductor 48 are connected to logic function modules 12-9 and 12-9.
−10 extend in the column direction and form the intersection with their output conductors, and the branch 120 of the data input conductor 46 and the branch 122 of the enable input conductor 48 are
It extends in the column direction between 2-11 and 12-12, forming an intersection with their output conductors. These intersections are also installed using user programmable interconnect elements. Conductors 112, 116 and 120 are hardwired to data input conductor 46 of output buffer 42 and
4, 118 and 122 are hard-wired to the enable input conductor 48 of the output buffer 42 so that there is only one at the intersection of the output of the logic function module and one of the branches 112, 114, 116, 118, 120 and 122. User programmable elements are required to connect the data input and enable input conductors of the output buffer to drive signals from the logic function module.

This same aspect of the invention provides a connection made from the output of the input buffer to the input conductor of the logic function module,
Even though the output conductors of the input buffer run in the same direction as the input conductors of the logic function module, this is possible with a single user programmable interconnect element. The data output conductor 30 of the input buffer 26 is connected between the column containing the logic function modules 12-3, 12-9, and 12-15 and the column containing the logic function modules 12-4, 12-10, 12-16. Run down the array vertically. However, the logic function modules 12-3, 12-4, 12-9, 12-10, 12-1
5 and 12-16 inputs 14-1 through 14-5 are also running vertically.

According to the present invention, the branch line 124 extends in both the left and right directions from the data output conductor 30 of the input buffer 26 and is disconnected, and the five inputs 14-1 to 14 of both logic function modules 12-3 and 12-4 are disconnected.
Crosses with -5. The branch line 126 extends from the data output conductor 30 of the input buffer 26 in both the left and right directions and is disconnected, and the five inputs 14-1 to 5-1 of the logic function modules 12-9 and 12-10 are disconnected.
Crosses 14-5. The branch line 128 extends in both the left and right directions from the data output conductor 30 of the input buffer 26 and is broken, and intersects with the five inputs 14-1 to 14-5 of both logic function modules 12-15 and 12-16. All these intersections can be installed using user-programmable interconnect elements, and thus by programming a single user-programmable interconnect element,
It can be connected to any input of these logic function modules.

As will be appreciated by those skilled in the art, a prior art alternative to this aspect of the invention is to employ a portion of a general interconnect architecture to configure these connections. This alternative requires that the signal pass through the on-resistance of at least two user-programmable interconnect elements, thus reducing the performance of the net formed by the interconnect.

According to another aspect of the invention shown in FIGS. 6a and 6b, the data output conductors and data input conductors associated with the I / O kernel of the architecture of the invention have varying lengths. For example,
Any of these conductors can extend the full length of the row or column of the array, or can be smaller, e.g., a fraction of the length of the row or column of the array, e.g.,
Can be 1/4, 1/3, 1/2, etc. in length, or can be a fixed number of modules (integers from 1 to n, where n is the number of modules in the row or column of the array) is there. Alternatively, the length of each individual one of the input, output, control or enable conductors can be measured by the number of logic function modules in a row or column to which they can be connected by user programmable elements. This variety is well known in the art and indicates the use of dedicated I / O modules provided around the integrated circuit die, or the I / O related conductors penetrating a fixed distance into the area of the array.

This aspect of the present invention seeks to maximize the benefits of using shorter and longer data input / output connector lengths. Longer conductor lengths penetrate deeper into the logic array, providing greater connectivity and allowing more logic function modules to be reached. But,
Long conductor lengths are more expensive than short conductors because they occupy more silicon area. In addition, longer lengths involve more capacitance and can reduce circuit performance. Therefore, careful selection of length is desired as a design choice.

FIG.6a is a block diagram of an array illustrating features of the invention;
The input conductors for different output buffers extend different distances in the array. In the array 130 shown in FIG. 6a, the five rows (or columns) of the array 130 are rectangular 1
32, 134, 136, 138 and 140. One skilled in the art will recognize that the array 130 is similar to the array 10 shown in FIG. 1 and is not needed to avoid complicating the figure and obscuring the inventive features that FIG. 6a intends to show. Detailed description is omitted.

I / O pads 142, 144, 146, 148 and 150 are shown connected to the outputs of output buffers 152, 154, 156, 158 and 160, respectively. Input conductors 162, 164, 166, 168 and 170 provide input data to output buffers 152, 154, 156, 158 and 160, respectively, and extend into array 130.

According to this aspect of the invention, the input conductors 162, 164, 166, 16
8 and 170 extend different distances into the array 130.
That is, the input conductor 162 extends across only one row 132 of the array 130 and through a user-programmable interconnect element (shown as a small circle at the output of the logic function module), The output of module 132-1 is being accessed. The input conductor 164 is
Extending across the two rows 132 and 134 of the array 130;
User programmable interconnect elements (shown as small circles at the output of the logic function module)
, The output of the logic function modules 132-2 and 134-2 is accessed. The input conductor 166 is
Via the user programmable interconnect elements (shown as small circles at the output of the logic function module) extending across the three rows 132, 134 and 136
The outputs of the logic function modules 132-3, 134-3, and 136-3 are being accessed. The input conductor 168 extends across the four rows 132, 134, 136 and 138 of the array 130 and via user programmable interconnect elements (shown as small circles at the output of the logic function module). 132-4,134-4,136-4 and 138
-4 output is being accessed. The input conductor 170 extends across the five rows 132, 134, 136, 138 and 140 of the array 130, and via user-programmable interconnect elements (shown as small circles at the output of the logic function module). 132−5,134−
5,136-5,138-5 and 140-5 are accessed.

FIG. 6b is a block diagram of the same array 130 showing similar features of the invention where the output conductors of different input buffers extend different distances into the array. Same I / O pad 142,144,146,
148 and 150 are shown, in this case connected to the inputs of input buffers 172, 174, 176, 178 and 180, respectively. Output conductors 182, 184, 186, 188 and 190 provide output data from input buffers 172, 174, 176, 178 and 180, respectively, and extend into array 130.

According to this aspect of the invention, the output conductors 182, 184, 186, 18
8 and 190 extend different distances into the array 130.
That is, the output conductors 182 extend across only one row 132 of the array 130 and, via user-programmable interconnect elements (shown as small circles at the output of the logic function module), The output of module 132-1 is being accessed. The output conductor 184
Extending across the two rows 132 and 134 of the array 130;
User programmable interconnect elements (shown as small circles at the output of the logic function module)
, The output of the logic function modules 132-2 and 134-2 is accessed. The output conductor 186 is
Via the user programmable interconnect elements (shown as small circles at the output of the logic function module) extending across the three rows 132, 134 and 136
The outputs of the logic function modules 132-3, 134-3, and 136-3 are being accessed. The output conductor 188 extends across the four rows 132, 134, 136 and 138 of the array 130 and through user programmable interconnect elements (shown as small circles at the output of the logic function module). 132-4,134-4,136-4 and 138
-4 output is being accessed. The output conductor 190 extends across the five rows 132, 134, 136, 138 and 140 of the array 130 and through user-programmable interconnect elements (shown as small circles at the output of the logic function module). 132−5,134−
5,136-5,138-5 and 140-5 are accessed.

The exact distribution of the input conductors 162, 164, 166, 168 and 170 of different lengths and the output conductors 182, 184, 186, 188 and 190 is simply a matter of design choice. Important to the flexibility of the architecture of the present invention is to provide the conductors extending into these arrays with different lengths.

Referring to FIG. 7, a block diagram of the FPGA array 200 is:
Input and output buffers in FPGA architecture
FIG. 3 illustrates features of the present invention that can be connected to a general interconnect that can provide considerable flexibility in allocating I / O. Array 20 of FIG.
0 is similar to the array 10 shown in FIG.

The logic function module array 200 includes the logic function modules 12-1, 12-2, 12-12 in the first row of the array.
-3 and 12-4. The second row of the array contains the logic function modules 12-5, 12-6, 12-7 and 12-8.
And the third row of the array comprises logic function modules 12-9, 12-10, 12-11 and 12-12.

Generic interconnect architecture is a logical function module
Overlaid on an array 200 of 12-1 to 12-12. The two groups of vertical interconnect conductors are indicated by brackets 18. The three groups of horizontal interconnect conductors are in brackets
Indicated by 20. Vertical and horizontal interconnect conductors 18
And 20 groups are each shown as having five such conductors, but those of ordinary skill in the art will appreciate that the number of conductors provided in each group may be primarily a matter of design choice. It will be appreciated that different groups of interconnect conductors may each have a different number of conductors.

Inputs 14-1 to 14-5 of the logic function modules 12-1 to 12-12 (exemplified in the logic function module 12-9)
And (exemplified in logic function module 12-10)
Outputs 16-1 to 16-3 intersect the interconnect conductors in groups 18 and 20. In FIG. 7, the inputs 14-1 to 14-5 of the logic function modules 12-1 to 12-12 are shown as extending vertically downward, and a group of horizontal interconnect conductors is shown.
20 and the logic function modules 12-1 to 12-1.
Although the outputs 16-1 to 16-3 of 12-12 are shown extending horizontally to the left and right and intersect with a group 18 of vertical interconnect conductors, those of ordinary skill in the art will appreciate that It will be appreciated that one can imagine an architecture that is arranged face-to-face, as well as an architecture where both vertically extending inputs and outputs are mixed.

User-programmable interconnect elements, such as 22, for example, are interconnect conductors and logic function modules 12.
At the intersection with the output and input conductors of -1 to 12-12,
It is shown as a hollow circle. Although these intersections are shown quite dense in the exemplary architecture of FIG. 7, less dense architectures are also within the scope of the invention.

According to the embodiment of the present invention shown in FIG.
Is connected to the input of the input buffer 204 and to the output buffer 206
Connected to the output. I / O pad 208 is connected to the input of input buffer 210 and to the output of output buffer 212. The input of the output buffer 206 is connected to the conductor 214, and the input of the output buffer 212 is connected to the conductor 216. The output of the input buffer 204 is connected to a conductor 218 and the output of the output buffer 210 is connected to a conductor 220.

The conductors 214 and 216 extend into the array 200 and are parallel to the upper two groups 20 of universal interconnect conductors and so that they interconnect the logic function module inputs 14-1 to 14-5. It is shown that it extends adjacently.
The conductor 214 intersects the inputs to the logic function modules 12-1 to 12-4, and the conductor 216
Crosses the inputs to 2-5 to 12-8. User programmable interconnect conductors are shown located at these intersections.

Conductors 218 and 220 also intersect the universal interconnect line 20, with conductor 218 intersecting the interconnect lines of the upper group 20 and conductor 220 intersecting the interconnect lines of the central group 20. ing. User programmable interconnect elements are shown as conductors 218 and 220 and the center circle at the intersection of each of the interconnect conductors in group 20 above.

I / O pad 230 is shown at the top of FIG.
It is connected to the output of 232 and to the input of input buffer 234. The input of the output buffer 232 is connected to the conductor 236, and the output of the input buffer 234 is connected to the conductor 238. Conductors 236 and 238 extend vertically down into the array 200 and parallel to the vertical interconnect conductor group 18;
The above logic function modules 12-3, 12-4, 12-7, 12-8, 12-
Forming an intersection with the outputs of 11 and 12-12,
It forms the intersection with each universal interconnect conductor in three groups 20 of horizontal interconnect conductors. The user-programmable interconnect elements include conductors 236 and 238 and the logic function modules 12-3, 12-4, 12- as well as each interconnect conductor of group 20 of horizontal interconnect conductors.
It is shown as a hollow circle at the intersection of the outputs 7,12-8,12-11 and 12-12.

As can be seen from the discussion of FIG. 7, the FPGA architecture in accordance with this aspect of the present invention is highly susceptible because any input or output connection can be routed to or from any of the logic function modules 12-1 to 12-12. It is flexible. Prior art architectures do not allow such connectivity, but instead only provide connectivity to I / O modules in place. The present invention allows for a more useful choice of location and route software for connecting logic function modules to I / O pads, depending on the application of the user. In addition, the fewer programmable connections employed between the I / O pads and the logic function module provide faster input and output signal paths, thus improving the performance of the integrated circuit.

Those of ordinary skill in the art will recognize the I / O described here.
It will be appreciated that the architecture may include other features such as test features, such as, for example, JTAG boundary scan technology or the like, or other logic functions and features.

While embodiments and applications of the invention have been shown and described, it will be obvious to those skilled in the art that many more modifications than those described above are possible without departing from the spirit of the invention. Accordingly, the invention is not to be restricted except in the spirit of the appended claims.

──────────────────────────────────────────────────の Continuation of the front page (72) Inventor Captanoglu, Sinan San Simeon Way, 2810 San Carlos, California 94070 United States (72) Inventor Lean, Yun-Cheung San Jose, CA 95129 United States of America Alcante Drive No. 6062 (72) Inventor Chan, King W. No. 697 Riverside Drive, Los Altos, California 94024, United States No. 697 (72) Inventor El-Ayat, Kard A. United States 95014 Randy Lane, Cupertino, California, USA No. 10174 (56) References JP-A-3-78317 (JP, A) JP-A-6-502523 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 19/177

Claims (33)

(57) [Claims] 1. An architecture for a field programmable gate array arranged in an integrated circuit, comprising: a plurality of logic function modules in an array of rows and columns, each module having at least one input conductor and at least one output conductor. A plurality of input / output pads, a plurality of input / output kernels, each input / output kernel being connected to one of the I / O pads, a data input and an input buffer data. An input buffer having a data output connected to the conductor; and a data input connected to the output buffer data conductor and a data output connected to one of the I / O pads and an enable input connected to the output buffer enable conductor. Wherein the input buffer data conductor has a direction along the row and Extending in a direction that constitutes one of the directions along the column, wherein some of the input buffer data conductors have different lengths compared to the other input buffer data conductors and have a different number of input buffer data conductors. Extending across the row or the column, the input buffer data conductor forms a first intersection with some of the inputs of the module, and the output buffer data conductor and the output buffer enable conductor are connected to the row. Extending in one of the directions along and along the column, some of the output buffer data conductors and output buffer enable conductors are connected to the other output buffer data conductors and output buffer enable conductors. Have different lengths in comparison,
Extending across a different number of the rows or columns, the output buffer data conductors and output buffer enable conductors form a second intersection with some of the outputs of the module; A field programmable gate array architecture comprising user-programmable interconnect elements connected to selected ones of the intersections. 2. The field programmable gate array architecture of claim 1 wherein said user programmable interconnect elements are connected to all of said first intersections. 3. The field programmable gate array architecture of claim 1, wherein said user programmable interconnect elements are connected to all of said second intersections. 4. The field programmable gate array architecture of claim 1, wherein said user programmable interconnect elements are connected to all of said first and second intersections. architecture. 5. The architecture of claim 1, wherein at least two of said output buffer data conductors are connected to at least one common output of said outputs of said module by user programmable interconnect elements. Connectable field programmable gate array architecture. 6. An architecture according to claim 1, wherein said input / output kernel forms a Vcc intersection with a Vcc conductor and an output buffer slew rate control conductor which forms a ground intersection with a ground conductor. And a field programmable gate array architecture wherein user programmable interconnect elements are located at said Vcc intersection and ground intersection. 7. The field programmable gate array architecture of claim 1, wherein a plurality of interconnect conductors, at least some of which are third intersections with some of said input buffer data conductors. And a user-programmable interconnect element connected to selected ones of said third intersections, the field-programmable gate array architecture further comprising: 8. The architecture of claim 1, wherein a plurality of interconnect conductors, at least some of which are third intersections with some of said output buffer data conductors. And a user-programmable interconnect element connected to selected ones of said third intersections, the field-programmable gate array architecture further comprising: 9. The field programmable gate array architecture of claim 1, wherein a plurality of interconnect conductors, at least some of which are third intersections with some of said output buffer enable conductors. And a user-programmable interconnect element connected to selected ones of said third intersections, the field-programmable gate array architecture further comprising: 10. The architecture of a field programmable gate array arranged in an integrated circuit, comprising: a plurality of logic function modules in an array of rows and columns, each module having at least one input conductor and at least one output conductor. A plurality of interconnect conductors, a plurality of input / output pads, a plurality of input / output kernels, each input / output kernel connected to one of the I / O pads. An input buffer having a data input connected thereto and a data output connected to an input buffer data conductor, and a data input connected to an output buffer data conductor and a data output and output connected to the one of the I / O pads. An output buffer having an enable input connected to a buffer enable conductor, said input buffer The data conductor extends by a first length in one of the direction along the row and the direction along the column, and extends between the direction along the row and the direction along the column. Extending in the other direction by a second length, the input buffer data conductors form a first intersection with some of the inputs of the module and some of the interconnect conductors; A first length extends in one of a direction along the row and a direction along the column, and a second length extends in the other direction between the direction along the row and the direction along the column. Wherein the output buffer data conductors form a second intersection with some of the outputs of the module and some of the interconnect conductors, and wherein the first and second intersections Touch selected intersection A different number of said input buffer data conductors having different lengths; and a different number of said output buffer data conductors having different lengths from each other. Programmable gate array architecture. 11. The field programmable gate array architecture of claim 10, wherein at least some of said output buffer enable conductors are in one of a direction along said row and a direction along said column. Extending along a first length and extending a second length in the other direction along the row and along the column, the output buffer enable conductor includes a plurality of outputs of the module. A field-programmable gate array architecture comprising a user-programmable interconnect element forming a third cross-section and connected to a selected one of said third cross-sections. 12. The architecture of the field programmable gate array of claim 10, wherein a plurality of third interconnect conductors, at least some of which are connected to some of said input buffer data conductors and said third interconnect conductor. Field programmable further comprising: a third interconnect conductor forming an intersection of the following; and a user-programmable interconnect element connected to selected ones of the third intersections. Gate array architecture. 13. The field programmable gate array architecture of claim 10, wherein a plurality of third interconnect conductors, at least some of which are connected to some of said output buffer data conductors and said third interconnect conductor. Field programmable further comprising: a third interconnect conductor forming an intersection of the following; and a user-programmable interconnect element connected to selected ones of the third intersections. Gate array architecture. 14. The field programmable gate array architecture of claim 10, wherein a plurality of third interconnect conductors, at least some of which are connected to some of said output buffer enable conductors and said third interconnect conductor. Field programmable further comprising: a third interconnect conductor forming an intersection of the following; and a user-programmable interconnect element connected to selected ones of the third intersections. Gate array architecture. 15. The architecture of a field programmable gate array arranged in an integrated circuit, comprising: a plurality of logic function modules in an array of rows and columns, each module having at least one input conductor and at least one output conductor. A plurality of input / output pads; a plurality of general purpose interconnects forming a first intersection with inputs from some of the logic function modules; A kernel, wherein each input / output kernel is connected to an input buffer having a data input connected to one of the I / O pads and a data output connected to an input buffer data conductor, and an output buffer data conductor. A data input and a data output connected to the one of the I / O pads and an output buffer enable conductor. An output buffer having an enable input connected thereto, wherein the input buffer data conductor extends in a column direction, and some different ones of the input buffer data conductors are different compared to the other input buffer data conductors Having a length, extending across a different number of the rows, forming a second intersection with some of the plurality of general interconnect conductors, wherein the output buffer data conductor and the output buffer enable conductor are A different number of the output buffer data conductors and output buffer enable conductors extending in the column direction have different lengths as compared to the other output buffer data conductors and output buffer enable conductors, and Extending across the row, the output buffer data conductor and the output buffer enable conductor are Forming a third intersection with some of the forces, comprising a user-programmable interconnection element connected to a selected one of the first, second and third intersections; Gate array architecture. 16. The field programmable gate array architecture of claim 15, wherein said user-programmable interconnect element comprises said first element.
The architecture of the field programmable gate array connected to all of the intersections. 17. The field programmable gate array architecture of claim 15, wherein said user-programmable interconnect element comprises said second element.
The architecture of the field programmable gate array connected to all of the intersections. 18. The field programmable gate array architecture of claim 15, wherein said user-programmable interconnect element comprises said third element.
The architecture of the field programmable gate array connected to all of the intersections. 19. An architecture for a field programmable gate array disposed on an integrated circuit, comprising a plurality of logic function modules in an array of rows and columns, each of said plurality of modules having at least one input. A logic function module having a conductor and at least one output conductor; a plurality of input / output pads; and a plurality of universal interconnect conductors forming a first intersection with inputs from some of the logic function modules. An input buffer comprising a plurality of input / output kernels, each input / output kernel having a data input connected to one of the plurality of I / O pads and a data output connected to an input buffer data conductor; and A data input connected to an output buffer data conductor and a data output connected to the one of the plurality of I / O pads. An output buffer having a force and an enable input connected to an output buffer enable conductor, wherein the plurality of input buffer data conductors extend in a row direction;
A different number of the plurality of input buffer data conductors comprises:
Extending across a different number of the columns, having a different length as compared to the other input buffer data conductors, forming a second intersection with some of the plurality of universal interconnect conductors; The plurality of output buffer data conductors and the plurality of output buffer enable conductors extend in a row direction, and different ones of the plurality of output buffer data conductors and the plurality of output buffer enable conductors include other output buffer data conductors and The plurality of output buffer data conductors and the plurality of output buffer enable conductors have different lengths as compared to the output buffer enable conductors and extend across a different number of the columns, the plurality of output buffer enable conductors and the plurality of output buffer enable conductors of the plurality of modules. Forming a third intersection with some of the plurality of outputs, at a selected one of the first, second, and third intersections; Continued been user comprises a plurality of interconnected elements programmable, field programmable gate array architecture. 20. A user-programmable interconnect element connected to all of said first intersections.
20. The architecture of the field programmable gate array according to 19. 21. A user-programmable interconnect element connected to all of said second intersections.
20. The architecture of the field programmable gate array according to 19. 22. A user-programmable interconnect element connected to all of said third intersections.
20. The architecture of the field programmable gate array according to 19. 23. The architecture of a field programmable gate array disposed on an integrated circuit, comprising: a plurality of logic function modules in an array of rows and columns, each of said plurality of modules having at least one input. A logic function module having a conductor and at least one output conductor; a plurality of input / output pads; and a plurality of universal interconnect conductors forming a first intersection with outputs from some of the logic function modules. An input buffer comprising a plurality of input / output kernels, each input / output kernel having a data input connected to one of the plurality of I / O pads and a data output connected to an input buffer data conductor; and A data input connected to an output buffer data conductor and a data output connected to the one of the plurality of I / O pads. An output buffer having a force and an enable input connected to an output buffer enable conductor, wherein the plurality of input buffer data conductors extend in a column direction, and different ones of the plurality of input buffer data conductors are connected to another of the other input buffers. Extending across a different number of said rows, having a different length as compared to the buffer data conductor;
Forming a second intersection with some of the inputs of the plurality of logic function modules; the plurality of output buffer data conductors and the plurality of output buffer enable conductors extending in a column direction; A different number of the plurality of output buffer enable conductors having a different length as compared to the other output buffer data conductors and output buffer enable conductors and extending across a different number of the rows; A plurality of output buffer data conductors form a third intersection with some of the plurality of universal interconnect conductors, and are connected to a selected one of the first, second, and third intersections. Field programmable gate array architecture with multiple user programmable interconnect elements. 24. A user-programmable interconnect element connected to all of said first intersections.
24. The architecture of the field programmable gate array according to 23. 25. A user-programmable interconnect element connected to all of said second intersections.
24. The architecture of the field programmable gate array according to 23. 26. A user-programmable interconnect element connected to all of said third intersections.
24. The architecture of the field programmable gate array according to 23. 27. The architecture of a field programmable gate array located on an integrated circuit, comprising: a plurality of logic function modules in an array of rows and columns, each of said plurality of modules having at least one input. A logic function module having a conductor and at least one output conductor; a plurality of input / output pads; and a plurality of general-purpose interconnect conductors forming a first intersection with one output of the plurality of logic function modules. An input buffer comprising a plurality of input / output kernels, each input / output kernel having a data input connected to one of the plurality of I / O pads and a data output connected to an input buffer data conductor; and A data input connected to the output buffer data conductor and a data output connected to the one of the plurality of I / O pads. An output buffer having a force and an enable input connected to an output buffer enable conductor, wherein the plurality of input data buffer data conductors extend in a row direction, and different ones of the plurality of input buffer data conductors are connected to another one of the other. Having a different length as compared to the input buffer data conductor and extending across a different number of said columns to form a second intersection with some inputs of said plurality of logic function modules; The plurality of output buffer data conductors and the plurality of output buffer enable conductors extend in a row direction, and different ones of the plurality of output buffer data conductors and the plurality of output buffer enable conductors are connected to the other output buffer data conductor and the output. Extending across a different number of said columns, having a different length as compared to the buffer enable conductor The plurality of output buffer data conductors form a third intersection with some of the plurality of universal interconnect conductors and connect to a selected one of the first, second, and third intersections. Field programmable gate array architecture with multiple user-programmable interconnect elements. 28. A user-programmable interconnect element connected to all of said first intersections.
28. The architecture of the field programmable gate array according to 27. 29. A user-programmable interconnect element connected to all of said second intersections.
28. The architecture of the field programmable gate array according to 27. 30. A user-programmable interconnect element connected to all of said third intersections.
28. The architecture of the field programmable gate array according to 27. 31. The architecture of a field programmable gate array disposed on an integrated circuit, comprising: a plurality of logic function modules in an array of rows and columns, each of said plurality of modules having at least one input. A logic function module having a conductor and at least one output conductor, comprising a plurality of I / O pads, comprising a plurality of I / O kernels, each I / O kernel being one of the plurality of I / O pads. An input buffer having a data input connected to the input buffer and a data output connected to the input buffer data conductor; and a data input connected to the output buffer data conductor and connected to the one of the plurality of I / O pads. An output buffer having a data output and an enable input connected to an output buffer enable conductor. The input buffer data conductors extend in a direction that constitutes one of a direction along the row and a direction along the column, and some of the input buffer data conductors include other ones of the input buffer data conductors. Extending across the different rows or columns with different lengths as compared to the input buffer data conductors, wherein the input buffer data conductors have a first intersection with some of the inputs of the plurality of logic function modules. Wherein the output buffer data conductors extend in a direction that constitutes one of a direction along the row and a direction along the column, and some of the output buffer data conductors include the output buffer. The output buffer data conductor has a different length as compared to some of the other data conductors and extends across the different rows or columns, and the output buffer data conductor comprises A plurality of user-programmable interconnects forming a second intersection with one of the outputs of the functional module and connected to a selected one of the first and second intersections A global enable conductor extending in both the direction along the row and the direction along the column, the global enable conductor forming a third intersection with at least some of the output buffer enable conductors. A field programmable gate array architecture comprising a plurality of user programmable interconnect elements connected to at least some of said third intersections. 32. The global enable conductor is located substantially near the periphery of the array and has one section extending in the row direction and one section extending in the column direction.
32. The architecture of the field programmable gate array of claim 31, forming one partition. 33. The global enable conductor is positioned substantially near an outer periphery of the array, forming at least one section extending in a row direction and at least one section extending in a column direction. 32. The architecture of the field programmable gate array of claim 31.