JP3285611B2 - Dynamic semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (hereinafter simply referred to as "DRAM"), and more particularly to a DRAM that automatically executes a refresh operation.

[0002]

2. Description of the Related Art Conventionally, dynamic semiconductor memory devices (DRAMs) having a built-in self-refresh function have been known and have been widely used in many fields.
As shown in FIG. 19, the circuit configuration of such a known DRAM includes, as shown in FIG. 19, at least an externally input address information (A1 to A11) input stage EAD, a row address strobe RAS (bar) as a control signal, and a column. An input means 1 comprising an input stage IN to which an address strobe CAS (bar) is inputted; a column control means 2 comprising a column related control circuit 21, a column related address buffer 22 and a column decoder 23; System control circuit 41
, A row-system control means 4 comprising a row-system address buffer 42 and a row decoder 43, a sense amplifier 5, and a matrix memory cell 3. Further, each of the matrix memory cells provided in the matrix memory cell 3 is provided. And refresh means 8 for refreshing the information stored in.

[0003] The refresh means 8 includes, for example,
An oscillating circuit (OSC) 81 for generating a clock signal based on a refresh operation, a refresh control circuit 82 to which the oscillating circuit 81 and the input means 1 are connected, and an output of the refresh control circuit 82 The output is the row address buffer 4 of the row control means 4.
Refresh address counter 8 connected to 2
3.

The output of the refresh control circuit 82 is simultaneously output to the row control circuit 4 of the row control means 4.
It is connected to one. In the DRAM provided with the conventional refresh function, when the self-refresh operation starts, the oscillating means (oscillator) 81
A predetermined time interval by clock φ0 from
For example, the refresh operation is performed in 16 microseconds (16 μs).

In the above example, a 16 Mbit DRA
M, and the cell configuration of the matrix memory cell 5 of the DRAM is, for example, 4096 × 4096.
With such a configuration, 4096 memory cells arranged along one word line or one bit line can be simultaneously refreshed in one refresh operation.

Here, an example of a refresh operation of the matrix memory cell 3 in a conventional dynamic semiconductor memory device will be described with reference to FIG.
First, in a normal operation of writing or reading information to or from the matrix memory cell in the dynamic semiconductor memory device, the matrix memory cell 3 is accessed by a command from an appropriate computer or the like.

For example, as shown in FIG. 20, if the information included in the external address EAD is such that the row address RA and the column address CA are alternately arranged as shown in FIG. 20 (B) and 20 (C) of the row address strobe RAS (bar) and column address strobe CAS (bar) input to the input means 1
As shown in FIG.
(Bar) first changes from the “H” level to the “L” level, and under the control of the row-related control circuit 41, the information of the external address EAD is transmitted to the row-related address buffer 42, and a predetermined row, ie, , One corresponding bit line is selected, and then the column address strobe CAS
When (bar) changes from “H” level to “L” level, the information of the external address EAD is stored in the column address buffer 22 under the control of the column control circuit 21.
And a specific column, that is, one corresponding word line is selected and a specific memory cell is selected, so that a predetermined information write or read operation is performed on the memory cell.

However, each memory cell constituting such a matrix memory cell is, for example, shown in FIG.
The MOS type transistor Q1 arranged at the intersection of the word line WL and the bit line BL has one node N1 having a predetermined capacitance C.
It is connected to the 1 / 2Vcc through one inevitably formed as P-N connected to the semi-conductor layers (junction) section
Engaging Ru portion is Ri equivalent der the general diode D1,
The charge stored in the capacitor C1 connected to the transistor Q1 flows out through the diode D1,
There is a problem that the charging voltage of the node portion N1 decreases.

For this reason, conventionally, the same information as the information held by each cell is periodically written into each cell of the matrix memory cell 3 so that the storage information of the matrix memory cell 3 is written. It needs to be refreshed. Therefore, in the related art, the refresh operation is constantly and repeatedly executed while a command is issued from a predetermined computer that the matrix memory cell 3 does not need to be accessed. Has become.

For example, in the conventional refresh operation illustrated in FIG. 22, all the memory cells included in one bit line BL are sequentially refreshed sequentially for each bit line. However, as shown, during a period when the computer does not request access to the matrix memory cell 3, the column address strobe CAS (bar) is set to the row address based on a predetermined control signal. If the row address strobe RAS (bar) changes from "H" level to "L" level after changing from "H" level to "L" level prior to the strobe RAS (bar) and the state occurs, Is recognized as the timing at which the refresh operation is executed, and the row address strobe RAS (bar) is From the time of change in L "level" level "H, after a predetermined period of time predetermined,
For example, after a lapse of 100 μs, the self-refresh operation is started.

When the self-refresh operation starts, the reference clock φ0 output from the oscillation means 81 causes
The refresh control circuit 82 is operated to transmit a predetermined control signal to the row-related control circuit 41, and at the same time, the word line W to be refreshed by the row-related address buffer 42 via the refresh address counter 83.
L are sequentially selected one by one, and information corresponding to the information stored in all of the memory cells of the selected one word line WL is stored in an external address E.
From the AD, the data is fetched into the sense amplifier 5 via the column decoder 23, and each piece of information is written into each memory cell of the word line WL selected from the sense amplifier 5, and the refresh operation is completed.

When a predetermined refresh operation is completed for one word line WL, the refresh address counter 83 selects an adjacent word line WL and performs the same refresh operation as described above. In the conventional refresh operation of a dynamic semiconductor memory device, for example, in the case of the row address buffer described above, if the refresh time of one matrix memory cell is set to 64 ms, one word line or one bit line is set. The arranged 4096 cells have a size of 16 μm.
A refresh operation is performed every s (64 ms ÷ 4096 = 16 μs).

When the refresh operation is sequentially performed on all the word lines WL of the matrix memory cell 3, for example, 4096 word lines WL, the refresh address counter 83 again starts the refresh address counter 83. And the same refresh operation is repeated thereafter. FIG. 25 illustrates the configuration of a specific example of the refresh address counter 83 used in the conventional dynamic semiconductor memory device.

That is, assuming that the number of word lines WL of the matrix memory cell is 4096,
In order to specify the address of each word line WL, 12
Flip-flops (FF-0 to FF-11) are arranged in series, and from the Q output of each flip-flop,
The configuration is such that address signals RFA0 to RFA11 are respectively output.

The refresh operation is repeated until the computer issues a command to access the matrix memory cell 3 again. However, each of the memory cells in the conventional matrix memory cell 3 has a problem that the charge held in the cell leaks from the PN-junction portion formed in the semiconductor layer, and the charge leaks. The speed varies with temperature, manufacturing variations, PN-junction area, charging voltage, and the like.

In particular, such a leak is particularly affected by the temperature of the dynamic semiconductor memory device, and as shown in a graph X of FIG. 23, a time required for a refresh operation in the memory cell is required. The interval is
The higher the temperature, the shorter. That is, assuming that the time interval required for refreshing when the temperature of a certain memory cell is 0 ° C. is 1, the time interval required for refreshing when the temperature reaches 100 ° C. is expressed in logarithmic 0. It becomes 1.

That is, in each of the matrix memory cells in the dynamic semiconductor memory device, the higher the temperature is, the larger the leakage is. Therefore, it is necessary to shorten the time interval of the refresh operation for the cell. There is. On the other hand, the graph Y in FIG.
1 shows the oscillation frequency of the clock, that is, the cycle time corresponding to the change in temperature. However, when the temperature rises compared to when the temperature is 0 ° C., the oscillation of the oscillation circuit 81 is increased. As the frequency increases and the temperature rises, the time interval of the refresh operation must be shortened, whereas the clock interval becomes longer, so that in the past, it was impossible to execute an accurate refresh operation. It was impossible.

In FIG. 19, which is a diagram of a conventional example, an example of an oscillator used as the oscillating means 81 in the refresh means 8 is shown in FIG. That is, the oscillating means shown in FIG. 24 is, as described above, in the refresh operation in the conventional DRAM, the refresh time is strongly affected by the temperature. When the temperature rises, the refresh time becomes shorter, while the oscillation cycle (oscillator cycle) of the oscillation circuit
Is configured to detect the leak current at the PN junction and generate a refresh clock for the cell, in order to improve such a drawback because the temperature becomes slow as the temperature rises.

That is, as is apparent from FIG. 24, one end is connected to a predetermined power supply Vp, and the other end (node N2) of the transistor Q2 whose gate is supplied with the signal φp indicating the refresh cycle is connected to the power supply 1/2 Vcc. the same time to connect to the other end of the capacitor C2 of which one end portion is connected, one end is set to the substrate potential V _BB, PN junction (diode D
2), the other end (node N2) of the transistor Q2 is input to one input terminal of the comparing means C, and a reference voltage ( Vp−ΔVp), and an output corresponding to the difference is obtained by comparing the output of the comparing means C with the changed oscillation frequency φR
Is output as

However, in the oscillator having such a configuration, for example, it is necessary to obtain a clock which is 1/4096 of the refresh time of the matrix memory cell. Obtaining a one-half clock was difficult. In addition, the PN junction has a large variation in leakage, and therefore requires a plurality of circuits, which has the disadvantage of increasing the area of one chip and increasing power consumption.

[0021]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned disadvantages of the prior art, and to increase the area of the chip and the power consumption without incurring the influence of temperature. A dynamic semiconductor memory device capable of performing a refresh operation is provided.

[0022]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, at least an information input means, a column decoder, a row decoder, and a matrix memory cell, and a sense amplifier connected to a bit line pair of the matrix memory cell and the sense amplifier connected to the bit line pair of the matrix memory cell. At least one refresh check cell array connected to an amplifier and added to a word line of the matrix memory cell in parallel for adjusting a refresh time; and information stored in the matrix memory cell and the refresh check cell array. Means for refreshing the refresh check cell array and determining whether or not the information held in all the memory cells of the refresh check cell array at the time of refreshing the refresh check cell array is normal information. Refresh check means, a further dynamic semiconductor memory device comprising.

[0023]

In the dynamic semiconductor memory device (DRAM) according to the present invention, since the above-mentioned technical configuration is employed, the refresh check cell array is added to the matrix memory cell to thereby provide the dynamic memory device. in the semiconductor memory device, the refresh operation result of each of the memory cells, and by determine the word line WL direction of the matrix memory cells, it is determined whether the refresh operation is appropriate, it is determined that there is appropriate In such a case, the refresh time interval in the refresh operation is not changed or adjusted so as to be longer, and if it is determined that the refresh time interval is not appropriate, the refresh time interval in the refresh operation is shortened. It is necessary to increase the chip area and power consumption. Without incurring large, be natural, not affected by temperature, it is possible to provide a dynamic semiconductor memory device which can perform accurate serifs refresh operation.

Further, in the dynamic semiconductor memory device according to the present invention, it is not necessary to generate, for example, a 1/4096 clock, so that the circuit configuration is simplified.
It can be easily manufactured.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a DRAM according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram for explaining a configuration of a specific example of a dynamic semiconductor memory device according to the present invention. In FIG. 1, at least an externally input address information (A1 to A11) input stage EAD and a row address as a control signal are shown. Input stage I to which strobe RAS (bar) and column address strobe CAS (bar) are input
N, input means 1 composed of N and column control circuit 21
And column address buffer 22 and column decoder 2
3; a row control means 4 including a row control circuit 41; a row address buffer 42; and a row decoder 43; a sense amplifier 5; Further, in the dynamic semiconductor memory device comprising refresh means 8 for refreshing information stored in each of the matrix memory cells provided in the matrix memory cell 3, the refresh time is further adjusted. A dynamic semiconductor memory device is shown in which at least one refresh check cell array 6 is added in parallel to either the word line or the bit line of the matrix memory cell 3 for performing the operation.

That is, in the dynamic semiconductor memory device according to the present invention, when each memory cell in the matrix memory cell 3 is refreshed,
In order to solve the conventional problem and efficiently execute the adjustment of the refresh time by the temperature change, the refresh check cell array 6 is provided separately from the matrix memory cell 3.
The refresh check cell array is preferably arranged adjacent to the matrix memory cell.

That is, in the present invention, the refresh check cell array 6 composed of memory cells having the same configuration as the plurality of memory cells constituting the matrix memory cell 3 is adjacent to the matrix memory cell 3. The refresh check cell array 6 is refreshed in accordance with the timing at which the matrix memory cells 3 are refreshed, and the result is determined by a method described later to determine whether the refresh operation has been performed normally. Is detected, and when it is determined to be normal, the time interval of the refresh operation,
In other words, the generation period of the refresh clock is extended or not changed. Conversely, when it is determined that the refresh operation is abnormal, the time interval of the refresh operation, that is, the generation period of the refresh clock is used. The adjustment operation is performed so as to shorten.

In other words, the present invention provides a matrix memory cell 3 comprising a very large number of memory cells.
The result of the refresh of each cell is determined as a representative of some memory cell groups having the same cell configuration, and the refresh operation for all the memory cells is adjusted. Therefore, in the present invention, for example, the refresh check cell array 6 is configured so as to be in parallel with either the word line or the bit line of the matrix memory cell 3 and to configure either the word line or the bit line. It is preferable that the above determination and adjustment operation be performed using a check cell group composed of the same number of memory cells as the number of memory cells to be checked.

The dynamic semiconductor memory device according to the present invention and the basic operation of the refresh operation in the device will be described in detail with reference to FIG. FIG.
Is basically the same as the configuration of the conventional dynamic semiconductor memory device shown in FIG. 19, and the operation thereof is basically the same as that described with reference to FIG.

[0030] Therefore, in the said dynamic semiconductor memory device according to the present invention, when only explained differences in configuration between the conventional dynamic semiconductor memory device of FIG. 19, is at 1, as mentioned above, As an example, outside of the matrix memory cell 3, adjacent to the matrix memory cell 3 and in parallel with the word line WL of the matrix memory cell, a memory cell forming one word line WL of the matrix memory cell 3 are those refresh check cell array 6 having a number of identical number is provided, the refresh read-write for writing and reading predetermined information in each memory cell of Mata該 refresh check cell array 6, then the predetermined information Means 7, and the refresh read
The write means 7 is used for the refresh check cell array 6
Is provided with a refresh check means 9 for judging the refresh state of the refresh check cell array 6 based on the result of reading the information contained in the row information. A new row decoder 43 that allows the address of the refresh check cell array 6 to be specified to the decoder 43
# 1 is provided, and the row decoder 43
In order to designate # 1, the counter in the refresh address counter 83 in the refresh means 8 is increased by one so that, for example, the 4096 + 1st address can be designated.

The refresh operation of the dynamic semiconductor memory device according to the present invention will now be described. The refresh operation of the dynamic semiconductor memory device according to the present invention is basically performed in FIG. The operation is substantially the same as the operation described in the conventional example. Therefore, the refresh operation for each memory cell of the matrix memory cell 3 is not different from the conventional operation.
When the refresh operation is started, the first word line WL # of the matrix memory cell 3 according to the clock generated from the clock generating means 81 at a period of 16 μs.
Each word line WL from 1 to word line WL # 4096 is sequentially selected, and predetermined information is written from an external address to each memory cell of the selected word line WL via the sense amplifier 5.

The refresh operation is performed in the fortieth cycle.
When the word line WL reaches the 96th word line, the refresh address counter 83 of the refresh unit 8 next counts up to 40.
The 96th + 1-th address is designated, and the row address corresponding to the refresh check cell array 6 selects the row address decoder 43 # 1 via the row address buffer. Therefore, the refresh check cell array 6 is selected as a refresh target. Is done.

In the present invention, the information 1, that is, the "H" level is applied to all the memory cells of the refresh check cell array 6 via the sense amplifier 5 in advance. When the refresh check cell array 6 is selected by the refresh operation and written and placed, whether all the memory cells of the refresh check cell array 6 are 1 or not,
Alternatively, the refresh check means 9 determines whether or not the information of at least one memory cell has been changed to 0, and after executing the determination, the selected refresh check cell array 6 includes Through the sense amplifier 5, the refresh check cell array 6
Is written and stored in all the memory cells.

With such a configuration, the refresh check cell array 6 is refreshed at predetermined intervals, and at the same time, it is determined whether or not refreshing is normally performed. That is, in the present invention,
At least refresh is performed at the same cycle as each memory cell in the matrix memory cell 3 of the dynamic semiconductor memory device, and information is changed to 0 in each memory cell in the refresh check cell array 6. In the case where there is a memory cell that is not present, it is determined that the required refresh time is short in all the memory cells of the matrix memory cell 3 and the time interval at which the refresh operation is performed, That is, the refresh control circuit is adjusted so as to shorten the refresh operation cycle.

In other words, in the present invention, the memory cells included in the matrix memory cell 3 vary in the magnitude of leakage current, leakage time, etc. due to variations in the manufacturing process and the like. Since it is impossible to manufacture the matrix memory cell 3 in the refresh check cell array 6 because it is impossible to manufacture the matrix memory cell 3
This is to be represented as a refresh result of a memory cell in the inside.

Therefore, when the information of all the memory cells in the refresh check cell array 6 is all 1, it is determined that the refresh operation of all the memory cells in the matrix memory cell 3 is normal. In this case, however, the refresh operation cycle may not be changed, or the refresh operation cycle may be made longer than the previous cycle, and the cycle may be lengthened.

On the other hand, when the information of at least one of the memory cells in the refresh check cell array 6 is 0, the information may be increased due to, for example, a rise in temperature or a decrease in charging voltage. Since the leak current from the memory cell of the matrix memory cell 3 has increased or the charge charge has decreased, it is determined that the information of 1 has changed to 0, and the time interval of the refresh operation, that is, the cycle, is shortened. It is adjusted in such a way.

In the present invention, the memory cells constituting the refresh check cell array 6 are arranged so that the time required for refreshing the matrix memory cells can be accurately and promptly determined. Is preferably configured to be shorter than the time required for refreshing in each cell constituting. As a method of realizing such a configuration, for example, the capacity of each cell configuring the refresh check cell array 6 is determined as follows.
This can be realized by setting the capacity to be smaller than the capacity of each cell constituting the matrix memory cell. More specifically, for example, the capacity of each cell constituting the refresh check cell array 6 is set to It is possible to set such that the capacity of each cell constituting the matrix memory cell 3 is １ ／.

Further, in the present invention, for example, the charging voltage for each cell constituting the refresh check cell array is set to be higher than the charging voltage for each cell constituting the matrix memory cell. Alternatively, the size of the PN junction area in each cell constituting the refresh check cell array may be set to be larger than the PN junction area in each cell constituting the matrix memory cell. It may be.

In the present invention, the threshold value of each cell constituting the refresh check cell array is set to be higher than the threshold value of each cell constituting the matrix memory cell. You may. next,
A method of changing and adjusting the refresh operation interval based on the output result of the refresh check means 9 according to the present invention will be described.

That is, in the present invention, the refresh time adjusting means 10 for changing the refresh time for the matrix memory cell 3 in response to the output of the refresh check means 9 is provided. . The refresh time adjustment means 10, by the refresh check means 9, at least one of the information contained in all cells of the refresh check cell array 6, if it is determined not to be normal information, the re-off < br /> Oh intended to be operated so as to shorten the interval of the threshold time
Ri also by the refresh check means 9, all of the information contained in all cells of the refresh check cell array 6, if it is determined to be normal, or not change the spacing of the fresh time, or It is operated to make it longer.

For this reason, the refresh time adjusting means 10 according to the present invention generates, for example, different voltage values in accordance with the output of the refresh check means 9, and generates the different voltage values from the oscillation circuit 81 based on the voltage signal. For example, it may be configured to drive a set circuit of a binary counter that modulates a clock signal having a predetermined cycle.

FIG. 2 shows an example of a specific configuration of the refresh time adjusting means 10. FIG. 2 shows a specific example of the refresh time adjusting means 10 used in the present invention. The counter receives the output of the refresh check means 9 as an input and changes the set count value of a binary counter 102 described later. The oscillation signal of the set circuit 101 and the oscillator 81 which is the oscillation circuit is received at the input,
A binary counter 102 having a function of changing the frequency of the oscillation signal of the oscillator 81 based on the set count value set by the counter set circuit 101
And is composed of

The output of the binary counter 102 is
It is connected to the input of the refresh control circuit 82.
In the refresh time adjusting means 10, in the refresh check means 9, when all the memory cells of the refresh check cell array 6 are information of 1, in the counter set circuit 101,
In order not to change the refresh operation cycle used in the previous refresh operation, to keep the counter value of the counter set circuit 101 the same as the previous counter value, or to slightly lengthen the refresh operation cycle,
For example, it is set to an appropriate value of 0.9 or less.

The refresh check cell array 6
When at least one of the memory cells has changed to information of 0, the counter set circuit 101 sets the refresh operation cycle used in the previous refresh operation so as to shorten the refresh operation cycle. The counter value of the counter set circuit 101 is changed and set to an appropriate value such as 1.5 or 2.0.

When the counter value of the counter set circuit 101 is changed, the binary counter 102 changes the oscillation frequency input from the oscillator 81 and outputs it to the refresh control circuit 82. Based on such an operation, the refresh control circuit 82
, The refresh address counter 83 is driven based on the refresh clock φR output from the device, so that the cycle of the refresh operation is changed.

FIG. 3 is a diagram for explaining an example of the configuration of the refresh address counter 83 used in the above embodiment according to the present invention. The basic configuration and its operation are shown in FIG. Although it is substantially the same as the refresh address counter 83 in the conventional dynamic semiconductor memory device, the present invention is different from the first embodiment in that one flip-flop FF12 for setting the address of the refresh check cell array 6 is provided. When the refresh check cell array 6 is selected by the output of the flip-flop FF-12, the refresh address counter 83 is reset, and the refresh operation is restarted from the word line WL # 1 again. Is configured. FIG. 4 shows an example of the configuration of the sense amplifier 5, matrix memory cell 3, refresh check cell array 6, and refresh read / write means 7 in the dynamic semiconductor memory device according to the present invention, and the relationship between them. FIG.

The memory cells forming the refresh check cell array 6 and the memory cells forming the matrix memory cell 3 may have the same configuration as shown in FIG. Is composed of four MOSFET transistors Q12 to Q15 having a wiring structure as shown in FIG. 4, and the refresh read / write means 7 has a source connected to Vcc and a drain connected to a bit. Line BL
Side, and the gate is an input line φ for writing.
MOSFET transistor Q1 connected to RCW
6, the source is connected to the BL (bar) side of the bit line,
And a drain connected to Vss and a gate connected to the input line φRCW for writing.
The SFET transistor Q17, the gate is connected to the BL (bar) side of the bit line, the drain side is connected to the read line φRF, and the source is connected to the connection node between the transistors Q13 and Q15 in the sense amplifier. And a MOSFET transistor Q18.

In such a configuration, when the refresh read / write means 7 reads information of a plurality of memory cells constituting the refresh check cell array 6, the memory cell has one information. In this case, BL (bar) of the bit line is 0, and the transistor Q18 is turned off. Therefore, the potential of the read line φRF previously set to “H” level is maintained at “H” level. Is done.

However, if even one of the memory cells in the refresh check cell array 6 has information of 0, the transistor Q18 is turned on because the bit line BL is 1. Therefore, the potential of read line φRF preset to “H” level is
Since the level changes to the “L” level, it is possible to determine the change timing of the refresh operation cycle.

Next, in the above configuration, when writing 1 information to all the memory cells of the refresh check cell array 6, the write input line φR
When CW is changed to “H” level, the input line φR
The transistor Q16 connected to the CW is turned on, and the voltage of Vcc is applied to the memory cell of the refresh check cell array from the source of the transistor Q16, so that information 1 is written to the memory cell.

While such an operation is being performed, the transistor Q17 is also turned on, so that a current flows from the bit line BL (bar) to the drain of the transistor Q17, and the potential of the bit line BL (bar) is changed. Is held at the “L” level. In the specific example of the dynamic semiconductor memory device according to the present invention described above, each of the memory cells forming the refresh check cell array 6 is replaced with each of the memory cells forming the matrix memory cell 3 by refreshing. Although an example in which the operation request cycle is configured to be short has been described, changing the refresh characteristics for each of the memory cells may be complicated in the process of manufacturing the semiconductor device. It is also possible to set the period of the refresh check operation for the refresh check cell array 6 longer than the period of the refresh operation for the memory cells of the matrix memory cell so as to detect a change in stored information due to a leak as soon as possible. is there.
As an example, instead of performing the refresh operation and the refresh check operation of the refresh check cell array 6 for each refresh operation to the matrix memory cell 3, one refresh operation to the matrix memory cell 3 is performed once. The refresh operation and the refresh check operation are performed.

[0053] That is, specifically, constitutes a refresh operation and a refresh check operation of the refresh check cell array 6 in each execution twice refresh operation on the matrix memory cell 3 in one row cormorants like. More specifically, this is realized by driving flip-flop F-12 after repeating flip-flops FF-0 to FF-11 twice in refresh address counter 83 shown in FIG. It is possible to do.

FIG. 5 illustrates a practical example of the operation of the above specific example according to the present invention. At time t1, the refresh check cell array word line RCWL in which the refresh check cell array 6 is arranged is selected. ,
During the time t1 ', the refresh means performs the above-described refresh check and determination operations to set an appropriate refresh operation cycle.

In this specific example, the refresh operation cycle is set to 32 μs, and the word line W
The refresh operation in L0000 is performed between time t1 ′ and time t2. Then, in the refresh operation cycle, each of the 4096 word lines WL is refreshed, and at time t3, the refresh operation of the 4096th word line WL4095 is completed, the refresh check cell array word line RCWL is selected again, and until time t4. Between the refresh check cell array 6 and the refresh check as described above;
By executing the determination operation, an appropriate refresh operation cycle is set again.

In this specific example, since it has been determined that none of the information of each memory cell of the refresh check cell array 6 has changed, the subsequent refresh operation cycle is set to 48 μs and the previous refresh operation cycle. Each operation described above is repeated with the setting made slightly longer than the above. Next, a second example of the present invention will be described in detail with reference to the drawings.

That is, in the first specific example described above,
According to the determination of the refresh check means for the refresh check cell array 6, only two types of information for determining whether to shorten the refresh operation cycle and not to change or increase the refresh operation cycle can be obtained. On the other hand, the second specific example is configured to positively obtain third information for obtaining a conclusion that the refresh operation cycle is not changed.

That is, as a configuration of the second specific example, the refresh check cell array 6 is divided into at least two sets and the refresh read / write means 7 is provided.
The refresh check means 9 is also configured to be divided into at least two systems so as to read, write, and determine information of each refresh check cell array 6.

That is, in this specific example, the refresh check cell array 6, the refresh read / write means 7 and the refresh check means 9 are divided into a plurality of independent refresh check systems, each of which is individually described above. A similar refresh check is performed, and the obtained information is comprehensively determined, and a determination is made as to whether the refresh operation cycle should be shortened, lengthened, or not changed. .

The number of divisions of the refresh check cell array 6, the refresh read / write means 7 and the refresh check means 9 in this embodiment is not particularly limited, but is at least two. In the above embodiment of the present invention, the refresh operation required time intervals of the memory cells constituting the divided refresh check cell arrays 61, 62,... Must be different from each other. The refresh operation required time intervals of the memory cells forming the refresh check cell arrays 61, 62,... Naturally satisfy the relationship set with the memory cells forming the matrix memory cells 3 as described above. Needless to say, this is a premise.

If the above premise is satisfied,
In this specific example, for example, the required refresh operation time interval of the memory cells forming the refresh check cell array 61 is set to be smaller than the required refresh operation time interval of other refresh check cell arrays, for example, the memory cells forming the refresh check cell array 62. Is desirably configured to be longer.

In order to realize such a configuration, as described in the first specific example, the configuration relationship between the memory cells is changed by, for example, a method of giving a change in the capacity, a change in the charging voltage for each cell. PN in each cell constituting the refresh check cell array.
This can be achieved by changing the size of the junction area or the threshold value.

FIG. 6 is a diagram showing an example of the structure of the second embodiment of the present invention. Most of the structure is the first embodiment of the present invention shown in FIG. Although the configuration is the same as that of the example and their detailed description is omitted, the difference from FIG. 1 is that the refresh check cell array 6 is divided into two, and the refresh check cell arrays 61 and 62 are provided. Accordingly, the refresh read / write means 7 also performs refresh read / write means 71 and 72.
The refresh check means 9 is also divided into refresh check means 91 and 92, each of which forms an independent refresh control system.

In this specific example, the division ratio of the refresh check cell array 6 is not particularly limited, and can be set to an arbitrary ratio. In the case of FIG. An example in which the data is divided into / 2 is shown. In this specific example, the configuration of each memory cell constituting the refresh check cell array 61 is set such that the required time interval of the refresh operation of the refresh check cell array 61 is longer than the required time interval of the refresh operation of the refresh check cell array 62. It is necessary to make the configuration of each memory cell constituting the refresh check cell array 62 different.

As a specific example, for example, the capacity of each memory cell forming the refresh check cell array 61 is set to の of the capacity of the memory cell forming the matrix memory cell 3, and the refresh check cell array 62 is formed. The capacity of each memory cell is set to １ ／ of the capacity of each memory cell forming the refresh check cell array 61, that is, １ ／ of the capacity of the memory cell forming the matrix memory cell 3.

The refresh operation of each of the refresh check cell arrays 61 and 62 and the method of judging the result in this embodiment are the same as those of the first embodiment described above. The refresh check means 91 and 92 are stored in the refresh check means 91 and 92, respectively, and the determination means 93 newly provided based on the respective information performs the following determination processing, for example.

FIG. 7 shows a reference example for executing the above-mentioned judgment processing in this specific example. Specifically, the contents are shown in an appropriate look-up table in the refresh check means. Is stored in the refresh check means 91 and 92 at a predetermined timing, and is compared with the refresh determination result. A predetermined control signal is sent from the determination means 93 to the refresh time adjustment means 1.
Output to 0.

That is, the refresh check means 91,
In response to the output of 92, it is determined whether to make the refresh operation cycle for the matrix memory cell 3 slower, faster, or not changed with respect to the previous refresh operation cycle. It is composed. That is, in FIG. 7, the refresh check cell array 61 having a relatively large memory cell capacity is used.
FIG. 9 shows a combination of the determination results of the refresh check means 91 and 92 after the refresh operation by the (first system) and the refresh check cell array 62 (second system) having a relatively small memory cell capacity.
If both the system and the second system are PASS, that is, if the information of each memory cell in the refresh check cell array is all 1 (hereinafter referred to as Case 1), the first
When only the system is PASS and the second system is FAIL, that is, when at least one information of the memory cell in the refresh check cell array is changed (hereinafter referred to as Case 2), both systems are FAIL (hereinafter referred to as FAIL). Case 3) is assumed, and in Case 1 the temperature may be falling, for example. Therefore, in this case, the refresh operation cycle is lengthened (slower). To do) is possible.

In case 2, for example, there is a case where there is no change in temperature. Therefore, in this case, it is determined that the refresh operation cycle does not need to be changed. Further, in case 3, for example, a case where the temperature is rising may be considered. Therefore, in this case, it is necessary to shorten (fasten) the refresh operation cycle.

That is, in this specific example, for example, the result of the refresh operation determination of the refresh check cell array 62, which is the second system using small-capacity memory cells, may be FAIL early, and the first system refresh If the check cell array 61 is PASS, it is assumed that the refresh operation of the memory cell of the matrix memory cell 3 is normally performed.

FIGS. 8 and 9 are views for explaining a third specific example according to the present invention. As described above, in the present invention, the cycle in the oscillator circuit such as the oscillator must always be shorter than the required time interval for the refresh operation normally required by the memory cell, and to a certain extent. You need to have room. Therefore, in the first specific example described above, for example, the capacity of the memory cell is realized by reducing the capacity of the memory cell of the matrix memory cell. However, for example, the capacity of the memory cell is reduced to half. In order to reduce the size, the memory cell array of the refresh check cell array 6 preferably has the same structure as a normal memory cell in terms of layout. Therefore, the purpose is achieved by doubling the thickness of the capacitance insulating film. I can.

However, in order to increase the thickness of the insulating film, it is necessary to form the insulating film itself twice.
There is a problem that manufacturing costs increase. In order to solve this problem, in this specific example, the memory cells forming the refresh check cell array 6 are made to have the same configuration as the memory cells forming the matrix memory cells 3 and, instead, the refresh check The refresh operation cycle of the cell array 6 is set to be an integral multiple of the refresh operation cycle for the matrix memory cell 3, for example, two times, three times, or four times.

That is, the matrix memory cell 3
One refresh operation and one refresh check operation are executed in response to a plurality of refresh operations for. That is, specifically, every time the refresh operation for the matrix memory cell 3 is performed twice, the refresh operation of the refresh check cell array 6 and the refresh check operation are performed once.

FIG. 8 shows an example of a specific configuration of a dynamic semiconductor memory device for realizing the above-mentioned third specific example, which is basically the same as FIG. Is added to the refresh address counter 83 such that a flip-flop FF-12 outputs a 1 from the flip-flop FF-12 only after the flip-flops FF-0 to FF-11 have turned n times, for example, twice.

Therefore, the refresh operation cycle of the refresh check cell array 6 is set to be n times longer than the refresh operation cycle of the matrix memory cell 3. FIG. 9 is a diagram for explaining a configuration example of the refresh address counter 83 in the specific example of FIG. 8. The basic configuration is the same as that of FIG. 3, but the output of the flip-flop FF-11 is two times. On the other hand, flip-flops FF-12 and FF-12 are output so that an address for selecting the refresh check cell array 6 is output once.
-13 is added in series.

That is, in this specific example, for example, executing one refresh operation of the refresh check cell array 6 for two refresh operations of the matrix memory cell 3 means that the memory cells of the refresh check cell array 6 Has the same effect as when the capacity of the memory cell of the matrix memory cell 3 is reduced to half of that of the matrix memory cell 3, the operation by software becomes possible as compared with the above specific example, so that the production cost does not increase. .

Next, a fourth embodiment according to the present invention will be described with reference to FIG.
This will be described with reference to FIG. This specific example corresponds to the third
The determination of the change of the refresh operation cycle in the specific example of
In contrast to the configuration in which only two types of information for determining whether to shorten the refresh operation cycle and not to change or lengthen the refresh operation cycle can be obtained, in the fourth specific example, In addition, the third information is configured to positively obtain the conclusion that the refresh operation cycle is not changed.

That is, in the configuration of the fourth embodiment, the refresh operation cycle of the refresh check cell array 6 in the third embodiment is longer than the refresh operation cycle of the memory cells in the matrix memory cell 3. The condition for increasing the refresh operation cycle is limited to one type.
In this specific example, a plurality of types of changes in the refresh operation cycle are set, and based on the conclusion of the refresh check means under each condition, each of the changes obtained in the same manner as the second specific example is obtained. The information is comprehensively determined, and a determination is made as to whether the refresh operation cycle should be shortened, lengthened, or not changed.

That is, to exemplify a specific case, the refresh operation for the memory cells forming the matrix memory cell 3 is repeated twice, and then the refresh operation is performed for the refresh check cell array 6. The result of the judgment is stored in the first storage means 95 provided in the refresh check means 9, and the same refresh operation is repeated four more times on the matrix memory cell. It is stored in the second storage means 96 provided in the means 9.

That is, in this specific example, the memo refresh operation for the matrix memory cell 3 is alternately repeated twice and four times, and the judgment result of the refresh check means 95 and 96 in each step is repeated. Therefore, based on the criterion as shown in FIG. 12, the refresh check means 9 has a selection circuit for selecting whether to lengthen or shorten the refresh operation cycle or to keep the tears unchanged. Will be executed.

In the present embodiment, therefore, after the refresh operation for the matrix memory cell 3 is performed six times, the change of the refresh operation cycle is adjusted. Of course, in this specific example, the refresh operation is alternately performed twice and four times.
It is needless to say that this is merely an example and other combinations can be adopted.

FIG. 10 shows an example of the configuration of an apparatus for executing the above-described fourth specific example, which is basically the same as the configuration of FIG. , Refresh check means 95 and 96 incorporating storage means, and refresh check means 95 and 96
A determination circuit 97 for determining the change adjustment of the refresh operation cycle based on the above information is provided.

The refresh address counter 83 is configured to output a signal φRC ′ indicating which of the refresh check means 95 and 96 is to be selected.
FIG. 11 shows an example of the configuration of the refresh address counter 83. The difference from FIG. 9 is that a flip-flop FF-14 is further added. An alternative circuit 11 for selecting one of the repetitive operations is provided.

That is, the alternative circuit 11 outputs the output from the flip-flop FF13 output when the refresh operation is repeated twice and the return operation when the refresh operation is repeated four times. When the output from the flip-flop FF14 to be output is input, and when the output from the flip-flop FF13 is selected, the determination information of the refresh operation result at that time is stored in the refresh check means 95,
When the output from the flip-flop FF14 is selected, the determination information of the refresh operation result at that time is stored in the refresh check means 96.

When one of the outputs is selected by the alternative circuit 11, the flip-flops FF-0 to FF-11 of the refresh address counter 83 are set to A.
It is configured to be reset by the output of the ND gate circuit. FIG. 12 shows information serving as a criterion for changing and adjusting the refresh operation cycle in this specific example. Such contents are stored in an appropriate look-up table in the determining means 97, At each timing, it is compared with the refresh judgment result stored in the refresh check means 95 and 96, and a predetermined control signal is output from the judgment means 97 of the refresh check means 9 to the refresh time adjusting means 10.

That is, in this specific example, the capacity of the memory cells constituting the refresh check cell array 6 is increased by increasing the refresh operation cycle so that the capacity of the memory cells of the matrix memory cells 3 is increased. The same effect as that obtained by setting the capacity to be small and different from each other can be obtained as in the second specific example.
This can be realized without changing the structure of each memory cell.

Therefore, the method of comparing the refresh operation determination results for each refresh operation count in FIG. 12 is substantially the same as the method described with reference to FIG.
That is, FIG. 12 shows a combination of the determination results of the refresh check means 95 and 96 when the refresh operation is executed twice and when the refresh operation is executed four times, and both are PASS, that is, All information of each memory cell in the refresh check cell array is 1
(Hereinafter referred to as Case 4), only the former is P
ASS, the latter being FAIL, that is, at least one of the memory cells in the refresh check cell array.
When two pieces of information have changed (hereinafter referred to as case 5)
And both are FAIL (hereinafter referred to as Case 6) 3
In this case 4, the temperature may be falling, for example. Therefore, in this case, it is possible to lengthen (slow down) the refresh operation cycle. .

In case 5, for example, there is a case where there is no change in temperature. Therefore, in this case, it is determined that the refresh operation cycle does not need to be changed. Further, in case 6, for example, a case in which the temperature is rising may be considered. Therefore, in this case, it is necessary to shorten (fasten) the refresh operation cycle.

FIGS. 13 and 14 show a fifth specific example according to the present invention. In each of the above-described specific examples, when the self-refresh operation is started, it is unknown what value should be set for the initial refresh operation cycle, that is, the refresh time interval. That is, at this stage, the check for the refresh operation by the refresh check cell array 6 has not been executed at all.

Therefore, in the present embodiment, in order to solve the problem, when the refresh operation is started for the first time, the refresh operation cycle can be adopted in the dynamic semiconductor memory device. The refresh operation cycle having the shortest value in the cycle is adopted. In order to realize such an operation, in this specific example, the RAS (bar) signal and the CAS (bar)
A circuit 12 for detecting that the refresh operation has started for the first time using a signal and a minimum refresh operation cycle selection circuit 13 are used, and the specific configuration is shown in FIG.

FIG. 13 has a basic configuration substantially similar to that of FIG. 1, except that the self-refresh start detection circuit 12 and the minimum refresh operation cycle selection circuit 13 as described above are added. is there. The relationship among the self-refresh start detection circuit 12, the minimum refresh operation cycle selection circuit 13, the refresh time adjusting means 10, and the oscillation circuit 81 will be described in detail with reference to FIG.

That is, the self-refresh start detection circuit 1
2 detects that the dynamic semiconductor memory device has entered a self-refresh operation from the waveform relationship between the RAS (bar) signal and the CAS (bar) signal as shown in FIG. The minimum refresh operation cycle selection circuit 13 is input to the minimum refresh operation cycle selection circuit 13, and based on the signal, the minimum refresh operation cycle selection circuit 13 stores, for example, the dynamic semiconductor stored in a lookup table or the like which is a predetermined storage unit. From the plurality of refresh operation cycles that can be adopted by the memory device, one having the condition of the shortest refresh operation cycle is selected, and its command information is input to the above-described count value setting circuit 101, and the count set by the above is set. The binary counter 102 operates based on the value, and the clock oscillated from the oscillation circuit 81. It will be changed adjusting the period of the signal.

Next, a sixth example of the dynamic semiconductor memory device according to the present invention will be described. In each of the above-described embodiments, the refresh check cell array 6 provided separately from the matrix memory cell 3 is used to tick the required time interval of the refresh operation and perform necessary changes and adjustments. The basic technology is to detect and determine a change in stored information in a memory cell of a cell array.

However, the required time interval of the refresh operation is determined by the leak of the PN junction in the memory cell. Therefore, the required time interval of the refresh operation of each memory cell constituting the refresh check cell array 6 is not always required. It is not necessarily shorter than the memory cell of the matrix memory cell. Therefore, in this specific example, the refresh check cell array 6 is intended to be formed in the matrix memory cell 3 without being separated from the matrix memory cell 3.

That is, in this specific example, the word line WL having the shortest leak time is selected from the group of bit lines BL or word lines WL in the matrix memory cell 3 and the bit line BL is selected. BL or the word line WL is to be used as the refresh check cell array 6. In other words, when the word lines WL are used in this specific example, if the number of word lines WL and bit lines BL of the regular matrix memory cell 3 is 4096 × 4096, for example, The number of WLs is increased by one to make a configuration of 4097 × 4096, and a characteristic test is sequentially performed on the word line WL group, and the refresh operation required time interval is the shortest, that is, the leak is the most. The word line WL is used as the refresh check cell array 6, and another word line WL is used as the word line WL of the matrix memory cell 3.

That is, in the case of this specific example, the concept of the conventional redundant circuit is used. In order to realize such a method, in this specific example, at the same time as providing a refresh tick address circuit 15 for storing the address of the word line WL used as the refresh check cell array 6 in the matrix memory cell 3, The row decoder 43 incorporates an address switching circuit.

FIG. 15 shows a configuration example of this specific example. The basic configuration is the same as that of FIG. 1, except that the number of word lines WL of the matrix memory cell 3 is increased by one. It is a book, and the refresh tick address circuit 15 is connected to the row decoder 43, and the row decoder 43 has a built-in address switching circuit.

Therefore, the row decoder 43 has a conventional circuit and an address switching function, and switches to the 4097th address when the address of the refresh tick address is selected in normal access. It has a configuration. When the refresh tick is performed, the address stored in the refresh tick address storage circuit is selected.

Next, a seventh example of the dynamic semiconductor memory device according to the present invention will be described. In the refresh operation in the dynamic semiconductor memory device according to the present invention, the normal cells, that is, the memory cells of the matrix memory cell 3 and the refresh check cell array 6 are used.
Since the refresh time of the memory cell is not always the same, it is necessary to adjust the refresh time.

Therefore, in the case of the third specific example described above, an example of a method of setting the refresh operation cycle of the refresh check cell array 6 to twice the refresh operation cycle of the memory cells of the matrix memory cell is as follows. Also, in the case of the fourth specific example, an example of a method of making the refresh operation cycle of the refresh check cell array 6 twice and four times the refresh operation cycle of the memory cells of the matrix memory cells is shown. The refresh operation time of the memory cell in the matrix memory cell needs to be set to a time that is refreshed with a sufficient margin more than the refresh operation time of the refresh check cell array.

Therefore, how many times the refresh operation time of the matrix memory cell is set to the refresh operation time of the refresh check cell array depends on the memory cells constituting each matrix memory cell. It is preferable that the adjustment of time is flexible. Therefore, in this specific example, the circuit configuration of the refresh address counter 83 is changed so that the time adjustment can be freely set.

That is, as shown in FIG. 16, in this specific example, instead of the alternative circuit 11 of the refresh address counter 83 shown in FIG. , And information (RQ12, RQ12) corresponding to the refresh time arbitrarily set from the refresh time storage circuit 86.
13, RQ14, RQ15,) and the flip-flop F
A comparison circuit 85 compares the outputs Q12, Q13, Q14 and Q15 from F-12, FF-13, FF-14 and FF-15.
And the information corresponding to the refresh time (RQ
12, RQ13, RQ14, RQ15,) when a flip-flop output that coincides with a flip-flop output occurs.

That is, in the example of FIG. 16, the refresh operation cycle of the matrix memory cell 3 is set to one of the refresh operation cycle of the refresh check cell array 6.
It is possible to change the length up to double or 16 times.
FIG. 17 shows a specific example in which FIG. 16 is further improved. In the configuration of FIG.
Can be changed only by an integer multiple of 1 or 16 times the refresh operation cycle of the refresh check cell array 6, but according to the circuit of FIG. It is possible to set the operation cycle.

For this purpose, the configuration of the refresh address counter 83 shown in FIG. 17 includes a comparison circuit 85 'and a refresh time storage circuit 86' as in FIG. Circuit 8
6 ′, information (RQ1 to RQ15) corresponding to an arbitrarily set refresh time and the flip-flop F
Outputs Q1 to Q15 from each of F-0 to FF-15
Are compared by a comparison circuit 85, and when a flip-flop output coincident with the information corresponding to the refresh time is generated, the refresh operation is started.

FIG. 18 is a diagram for explaining an eighth specific example according to the present invention. In this embodiment, the word line W of the matrix memory cell 3 is used in each of the above embodiments.
A refresh check cell array 6 is provided in parallel with L,
Although the refresh operation cycle of the refresh check cell array 6 is determined by adjusting the refresh operation cycle, the refresh check cell array 6 is provided in parallel with the bit line BL direction in this specific example.

In this specific example, as shown in FIG.
The bit line BL of the matrix memory cell is set to 4097.
And the word lines WL are composed of 4096 lines, and the bit lines B
The first (BL-1) of L is used as the refresh check cell array 6. As can be seen from FIG. 18, in this specific example, the refresh read / write means 7
Need only read and write information from and to bit line BL # 1 and need not be provided for all bit lines BL.

However, sense amplifier 5 needs to be increased by the amount corresponding to bit line BL # 1. In this specific example, a refresh cycle check circuit 20 for checking a change in information of the bit line BL # 1 is provided. The operation of the present specific example will be described with reference to FIG. 18. When the dynamic semiconductor memory device starts a refresh operation, the bit line BL # 1 serving as the refresh check cell array 6 The memory cells of the matrix memory cell 3 are connected to the word lines W in the order of word lines WL.
L409 to 409 arranged in the direction of the bit line BL in each word line WL of the word lines WL4096.
The six memory cells are simultaneously refreshed. When the refresh operation of each word line WL is performed, the bit line BL # 1, for example, the first or 4097
It is checked whether or not the information of each memory cell on the bit line BL has changed.

In this specific example, the bit line B
Each of the memory cells constituting L-1 is supplied from the refresh address counter 7 via the sense amplifier 5 to the memory cell.
This operation is similar to the operation of writing 1 information to all the memory cells of the refresh check cell array 6 in the specific example described above.

When the refresh operation is completed for 4096 word lines WL with respect to the word lines WL of the matrix memory cell 3, the bit line BL is
It is checked whether or not there is a change in one information stored in each memory cell at -1. Such a check operation is performed every time each refresh operation is completed once in the matrix memory cell 3.

In response to the output signal of the refresh cycle check circuit 20, the refresh check means 9 performs the following in the refresh operation cycle.
If there is no change in the information of all memory cells, PASS
Is generated, and a FAIL signal is generated when there is a change in information even in one of the memory cells.

The meanings of the PASS and FAIL signals correspond to those shown in FIG.
Are the same as the criteria shown in FIG. Therefore, PAS
When the S signal is output from the refresh check means 9, the signal is input to the refresh time adjusting means 10 and the refresh operation cycle is lengthened or shortened in accordance with the same operation as described in the specific example. , Or one of the adjustment operations not to be changed.

[0112]

Since the dynamic semiconductor memory device according to the present invention has the above-described structure, it does not cause an increase in chip area and power consumption, and is not affected by temperature. A dynamic semiconductor memory device capable of performing a refresh operation can be obtained.

In the dynamic semiconductor memory device according to the present invention, the production cost does not increase.
Naturally, it is possible to accurately and easily set the optimum refresh operation cycle according to the characteristics of the matrix memory cell used, so that a dynamic semiconductor memory device capable of performing a refresh operation without economical malfunction is provided. You can get it.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first specific example of a dynamic semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing a configuration of a specific example of a refresh time adjusting unit used in the dynamic semiconductor memory device according to the present invention.

FIG. 3 is a diagram illustrating a specific example of a refresh address counter used in the dynamic semiconductor memory device according to the present invention.

FIG. 4 is a refresh read / write means used in the dynamic semiconductor memory device according to the present invention;
FIG. 3 is a diagram schematically illustrating a configuration of a sense amplifier, a matrix memory cell, and a refresh check cell array.

FIG. 5 is a diagram for explaining the timing of a refresh operation in the present invention.

FIG. 6 is a block diagram showing a configuration of a second specific example of the dynamic semiconductor memory device according to the present invention.

FIG. 7 is a diagram for explaining a criterion of a refresh check unit according to the present invention;

FIG. 8 is a block diagram showing a configuration of a third specific example of the dynamic semiconductor memory device according to the present invention.

FIG. 9 is a diagram showing a configuration example of a refresh address counter used in a third specific example according to the present invention.

FIG. 10 is a block diagram showing a configuration of a fourth specific example of the dynamic semiconductor memory device according to the present invention.

FIG. 11 is a diagram showing a configuration example of a refresh address counter used in a fourth specific example according to the present invention.

FIG. 12 is a diagram illustrating a criterion of a refresh check unit used in a fourth specific example of the present invention.

FIG. 13 is a diagram showing a configuration example of a refresh address counter used in a fifth specific example according to the present invention.

FIG. 14 is a diagram showing a configuration of a specific example of an arrangement configuration of a refresh time adjusting unit and a minimum refresh time storage circuit used in a fifth specific example according to the present invention;

FIG. 15 is a block diagram illustrating a configuration of a sixth specific example of the dynamic semiconductor memory device according to the present invention.

FIG. 16 is a diagram showing a configuration example of a refresh address counter used in a sixth specific example according to the present invention.

FIG. 17 is a diagram showing another configuration example of the refresh address counter used in the sixth specific example according to the present invention.

FIG. 18 is a block diagram showing the configuration of a seventh specific example of the dynamic semiconductor memory device according to the present invention.

FIG. 19 is a block diagram illustrating a configuration for performing a refresh operation of a conventional dynamic semiconductor memory device.

FIG. 20 is a timing chart illustrating a normal operation of a conventional matrix memory cell.

FIG. 21 is a diagram illustrating an example of a configuration of a memory cell used for a matrix memory cell of a conventional dynamic semiconductor memory device.

FIG. 22 is a diagram illustrating a timing at which a refresh operation of a conventional dynamic semiconductor memory device is started.

FIG. 23 is a diagram for explaining a problem in performing a conventional refresh operation of a dynamic semiconductor memory device.

FIG. 24 is a diagram illustrating a configuration example of an oscillation circuit used in a conventional dynamic semiconductor memory device.

FIG. 25 is a diagram illustrating a configuration example of a refresh address counter used in a conventional dynamic semiconductor memory device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 input means 2 column control means 3 matrix memory cell 4 row control means 5 sense amplifier 6 refresh check cell array 7 refresh read / write means 8 refresh means 9 refresh check means 10 refresh time Adjusting means 11 Alternative circuit 12 Self-refresh start detection circuit 13 Minimum refresh operation cycle storage circuit 15 Refresh refresh address storage circuit 20 Refresh cycle check circuit 21 Column control circuit 22 Column address buffer 23 ... Column decoder 41 Row control circuit 42 Row address buffer 43 Row decoder 81 Oscillator 82 Refresh control circuit 83 Refresh address counter 85 Comparison circuit 86 Riff Resh time storage circuits 93, 97: discriminating circuit 101: counter set circuit 102: binary counter

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-121196 (JP, A) JP-A-63-121197 (JP, A) JP-A-3-242895 (JP, A) JP-A 61-121 50287 (JP, A) JP-A-60-212896 (JP, A) JP-A-1-241096 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/406

Claims (21)

(57) [Claims] 1. A sense amplifier comprising at least information input means, a column decoder, a row decoder, and a matrix memory cell, connected to a bit line pair of the matrix memory cell, and via a bit line pair of the matrix memory cell. At least one refresh check cell array connected to the sense amplifier and added in parallel to a word line of the matrix memory cell for adjusting a refresh time; and stored in the matrix memory cell and the refresh check cell array. Refresh means for refreshing information stored therein, and whether or not information held in all memory cells of the refresh check cell array at the time of refreshing the refresh check cell array is normal information Dynamic semiconductor memory device characterized by further comprising a refresh check means for determining. 2. The dynamic semiconductor memory device according to claim 1, wherein said refresh check cell array is arranged adjacent to said matrix memory cell. 3. The refresh check cell array according to claim 2, wherein the number of cells in the refresh check cell array is equal to the number of cells in one array arranged along a word line in the matrix memory cells. 1 or 2
3. The dynamic semiconductor memory device according to claim 1. 4. The refresh check cell array, wherein each cell included in the refresh check cell array has a time required for refreshing the refresh check cell array is shorter than a time required for refreshing each cell constituting the matrix memory cell. 3. The dynamic semiconductor memory device according to claim 1, wherein the dynamic semiconductor memory device is configured to be shorter. 5. The dynamic memory according to claim 4, wherein the capacity of each cell constituting said refresh check cell array is set to be smaller than the capacity of each cell constituting said matrix memory cell. Semiconductor memory device. 6. The refresh check cell array according to claim 4, wherein a charging voltage for each cell constituting said refresh check cell array is set to be higher than a charging voltage for each cell constituting said matrix memory cell. Dynamic semiconductor memory device. 7. The size of the PN junction area of each cell constituting the refresh check cell array is determined by the value of P
5. The dynamic semiconductor memory device according to claim 4, wherein the area is set to be larger than the N junction area. 8. The method according to claim 1, wherein a threshold value of each cell constituting the refresh check cell array is set higher than a threshold value of each cell constituting the matrix memory cell. The dynamic semiconductor memory device according to claim 4, wherein 9. A refresh read / write means for writing predetermined check information to all cells of said refresh check cell array and for reading predetermined check information written to all cells of said refresh check cell array. The dynamic semiconductor memory device according to claim 1, wherein: 10. A refresh time adjusting means for changing a refresh time for said matrix memory cell in response to an output of said refresh check means is provided. 2. The dynamic semiconductor memory device according to claim 1. 11. The refresh time adjusting means, when the refresh check means determines that at least one of information included in all cells of the refresh check cell array is not normal information,
11. The dynamic semiconductor memory device according to claim 10, wherein the operation is performed so as to shorten the refresh time interval. 12. The refresh time adjusting means, if the refresh check means determines that all the information contained in all cells of the refresh check cell array is normal, the refresh time interval 11. The dynamic semiconductor memory device according to claim 10, wherein the operation is performed so as not to change or to increase the length. 13. The refresh check cell array is divided into at least two sets, and the refresh read / write means and the refresh check means also read and write information of each refresh check cell array and determine at least two sets. 10. The dynamic semiconductor memory device according to claim 9, wherein the dynamic semiconductor memory device is divided into systems. 14. The cells included in the first set of the refresh check cell arrays in the refresh check cell array each have a time required for refreshing the cells included in the second set of the refresh check cell arrays. 14. The dynamic semiconductor memory device according to claim 13, wherein the time is longer than a time required for refreshing in each cell. 15. The cells included in the first set of refresh check cell arrays in the refresh check cell array have at least a smaller capacity than the cells included in the second set of refresh check cell arrays. 15. The dynamic semiconductor memory device according to claim 14, wherein the dynamic semiconductor memory device has one of the following relationships: a low charging voltage; a low threshold; or a small PN junction area. 16. The refresh check cell array in the refresh check cell array, wherein a cell capacity of a first set of refresh check cell arrays is set to one half of a capacity of a capacity component constituting the matrix memory cell. 16. The dynamic semiconductor memory device according to claim 15, wherein a cell capacity of said refresh check cell array is set to one fourth of a capacity of a capacity component forming said matrix memory cell. 17. The refresh time adjusting means, in response to an output of the refresh check means, makes the refresh time for the matrix memory cell slower, faster, or changes with respect to the previous refresh time. 14. The dynamic semiconductor memory device according to claim 13, wherein the determination is made as to whether or not to perform the determination. 18. The method according to claim 1, wherein the refresh time interval for the refresh check cell array is set longer than a time for refreshing a cell array of each word line constituting the matrix memory cell. Item 10. The dynamic semiconductor memory device according to item 1. 19. The refresh check cell array according to claim 18, wherein the refresh time interval for the refresh check cell array is set to at least twice a time for refreshing a cell array of each word line constituting the matrix memory cell. A dynamic semiconductor memory device according to claim 1. 20. The apparatus according to claim 1, wherein the refresh interval when the first refresh operation is performed is operated using the shortest refresh interval among the settable refresh intervals. Any one
Item 10. The dynamic semiconductor memory device according to item 1. 21. The dynamic semiconductor memory device according to claim 20, further comprising a storage circuit for storing said shortest refresh interval.