JP3283732B2 - Scanning antenna device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to scanning control of the combined directional direction of two antenna elements arranged at a distance, and the number of scanning steps is kept constant even when the reception frequency changes. And a scanning antenna device.

[0002]

2. Description of the Related Art As an antenna of a radio receiver or the like mounted on a moving body such as a car, the direction of the antenna changes as the direction of the moving body changes. An omnidirectional one with little change is generally used. However, in the case of a drastic change in the reception state such as a fading phenomenon or a change in the direction of radio wave reflection by a building, a single antenna cannot maintain a sufficiently good reception state. Therefore, a diversity technique in which a plurality of antenna elements are arranged on a moving body to detect an antenna element in an optimal reception state and use the detected antenna element as an antenna is being widely used.

[0003]

In the above-mentioned diversity technique, a plurality of antenna elements are installed, but only a signal received by any one of the selected antenna elements is used. Therefore, signals received by other antenna elements are not used.

[0004] Therefore, the present inventors combine the output signals of the two antenna elements with an appropriate delay time difference and set the combined directional direction appropriately so that the combined directional direction as an array antenna can be adjusted to the reception frequency. I came up with the idea that the signal could be received well in the incoming direction of the signal. In addition, since a combined signal obtained by combining the output signals of the two antenna elements is output, there is a high possibility that the electric field strength becomes larger than the output signal of the single antenna element.

To obtain a predetermined combined directional direction, the output signals of the two antenna elements may be combined with a predetermined phase difference. However, in order to obtain the phase difference, the output signals of the antenna elements should be given. The delay time differs depending on the reception frequency. This is because the wavelength time differs depending on the reception frequency, and the delay time for obtaining a predetermined phase difference differs. Here, for example, if it is assumed that television signals in the VHF and UHF bands are to be received,
93.5 MHz of channel 1 to 7 of channel 62
The range is wide up to 67.5 MHz, and the time of one wavelength of the reception frequency of channel 1 and channel 62 has a difference of about 8: 1. Therefore, if the delay time of the delay means is changed so as to obtain the desired phase difference in channel 1 with the delay time change width in which the desired phase difference is obtained in channel 62, the steps required until the desired phase difference is obtained And the time required for rotationally scanning control of the combined directional direction is long.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a scanning antenna apparatus in which the number of steps for performing rotational scanning control of the combined directional direction is the same regardless of the reception frequency. Aim.

[0007]

In order to achieve the above object, a scanning antenna apparatus according to the present invention comprises two antenna elements arranged at a distance and a delay time between output signals from these antenna elements. Respectively, first and second delay means for combining the output signals, combining means for combining the delayed output signals, and the antenna based on the phase difference between the delayed output signals of the antenna elements combined by the combining means. Phase control means for controlling the delay time of the first and second delay means so as to scan the combined directional direction of the element, wherein each of the first and second delay means is formed by a plurality of delay circuits. In addition, all the delay circuits forming the first and second delay means are set to different delay times from each other, and the phase control means has a storage means, The digital data according to the delay time set in the first and second delay means with respect to the frequency to be received is stored in the memory so that the number of scanning steps in the directional direction is the same at each frequency to be received. The digital data is stored in advance in the means, and the digital data is read out at each scanning step in accordance with the frequency to be received, and the first and second delay means are controlled.

Then, the digital data is supplied to the delay circuit as parallel data from the phase control means, and the delay circuit is controlled to an operation state and a non-operation state by data of each line of the digital data. You may.

Further, the number of scanning steps is four,
The two output signals are in-phase and 90 degrees, 180 degrees and 2
In order to control the first and second delay means so as to be sequentially combined by the combining means with a phase difference of 70 degrees, the digital data may be stored in the phase control means in advance.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block circuit diagram of a receiver using one embodiment of the scanning antenna device of the present invention, and FIG. 2 is a more detailed block circuit diagram showing a configuration example of the delay unit in FIG. FIG. 3 is a diagram specifically showing a circuit configuration of the delay unit shown in FIG.
Shows a combined directional pattern when the reception frequency is 90 MHz, (a) shows the result of combining the output signals of the two antenna elements in phase, and (b) shows the result of combining the signals with a phase difference of 90 degrees. (C) is a signal synthesized with a phase difference of 180 degrees, (d) is a signal synthesized with a phase difference of 270 degrees, and FIG.
(A) is a result of combining the output signals of the two antenna elements in the same phase, (b) is a phase difference of 90 degrees, and (c) is a phase difference of 180 degrees. , (D) are synthesized with a phase difference of 270 degrees, FIG. 6 shows a synthesized directional pattern when the reception frequency is 770 MHz, (a) is in-phase, and (b)
Is a phase difference of 90 degrees, (c) is a phase difference of 180 degrees, (d)
FIG. 7 shows frequency-attenuation characteristics of the first delay means connected to the first antenna element shown in FIGS. 1 and 2, and FIG. 8 shows a case where all delay circuits are set to through, FIG. 8 (b) shows a case where delay time is given to all delay circuits, and FIG. 8 is connected to the second antenna element shown in FIGS. 7A shows the frequency versus attenuation characteristics of the second delay means, wherein FIG. 7A shows the case where all delay circuits are made through, and FIG. 7B shows the case where delay times are given to all delay circuits.

First, the structure of the scanning antenna device of the present invention will be described with reference to FIG. For example, on the roof of a car,
Two broadband omnidirectional monopole antennas capable of receiving VHF and UHF bands are disposed as first and second antenna elements 10 and 12 at a distance of about 1 to 1.5 m. Then, the output signal of the first antenna element 10 is amplified by the first amplifier 14, and further given an appropriate delay time by the first delay means 16, and
Given to. Further, the output signal of the second antenna element 12 is amplified by the second amplifier 20 and further given an appropriate delay time by the second delay means 22 so that the combining means 1
8 given. The synthesizing means 18 synthesizes a signal having two predetermined phase differences and supplies the synthesized signal to the television tuner 24. The tuner controller 26 to which the channel select signal is applied converts the channel data into channel data and applies the channel data to the television tuner 24, and the television tuner 24 extracts a reception frequency signal of a desired channel from the combined signal supplied from the combining unit 18. The video signal is output as a video / audio signal, and the video display and the sound amplification are performed by a television receiver (not shown). The channel data is serial data, which is supplied to the data conversion circuit 28, converted into parallel data, and supplied to the phase control means 30.

By the way, the output signals of the first and second antenna elements 10 and 12 are supplied to the first and second delay means 1.
6 and 22, an appropriate delay time is given, and the two signals are combined by the combining means 18 with an appropriate phase difference.
The combined directional direction of the first and second antenna elements 10 and 12 is determined. Therefore, the first and second delay means 1
By appropriately switching and controlling the delay times 6 and 22, the combined directional direction can be rotationally scanned. here,
If the combined directional directions of the first and second delay means 16 and 22 are rotationally controlled by the output data from the phase control means 30, the electric field strength of the reception frequency signal in the television tuner 24 changes. Then, an IF signal or the like corresponding to the electric field intensity of the received frequency signal is provided from the television tuner 24 to the detecting means 32, and the first signal having the maximum electric field intensity is provided.
And the combined directional direction of the second antenna elements 10 and 12 are detected. The detecting means 32 can use a diver selection circuit of a conventional diversity receiver. Detection data from the detection means 32 is supplied to a decoder 34.
And converted into appropriate data, and
0 is given. The phase control unit 30 is supplied with a vertical synchronization signal appropriately extracted from a video / audio signal output from the television tuner 24.

Output data is supplied from the phase control means 30 to the first and second delay means 16 and 22, for example, as 7-bit parallel data. The detection means 32 supplies the detection data to the decoder 34 as, for example, 4-bit parallel data.

The phase control means 30 includes, for example, first and second
In order to set the combined directional directions of the antenna elements 10 and 12 to four directions equally divided around the horizontal, data of Table 1 as described later is stored in the storage means in advance.
And the delay times of the second delay means 16 and 22 are set so that, for example, the two signals are combined with the same phase, a phase difference of 90 degrees, a phase difference of 180 degrees, and a phase difference of 270 degrees. Then, the operation of rotating scanning in the combined directional direction to detect the maximum electric field intensity is performed within a vertical flyback period based on a vertical synchronization signal.

Next, the structure of the first and second delay means 16 and 22 will be described with reference to FIG. The first delay means 16 connected to the first antenna element 10
, Third, fifth, and seventh delay circuits 16-1, 16-3, 1
6-5, 16-7 are connected in series, and a delay correction circuit 40 (which is schematically provided for easy understanding of the description) is connected in series, and the synthesizer 18 of the synthesis means 18 is connected.
-1. Also, the second antenna element 1
The second delay means 22 connected to the second delay circuit 22 is connected to the synthesizer 18-1 by connecting the second, fourth, and sixth delay circuits 22-2, 22-4, 22-6 in series. . This synthesizer 18
The output of -1 is impedance-converted by the matching unit 18-2 and output as a combined signal.

Further, parallel data as output data obtained by converting the channel data from the phase control means 30 is supplied to the first to seventh delay circuits 16-1, 16-3, 16-.
5, 16-7, 22-2, 22-4, and 22-6, but the signal is not supplied to the delay circuit of the first delay means 16 and the inverter 42 is supplied to the delay circuit of the second delay means 22.
Signals are inverted and provided via -1, 42-2, and 42-3.

Here, for the sake of simplicity, the operation of the delay circuit is such that when "1" is given, a predetermined delay time is given to the passing signal, and when "0" is given, the passing signal is given. It is assumed that there is no delay after passing through as it is. Then, the phase control means 30 outputs all “0” as output data.
Is output, the delay circuit of the first delay means 16 does not cause a delay, and the delay circuit of the second delay means 22 causes a delay time. The delay correction circuit 40 has a delay time corresponding to the total delay time of the delay circuit of the second delay means 22. That is, if the output data is all "0", the first delay means 16 does not cause a delay in each delay circuit but generates a delay time by the delay correction circuit 40, and the second delay means 22 , And is given to the combiner 18-1 in phase with the same delay time. Here, when “1” is output as output data from the phase control means 30 and inverted by the inverter and given “0”, the second delay means 22 does not apply a delay time to the passing signal, Is given as a reference, a relatively advanced phase is given. The first to seventh delay circuits are, for example, 0.1,
0.2, 0.4, 0.8, 1.5, 3.0, 6.0 ns
Is set to the delay time. Note that the delay correction circuit 40 is set to a delay time of 4.0 ns. By appropriately selecting and controlling these delay circuits, the delay time can be adjusted with a unit time width of 0.1 ns, and the two output signals of the first and second delay means 16 and 22 are switched from the same phase to the second output signal. Signal of the first delay means 16 is 1
A signal up to 2.0 ns delayed can be output.

Next, a specific configuration of FIG. 2 will be described with reference to FIG. The basic structure of the delay circuit is such that a through path Lt and a delay path Ld in which a delay element DL is interposed are parallel to each other, and a switch having one circuit and two contacts is provided at both ends thereof, and switches at both ends are provided. Controlled in conjunction, either the through path Lt or the delay path Ld is selected. Thus, the first delay means 16 includes a plurality of pairs of switches sw1, 2, sw3, 4, s constituting the respective delay circuits 16-1, 16-3, 16-5, 16-7.
w5, 6, sw7, and 8 are arranged in series with a capacitor interposed between the input terminal and the combiner 18-1. Then, a through path Lt and a delay path Ld via a delay element DL set to an appropriate delay time are connected in parallel between a plurality of pairs of switches. These plural pairs of switches sw1, sw2, sw3, 4, sw5, 6, sw7, 8
Are A1, as output data from the phase control means 30,
It is controlled by signals A3, A5 and A7.

The second delay means 22 includes sw9, 10, sw11, 12, and sw as a plurality of pairs of switch means constituting each of the delay circuits 22-2, 22-4, and 22-6.
13 and 14 are arranged in series with a capacitor interposed between the input terminal and the combiner 18-1. Similarly, a through path Lt and a delay path Ld are connected in parallel between a plurality of pairs of switches. These plural pairs of switches sw9, 10, sw11, 12, sw13, 14
Are A2, as output data from the phase control means 30,
The signals of A4 and A6 are supplied to inverters 42-1, 42, respectively.
-2, controlled by the signal inverted at 42-3.

Incidentally, the switches sw1 to sw14 are actually constituted by IC circuits, and the signals are delayed while passing through the switches and the like. Also, the longer the path, the longer the signal is delayed. In FIG. 3, the first
The second delay means 22 passes signals through six switches, while the delay means 16 passes signals through eight switches. Therefore, the output signal of the first delay means 16 lags the output signal of the second delay means 22 even if only the passage of the switch is considered. By setting such a delay time to be the delay time (4.0 ns in the example of FIG. 2) which can be set to the maximum by the second delay means 22, the delay shown in FIG. Correction circuit 4
0 is omitted.

Next, the phase control means 30 will be described. The phase control means 30 is a central processing means having storage means, and outputs appropriate parallel data to the first and second delay means 16 and 22 as output data A1 to A7 upon receiving channel data and the like. .., CH62 in Table 1 and the corresponding output data of A1 to A7 in the form of a matrix.

[0022]

[Table 1]

More specifically, when CH1 is given as channel data, signals A1 to A1 are first synthesized to combine the signals of the first and second antenna elements 10 and 12 in phase.
7 are the first and second output data of which are all “0” are read out.
To the delay means 16 and 22 of FIG. Note that, in the in-phase synthesis, “0” is output for all of A1 to A7 in all the channels. Then, a through path is selected for all delay circuits of the first delay means 16, and the delay correction circuit 40 selects 4.0 n.
s delay time is given and output. The delay circuit of the second delay means 22 includes inverters 40-1, 2, 3
Are output, the delay paths are all selected, and 4.0 ns is given as the total delay time and output. Here, assuming that the output data of "1" is given from the phase control means 30 and the delay circuit is activated, in the first delay means 16, the delay circuit selects the delay path and is in the activated state. In the second delay means 22, the delay circuit selects the through path and is in the operating state. Therefore, the two signals are output in phase. Next, in order to combine with a phase difference of π / 2, A1 to A7 are “0, 0, 1, 1, 1,
0,0 "(the 7-bit data is A7, A6, A
5, A4, A3, A2, and A1. )
In the first delay means 16, a delay path is selected by the third and fifth delay circuits 16-3 and 16-5, and a through path is selected in the other delay circuits. Is output as 5.9 ns. Also,
In the second delay means 22, the second and sixth delay circuits 22-
The delay path is selected at 2, 22-6, the through path is selected for the other fourth delay circuit 22-4, and the total delay time is output as 3.2 ns. Therefore, the signal of the first delay means 16 is delayed by 2.7 ns which is the difference between the total delay time of the first delay means 16 and the signal of the second delay means 22.
This 2.7 ns substantially corresponds to the phase difference π / 2 with respect to the reception frequency of the received CH1. Subsequently, the outputs A1 to A7 are "0, 0, 0,
1,1,1,0 ", and the first delay means 16 outputs
Only the fifth delay circuit 16-5 selects the delay path, and the total delay time is output as 5.5 ns. Also, the second
In the delay means 22, only the second delay circuit 22-2 selects the delay path, and the total delay time is output as 0.2 ns. Therefore, the time difference is 5.3 ns, which is substantially π with respect to the reception frequency of CH1. Further, in order to combine with a phase difference of 3π / 2, the outputs A1 to 7 output “1, 0, 1, 0, 1, 0, 1”, and all the delay circuits are delayed by the first delay means 16. The path is selected, and the total delay time is output as 12.0 ns. Also, the second
In all the delay circuits 22, the delay circuit selects the delay path, and the total delay time is output as 4.0 ns. Therefore, the time difference is 8.0 ns, which is approximately 3π / 2 with respect to the reception frequency of CH1.

When CH62 is given as the channel data, all the outputs A1 to A7 output "0" in order to first combine in phase. Next, the outputs A1 to A7 are "1,
1,0,0,0,0,0 "and outputs the first delay means 1
6 is 4.1 ns, the total delay time of the second delay means 22 is 3.8 ns, and the difference is 0.1 ns.
3 ns, which is substantially equal to the phase difference π / 2 with respect to the reception frequency of CH62. Subsequently, the outputs A1 to A7 output "1,1,1,0,0,0,0", the total delay time of the first delay means 16 is 4.5 ns, and the second delay means 22 Is 3.8 ns, and the difference is 0.7 ns, which is approximately equal to π. Further, the outputs A1 to A7 output "0, 1, 0, 1, 0, 0, 0", the total delay time of the first delay means 16 is 4.0 ns, and the output of the second delay means 22 is Total delay time is 3.0 ns
And the difference of 1.0 ns corresponds to 3π / 2.

As described above, by appropriately switching the output data of the outputs A1 to A7 in accordance with the channel data, even in the case where the reception frequency is different, the number of scanning steps of the antenna element in the combined directional direction is 4 in the above embodiment. One. In the above embodiment, in order to combine two signals with a predetermined phase difference with respect to a difference in reception frequency,
The delay time difference is adjusted for each of the reception frequencies.

FIG. 4 is a diagram showing a combined directional pattern of antenna elements at a reception frequency of 90 MHz in the scanning antenna apparatus of the present invention shown in FIG. To π /
2, π, 3π / 2 combined directional pattern (b),
In (c) and (d), the directional direction is rotationally scanned. FIG. 5 is a diagram showing a combined directional pattern of an antenna element at a reception frequency of 470 MHz, which has a complicated beam but shows that the combined directional pattern is rotationally scanned by a combined phase difference. FIG. 6 is a diagram showing a combined directional pattern of the antenna element at the reception frequency of 770 MHz, which has a more complicated beam, but shows that the combined directional pattern is rotationally scanned by the combined phase difference. .
4 to 6, the first and second antenna elements 10 and 12 are arranged at a distance on a line connecting 0 ° and 180 °.

In the description of FIGS. 2 and 3, the outputs A1 to A1 of the phase control means 30 are provided for easy understanding of the description.
Reference numeral 7 denotes output data of all "0", and the delay correction circuit 40 is provided so that the two output signals of the first and second delay means 16 and 22 have the same phase, or have the function thereof. However, it is sufficient that the combined directivity direction is controlled by rotational scanning. When all the outputs A1 to A7 are "0", the fact that the two output signals of the first and second delay means 16 and 22 are in phase is practical. Is not important. Therefore, even if the delay correction circuit 40 in FIG. 2 is omitted, rotational scanning control of the combined directional direction can be performed. For example, if CH1 is given as channel data and outputs A1 to A7 are all "0" output data,
All the delay circuits of the first delay means 16 select the through path, but all the delay circuits of the second delay means 22 select the delay path. As a result, the output signal of the first delay means 16 The output signal of the second delay means 22 is 4.0 ns.
Only late. Next, outputs A1 to A7 are “0, 0, 1, 1,
1, 0, 0 ", in the first delay means 16, the third and fifth delay circuits select a delay path, and the second delay means 2
At 2, the second and sixth delay circuits select the delay path, with the result that the output signal of the second delay means 22 lags the output signal of the first delay means 16 by 1.3 ns.
Subsequently, the outputs A1 to A7 are "0, 1, 1, 1, 0, 0,
If "0", the first delay means 16 selects the delay path only for the fifth delay circuit, and the second delay means 22 selects the delay path only for the second delay circuit.
The first delay means 16 with respect to the output signal of the delay means 22
Is delayed by 1.3 ns. Further, the output A1
If 7 is “1,0,1,0,1,0,1”, the first
And the second delay means 16 and 22 all select a delay path by the delay circuit, and the first delay means
The output signal of the delay means 16 is delayed by 4.0 ns. Therefore, for each of the outputs A1 to A7, the first
The output signal of the delay means is advanced by 4.0 ns with respect to the output signal of the second delay means 22, advanced by 1.3 ns, delayed by 1.3 ns, and delayed by 4.0 ns.
If 4.0 ns is added and corrected to these time differences, the time difference with respect to the phase difference in Table 1 will be obtained, so that it can be understood that scanning in the combined directional direction is performed by 90 degrees. Note that this combined directional direction is shifted by about 0.7π from that in which the outputs A1 to A7 are all “0” and are combined in phase.

Further, in the description with reference to FIGS. 2 and 3, the output data from the phase control means 30 provided to the second delay means 22 is inverted by the inverters 40-1, 2, 3, but is not limited thereto. The output data from the phase control means 30 to be provided to the first delay means 16 may be inverted by an inverter. In other words, if the output data of "1" is given from the phase control means 30 and the delay circuit is activated, the delay circuit in the first delay means 16 selects the through path and is in the operational state. In the second delay means 22, the delay circuit may select the delay path and operate. The operation in such a case will be briefly described. If the outputs A1 to A7 are all "0", all the delay circuits of the first delay means 16 select the delay path, all the delay circuits of the second delay means 22 select the through path, The output signal of the delay means 16 lags the output signal of the second delay means 22 by 8.0 ns. Next, outputs A1 to A7
Is "0, 0, 1, 1, 1, 0, 0", the first delay means 16 selects the delay path by the first and seventh delay circuits, and the second delay means 22 Four delay circuits select the delay path, resulting in the output signal being delayed by 5.3 ns. Subsequently, the outputs A1 to A7 are "0, 1, 1, 1, 0, 0, 0".
If so, the first delay means delays by 6.5 ns and the second delay means 22 delays by 3.8 ns, resulting in the output signal being delayed by 2.7 ns. Further, outputs A1 to A7
Is "1,0,1,0,1,0,1", the delay circuits of the first and second delay means 16 and 22 all select the through path, and as a result, the output signal becomes in-phase. Become. The rotation direction of the scan in the combined directional direction is opposite to that described above.
Obviously, it is scanned step by step.

In the above description, the output data of the matrix-shaped outputs A1 to A7 stored in the phase control means 30 is inverted by one of the first and second delay means 16 and 22 via an inverter. However, it is needless to say that the inverted output data may be stored in advance and the inverter and the like may be omitted.

In the scanning antenna device of the present invention having the above-described configuration, the two antenna elements 10 and 12
The signals received by the television tuner 2 are synthesized.
4, the electric field strength of the combined signal is stronger than the reception strength of one antenna element, so that reception in a favorable radio wave condition can be performed. In addition, since the combined directional direction of the antenna element is rotationally controlled, it is possible to cover all directions with a range of a beam having a high antenna gain, and to reliably receive a radio wave from any direction. it can.

Then, as in the above embodiment, the first and second
By providing the first and second delay means 16 and 22 in the antenna elements 10 and 12, respectively, the amounts of signal attenuation in both paths can be made substantially the same, and the signals are synthesized by the synthesizing means 18 as signals of substantially the same magnitude. it can. Therefore, the synthesized signal is also output efficiently. That is, the first delay means 16 has an attenuation characteristic diagram when a through path is selected in all delay circuits, and an attenuation characteristic diagram when a delay path is selected in all delay circuits. And the amount of attenuation is determined. Similarly, the amount of attenuation of the second delay means 22 is determined between FIG. 8A and FIG. 8B. 7 and 8
Are substantially the same, and the output signals from the first and second delay means 16 and 22 have substantially the same amount of attenuation.
Obviously, the difference between the attenuation amounts of the two output signals is smaller than when the delay means is provided only on the path of one antenna element.

In the scanning antenna apparatus of the present invention, the number of scanning steps in the combined directional direction of the antenna element is constant at 4 irrespective of the receiving frequency, so that scanning can be performed quickly even in a wide receiving range. . In addition, since the data for scanning is read from the storage means in correspondence with the channel data, the output of the output data for controlling the delay means for scanning is quick. In particular, in a television receiver or the like, it is desirable that scanning be completed within a vertical blanking period, and the scanning antenna device of the present invention that can rapidly perform rotational scanning control is preferable.

Further, the digital data output from the phase control means is parallel data, and each of the delay circuits to which the data of each line is given is controlled between an operating state and a non-operating state. The operation state and the non-operation state only need to be selected by the output of “0”, and the circuit structure for controlling the delay circuit is simple.

If the output signals of the two antenna elements are combined with the same phase and with a phase difference of 90 degrees, 180 degrees and 270 degrees, the combined directional directions are each 1/4 of the angle between adjacent lobes. Scanning while changing the direction,
The incoming direction of the reception frequency can be covered in a range of 360 degrees.

In the above-described embodiment, the scanning antenna device of the present invention is used as an antenna of an in-vehicle television receiver. However, the present invention is not limited to this, and can be applied as an antenna of a radio receiver or a transceiver. . It is also suitable as an antenna for a portable television receiver or the like. Further, the number of scanning steps in the combined directional direction is not limited to four, and may be appropriately set based on the width of the half-value angle of the beam of the combined directional pattern. The technique proposed in, for example, Japanese Patent Application Laid-Open No. 7-58537 can be applied as a broadband, non-directional antenna element.
Further, the rotational scanning control in the combined directional direction is not limited to the one operated in relation to the vertical synchronization signal.

[0036]

As is apparent from the above description, since the scanning antenna device of the present invention is constituted,
It has the following special effects.

In the scanning antenna device according to the first aspect, the number of steps of the rotational scanning control in the combined directional direction of the antenna element is the same regardless of the reception frequency;
Rotational scanning can be performed quickly even in a wide reception range. Also,
Since the first and second delay means are each formed by a plurality of delay circuits, and the plurality of delay circuits are set to different delay times from each other, an appropriate combination of these delay circuits can be selectively controlled. The relative delay time can be set with a small unit time width, and the two output signals can be combined with an appropriate phase difference.

In the scanning antenna device according to the second aspect of the present invention, the delay circuit is controlled to be active and inactive by the data of each line of the parallel data. What is necessary is just to perform selection control corresponding to the output of "0", and the circuit structure for controlling the delay circuit is simple. In particular, it is suitable to configure the switch means for controlling the delay circuit with an IC circuit or the like.

Further, in the scanning antenna device according to the third aspect, since the combined directional directions of the two antenna elements are changed in direction by 角 of the angle between adjacent lobes, the scanning is performed. The incoming direction of the reception frequency can be covered in the entire range of degrees.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a receiver using an embodiment of a scanning antenna device of the present invention.

FIG. 2 is a more detailed block circuit diagram showing a configuration example of a delay unit in FIG. 1;

FIG. 3 is a diagram specifically showing a circuit configuration of a delay unit shown in FIG. 2;

4A and 4B show a combined directional pattern when a reception frequency is set to 90 MHz. FIG. 4A shows a result of combining output signals of two antenna elements in the same phase, and FIG. 4B shows a result of combining signals with a phase difference of 90 degrees. (C) is obtained by combining with a phase difference of 180 degrees, and (d) is obtained by combining with a phase difference of 270 degrees.

5A and 5B show combined directional patterns when the reception frequency is set to 470 MHz. FIG. 5A is a diagram in which output signals of two antenna elements are combined in phase, and FIG.
(C) is a phase difference of 180 degrees, (d) is a phase difference of 27 degrees.
These are synthesized with a phase difference of 0 degrees.

6A and 6B show combined directional patterns when the reception frequency is 770 MHz, where FIG. 6A shows the same phase, FIG. 6B shows a phase difference of 90 degrees, FIG. 6C shows a phase difference of 180 degrees, and FIG. These are synthesized by the phase difference of degrees.

FIGS. 7A and 7B show frequency versus attenuation characteristics of a first delay path connected to the first antenna shown in FIGS. 1 and 2; FIG. 7A shows a case where all delay circuits are through; This is a case where a delay time is given to all delay circuits.

8A and 8B show frequency versus attenuation characteristics of a second delay path connected to the second antenna shown in FIGS. 1 and 2; FIG. 8A shows a case where all delay circuits are through; This is a case where a delay time is given to all delay circuits.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 1st antenna element 12 2nd antenna element 16 1st delay means 18 Synthesizing means 22 2nd delay means 30 Phase control means

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-62-224129 (JP, A) JP-A-62-243404 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01Q 3/00-3/46 H01Q 21/00-21/30 H01Q 23/00 H01Q 25/00-25/04

Claims (3)

(57) [Claims] 1. Two antenna elements arranged at a distance, first and second delay means for respectively giving a delay time to an output signal from these antenna elements, and the delayed output signal Combining means for combining the antenna elements, and the first and second delay means so as to scan the combined directional direction of the antenna element based on the phase difference between the delayed output signals of the antenna elements combined by the combining means. Phase control means for controlling the delay time, wherein the first and second delay means are respectively formed by a plurality of delay circuits, and all the delay circuits forming the first and second delay means are provided. The phase control means has storage means for setting different delay times from each other, and receives the signals so that the number of scanning steps in the combined directional direction becomes the same at each frequency to be received. Digital data corresponding to the delay time set in the first and second delay means for the frequency to be received is stored in the storage means in advance, and the digital data is scanned according to the frequency to be received. A scanning antenna device wherein the first and second delay means are read out every time to control the first and second delay means. 2. The scanning antenna apparatus according to claim 1, wherein said digital data is provided to said delay circuit as parallel data from said phase control means, and said delay circuit is operated in accordance with data of each line of said digital data. A scanning antenna device configured to be controlled to a non-operating state. 3. The scanning antenna device according to claim 1, wherein the number of scanning steps is four, and the two output signals are sequentially in-phase and at a phase difference of 90 degrees, 180 degrees and 270 degrees by the combining means. A scanning antenna apparatus wherein the digital data is stored in advance in the phase control means so as to control the first and second delay means so as to be combined with each other.