JP3280771B2 - Fan-out disassembly method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for decomposing a fan-out of a device.

[0002]

2. Description of the Related Art A signal delay (wiring delay) generated in a wiring between elements in a semiconductor integrated circuit is caused by an on-resistance of an element, an input capacitance of a next-stage element, and a resistance component and a capacitance component parasitic on a metal wiring. . In the conventional processing technology, since the resistance component and the capacitance component parasitic on the metal wiring are very small, it is possible to ignore the signal delay generated in the metal wiring. However, due to recent advances in processing technology, metal wiring has become finer, and the element spacing has increased due to an increase in the degree of integration, thereby increasing the parasitic component of the metal wiring, making it impossible to ignore the signal delay generated in the metal wiring. ing. In the design of semiconductor integrated circuits in recent years, it is essential to consider wiring delay. The method of calculating the wiring delay will be described below.

[0003] When the component parasitic on the metal wiring is ignored,
The wiring delay can be calculated as follows.

Wiring delay = R (i) × ΣC (j) (1) j∈O (i) R (i): ON resistance of element i C (j): Input capacitance O (i) of element j )... A set of elements driven by the element i The wiring delay in the conventional circuit design has been estimated by equation (1). However, this calculation method has a problem that an error is large. For this reason, a method of calculating a wiring delay in which the effect of the capacitance component parasitic on the metal wiring is added to the equation (1) has been adopted. This equation is shown below.

Wiring delay = R (i) × [ΣC (j) + Cw (i)] (2) j∈O (i) R (i): On resistance of element i C (j): element j The input capacitance O (i) of the element is a set of elements driven by the element i Cw (i) The capacitance component parasitic on the metal wiring connecting the element i and the element O (i) To be proportional,
The value of Cw (i) is determined by estimating the wiring length. Since it is empirically known that the sum of the wiring lengths is proportional to the number of elements included in O (i), an estimation formula of Cw (i) is generally formed by statistically examining the wiring lengths. That is being done. Although this wiring delay estimation method is more accurate than the equation (1), since the resistance component parasitic on the metal wiring is ignored, a delay more than estimated after layout may occur.

In order to accurately calculate the wiring delay, the parasitic resistance component of the metal wiring cannot be ignored. However, it is necessary to estimate the wiring topology in order to consider the resistance component. This is very difficult to do. The following equation shows a calculation formula of the wiring delay in the circuit and the layout example as shown in FIG. 7 in consideration of the resistance component. In this example, the model for delay calculation is as shown in FIG. 8, and the delay from the element 71 is as follows. R
on is the on-resistance of the element 71, and C (3) and C (4) are the input capacitances of the elements 71 and 73.

(Wiring delay between element 71 and element 72) = Ron [C (1,2) + C (2,3) + C (2,4) + C (3) + C (4)] + R (1,2) [C (1,2) / 2 + C (2,3) + C (2,4) + C (3) + C (4)] + R (2,3) [C (2,3) / 2 + C (3)] (Element Wiring delay from 71 to element 73) = Ron [C (1,2) + C (2,3) + C (2,4) + C (3) + c (4)] + R (1,2) [C (1, 2) / 2 + C (2,3) + C (2,4) + C (3) + C (4)] + R (2,4) [C (2,4) / 2 + C (4)] (3) As shown in parentheses), the wiring delay is closely related to the wiring topology. As described above, it is extremely difficult to design a circuit while more accurately estimating a wiring delay. Therefore, usually, the wiring delay prediction at the time of designing a logic circuit is performed ignoring the parasitic resistance component of the metal wiring. For this reason, the delay time estimated at the time of logic circuit design and the delay time actually measured after the layout processing are largely different from each other, and the integrated circuit may not operate.

In order to cope with such a situation, a fan-out decomposition process is performed. Here, the fan-out decomposition processing is to reduce the total wiring delay by inserting a buffer element into a net of multiple output elements to divide the net. FIG. 9 shows a net before the fan-out decomposition processing, and FIG. 3C shows a net after the fan-out decomposition processing.

The fan-out decomposition process proposed in the past includes KJ Singh et al., “AHeuristic Algorithm for t
he Fanout Problem ”, Proc. of the 27th DAC, pp.357-
360, June 1990, S. Lin et al ,. “A Fast and Efficient
Algorithm for Determining Fanout Trees in Large Ne
tworks ”, Proc. of the Euro. Dac, pp.539-544, Feb 19
91. is known. However, the conventional fan-out decomposition processing is performed in consideration of only the parasitic capacitance, and thus has a problem that the effect of delay reduction is small.

FIG. 3 shows a model for fan-out decomposition according to the conventional method. In the conventional method, a net is represented by a directed graph as shown in FIG. Here, the node 0 corresponds to an element that outputs a signal, and the other nodes correspond to elements that input a signal. The branches on the graph all go from node 0 to other nodes. Using a delay calculation method based on equation (2) on this graph, buffer elements are inserted so that the signal delays to all the nodes become the required values, and the fanout is decomposed. Figure 3 shows the buffer element insertion and net disassembly.
It is represented by a graph as shown in FIG. g1 is a node corresponding to the buffer element. In such a conventional method,
Although it is possible to consider the distance from node 0 as the weight of a branch, it is not possible to consider the positional relationship between nodes.

Such a conventional method has a problem that the net topology cannot be estimated because of the model used. For this reason, delay prediction in consideration of the parasitic resistance component cannot be performed, and a delay greater than the predicted value may occur after layout processing. Further, since the arrangement position of the elements cannot be considered, the applicable range is narrow. That is, since the conventional method cannot consider the arrangement position of the elements, it cannot be applied to the data after arrangement. For example, when the conventional method is applied to the data after arrangement as shown in FIG. 4, only the distance from the element 0 is taken into consideration.
There is a possibility that elements arranged at a distance from each other such as the element 6 and the element 6 may be combined into the same net (FIG. 3).
(C)). This makes the wiring process extremely difficult. From the above two points, the conventional method has a problem that even if it is applied to a recent semiconductor integrated circuit in which a parasitic component of a metal wiring appears remarkably, it cannot be sufficiently considered.

[0012]

As described above, the conventional fan-out disassembling method has a problem that the resistance component parasitic on the metal wiring cannot be considered. Further, there is a problem that the effect of shortening the expected delay time cannot be obtained because the position of the element cannot be considered, and that the layout becomes difficult.

Accordingly, the present invention has been made in view of such conventional circumstances, and has as its object to consider a resistance component which is parasitic on a metal wiring, and to apply an integrated circuit after layout to an element position. It is an object of the present invention to propose a fan-out decomposition method capable of reducing a wiring delay.

[0014]

In order to achieve the above object, the present invention provides a means for creating a directed graph having nodes of logic elements and buffer elements when performing fan-out decomposition of a logic circuit; Means for constructing a tree structure rooted at a node corresponding to an element outputting a signal above, means for inserting the same number of buffer elements as the number of nodes corresponding to buffer elements on the tree structure, Means for decomposing the net at the position of the node corresponding to the buffer element above.

Further, according to the present invention, when creating a directed graph in which the logic element and the buffer element are nodes, a directed graph in which the logic element is a node is created, and an arbitrary graph i of the directed graph in which the logic element is a node is created. Directed branch (i,
j), there is a node g corresponding to the buffer element, a directed branch (i, g) from the node i to the node g corresponding to the buffer element,

A branch (g, j) from a node g corresponding to the buffer element to the node j is added to the directed graph.

Further, according to the present invention, when the directional branch (i, j) is extended from the arbitrary node i to the node j, the X element has the same X coordinate as that of the arbitrary logical element i. Y for i
Logic element i among logic elements having a Y coordinate larger than the coordinate
Logic element closest to the logic element i, and X of the logic element i.
A logic element having the same X coordinate as the coordinates and having a smaller Y coordinate than the Y coordinate of the logic element i, the logic element having the shortest distance from the logic element i;

A logic element having the same Y coordinate as the Y coordinate of the logic element i and having the X coordinate larger than the X coordinate of the logic element i, the logic element having the shortest distance from the logic element i;

A logic element having the same Y coordinate as the Y coordinate of the logic element i and having an X coordinate smaller than the X coordinate of the logic element i, the logic element having the shortest distance from the logic element i;

A logical element having the X coordinate larger than the X coordinate of the logical element i and the Y coordinate larger than the Y coordinate of the logical element i, the logical element having the shortest distance from the logical element i; A logical element having the X coordinate larger than the X coordinate of the logical element i and the Y coordinate smaller than the Y coordinate of the logical element i, the logical element closest to the logical element i, and the Y coordinate larger than the Y coordinate of the logical element i And a logical element having the X coordinate larger than the X coordinate of the logical element i, the logical element closest to the logical element i, the Y coordinate larger than the Y coordinate of the logical element i, and the X of the logical element i. When a set of logic elements having the X coordinate smaller than the coordinates and having the closest distance from the logic element i is defined as S (i), the logic element set is determined from a node corresponding to an arbitrary logic element i. Included in S (i) It is characterized by tensioning a directed edge toward the section corresponding to the element.

Further, according to the present invention, when constructing the tree structure, means for giving a required value of a signal propagation time from an element outputting a signal to a node on a directed graph corresponding to a logical element, and an element outputting a signal Means for selecting a target clause from a set of clauses other than the clause corresponding to, means for tracing along the direction of the directed branch from the node corresponding to the element outputting the signal to the target clause along the direction of the directed branch, and Means for predicting the signal propagation time from the corresponding node to the target node, the branch and the node when the predicted value of the signal propagation time becomes less than or equal to the required value when following the directed graph along the direction of the directed branch Is selected.

Further, according to the present invention, when performing the layout processing of the logic circuit, the timing analysis is performed after the wiring processing between the logic elements is completed, and a net requiring a delay time longer than the required wiring delay is selected. Erase the wiring route of the selected net, insert a buffer element into the net by applying the above-described fan-out decomposition method,

It is characterized in that the wiring route of the net is obtained again.

[0024]

According to the above-mentioned means, the present invention creates a directed graph consisting of nodes corresponding to elements and nodes corresponding to buffer elements to be inserted from the arrangement information of the elements, and searches the directed graph while estimating the wiring propagation delay to search the tree. By constructing the structure, it is possible to consider the arrangement position of the element, that is, the net topology, perform the fan-out decomposition while evaluating the delay time in consideration of the resistance component parasitic on the metal line segment, and dispose the arrangement position of the element. Is considered, it is possible to perform fan-out decomposition without making the layout processing difficult.

Further, according to the present invention, it is possible to construct a tree structure at high speed by limiting directional branches when creating a directed graph.

[0026]

An embodiment of the present invention will be described below with reference to the drawings. According to the present invention, the fan-out of the signal output element is decomposed by inserting a buffer element. In the method, first, a net as shown in FIG. 4 is represented by a directed graph as shown in FIG. 1A (9). The numbers of the nodes on the graph represent the corresponding elements. Node 0 corresponds to signal output element 0,
Others correspond to signal input elements. Branches between nodes are set up based on the positional relationship of the corresponding elements.

FIG. 5 shows an example in which a branch from node 2 corresponding to element 2 is set. The branch between the nodes is represented by the Manhattan length (distance in the X direction + distance in the area divided into four around the element of interest).
(A distance in the Y direction) toward the node corresponding to the element that is present at the closest position. In the example of FIG. 5, a branch from node 2 to nodes 1, 3, 5, and 7 is provided.

Next, a tree having a signal output element as a root is generated on the directed graph (10). An example of this tree is shown in FIG. g1 is a node corresponding to the inserted buffer element. The tree is constructed by repeatedly searching the graph for a path that minimizes the delay time from node 0 to another node. FIG. 2 shows the process of tree construction. In this example, first, a route from node 0 to node 6 is searched (FIG. 2).
(A)). In the search, while calculating the delay from node 0, a path that always passes through the branch with the minimum delay is selected. The search uses the A * algorithm with delay time as cost.

The nodes that have passed in the course of the route search, in this example, nodes 1 and 7, are determined to have already been constructed, and the route search is not performed again. Since the route to nodes 1, 7, and 6 was searched,
To node 5 (FIG. 2B) and nodes 0 to 4
(FIG. 2 (C)). In the course of the route search, a buffer element g1 is inserted if necessary to achieve a target delay time.

Finally, from this tree structure, a net topology as shown in FIG. 1 (C) is generated and buffer elements are inserted. In this example of a tree structure, the nets are elements 0, 1, 6,
7 means that the buffer elements 2, 3, 4, and 5 are separated into elements 2, 3, 4, and 5 so as to drive them. The physical position is between the element 1 and the element 2.
Hereinafter, details of each process will be described.

FanoutProblem (CELLS) CELLS is a set of elements included in a multi-output element net; ｛G (V, E) is a directed graph; T (TV, TE) is a tree; G (V, E) = Generate directed graph (CELLS); ... (9) T (TV, TE) = Generate tree (G (V, E)); ... (10) Net divide (T (TV, TE)); ... (11)｝ First, from the arrangement position of the elements as shown in FIG.
A directed graph as shown in FIG. 1A is generated (9).

A description will be given of the expression of a directed graph G (V, E) of a net. v is a set of nodes on the directed graph, and E is a set of directed edges. (I, j) ∈E, from clause i∈V to clause j
枝 represents a branch toward V. Among the nodes on the directed graph, a node having no directional branch toward itself is called a signal output node. Also, a node input by a directional branch from node i is called an adjacent node of i, and a set of adjacent nodes of i is denoted as ADJOIN (i).

The flow of the directed graph creation process is shown below. First, a directed graph having nodes and branches corresponding to elements included in a net is created from given net information (1).
2, 13). Next, nodes and branches corresponding to the buffer elements are created (14).

Generate Directed Graph (CELLS) CELLS is a set of elements included in a net of multiple output elements; （G (V, E) is a directed graph, V is a node set, E is a directed branch set; V ′ = Generate vertexes (CELLS); ... (12) E '= Generate directed edges (V'); ... (13) [V ~, E ~] = Generate buffer vertexes and edges (V ', E'); ... (14) V = V'∪V ~; ... (14) E = E'∪E ~; ... (14)｝ return G (V, E);｝ Generate vertexes (CELLS) CELLS is a set of elements included in the multi-output element net.作 り Create a clause corresponding to CELLS and store it in the clause set V ′; return V ′;｝ Next, processing for creating a branch on the directed graph will be described below.
To make a branch from node i to another node, first, a node set V
ERTEXTES (i) = N (i) ∪S (i) ∪W (i)
∪E (i) ∪NE (i) ∪NW (i) ∪SE (i) ∪S
Make W (i) 15. Here, the clause set N (i), S
(I), W (i), E (i), NE (i), NW
(I), SE (i), and SW (i) are a set of clauses having the following relationship with the coordinates of the clause i.

N (i) is Px (i) = Px (k) and Px (i)
A set of elements having the shortest internode distance among elements having a coordinate relationship of y (i) <Py (k). S (i) is Px (i) =
A set of elements having the shortest internode distance among elements having a coordinate relationship of Px (k) and Py (i)> Py (k), W
(I) is Px (i)> Px (k) and Py (i) = Py
A set of elements having the shortest internode distance among the elements having the coordinate relationship of (k). E (i) represents the coordinate relationship of Px (i) <Px (k) and Py (i) = Py (k). A set of elements having the shortest internode distance among the elements that have, NW (i) is Px
(I)> Px (k) and a set of elements having the shortest internode distance among elements having a coordinate relationship of Py (i) <Py (k), and NE (i) is Px (i)> Px (k ) And Py
A set of elements having the shortest internode distance among elements having a coordinate relationship of (i)> Py (k), SW (i) is Px (i) <
A set of elements having the shortest internode distance among elements having a coordinate relationship of Px (k) and Py (i) <Py (k), SE
(I) is Px (i)> Px (k) and Py (i)> Py
A set of elements having the shortest internode distance among the elements having the coordinate relationship (k). However, k∈V '-｛i｝-
{S}. The node s is a node corresponding to an element that outputs a signal.

The X coordinate of the element corresponding to the node i in Px (i), the Y coordinate of the element corresponding to the node i in Py (i), and the internode distance L (i, k) are L (i, k). k) = | Px (i) -Px (k) | + | Py (i) -Py (k) |

Next, from node i to node set VERTEXTES
A branch is made to the node belonging to (i) (16).

Generate directed edges (V ′) V ′ is a node set; Ｅ E ′ is a directed branch set; E ′ = φ; For each vertex itexV ′ ｛N (i), S (i), W ( i), E (i), NE (i), NW (i), SW (i), SW (i);｝ VERTEXES (i) = N (i) ∪S (i) ∪W (i) ∪E (i) ∪NE (i) ∪NW (i) ∪SE (i) ∪SW (i);｝… (15) For each vertex k∈VERTEXES (i)… (16) E ′ = E′∪ {(I, k)}; (16) {return E ′;} FIG. 5 shows an example of creating a directed branch. In this example, directed branches from node 2 to nodes 1, 3, 5, and 7 are created. FIG.
4A illustrates a directed graph created from the circuit example shown in FIG. The output node 0 corresponds to the element 0 that outputs a signal.

Next, processing for creating a node (buffer node) and a branch (buffer branch) corresponding to the buffer element will be described. The creation of the buffer node and the buffer branch is performed for each directional branch belonging to the directional branch set E. To create a buffer node and a buffer branch for the directed edge (i, j) ∈E ′, first, a node g corresponding to the buffer element is created (17), and then nodes i to g
And a branch from g to j (18).

Generate buffer vertexes and edges (V ′, E ′) V ′ is a node set; E ′ is a directed edge set; ｛V ｛is a buffer node set; E〜 is a buffer branch set; V〜 = φ; E ~ = Φ; For each edge (i, j) {E '} Create a node g corresponding to the buffer element; ... (17) V ~ = V ~ {g}; ... (17) E ~ = E ~ ∪ {(I, g), (g, j)};... (18) {Return [V〜, E〜];｝ FIG. 6 shows an example of buffer node and branch insertion. For the branch of (1,2), one buffer node g1 and two directional branches (1, g1) and (g1,2) are stored in the buffer of g2 for the branch of (2,1). Knots and directed branches (2, g2), (g2,
1) Add.

According to the present invention, a tree T [TV,
TE], fan-out decomposition is performed. Here, the root is a node that has no branch toward itself. T
V is a node set TE on the tree is a directed branch set. However, there is a relationship TV = V, TE⊂E between the tree and the graph. FIG.
(B) shows an example of a tree structure. In this example, node 0 is the root.

Next, terms used in the description of the tree construction method will be defined. If there are two or more directional branches from the node in the tree, the node is called a branch node.
In the example of FIG. 1B, 1 and 2 are branch nodes. A node that has no branch from itself is called a leaf. In the example of FIG. 1B, nodes 4, 5, and 6 are leaves.

Let i, j (i ≠ j) be any node on the tree. If there is a directed branch from i to j,
i is called the parent clause of j, and j is called the child clause of i. The parent clause of j is denoted as parent (j), and the set of child clauses of i is CHI
Notated as LDREN (i). In the example of FIG.
IMDREN (1) = {g1,7}, parent
(1) = 0.

Let i and j be different nodes on the tree. The path from i to j along the directed branch is PATH [PV (i,
j), PE (i, j)]. Where PV
(I, j) is a set of nodes on the path from node i to node j, P
E (i, j) is a set of directed edges on the path, and pv
(I, j) ⊂TV, PE (i, j) ⊂TE. FIG.
In the example of (B), PV (1,4) = ｛1, g1,2,3,
4}, PE (1, 4) = {(1, g1), (g1,
2), (2, 3), (3, 4)}.

Let i, j (i ≠ j) be any node on the tree. If the path PATH [PV (i,
j), PE (i, j)], j is called the downstream node of i, and i is called the upstream node of j. The set of downstream nodes of i is denoted as DOWNSTREAM (i), and the set of upstream nodes of j is denoted as UPSTREAM (j). If j is not the root, UPSTREAM (j) contains the root. Also,
If i is not a leaf, DOWNSTREAM (i) contains one or more leaves. In the example of FIG. 1B, DOWNSTREA
M (2) = {3,4}, UPSTREAM (2) =
{0, 1, g1}.

Let s be the root and i be any node on the tree. Here, i ≠ s. Also, a path PATH from s to i
Let g be a buffer node or root included in [PV (s, i), PE (s, i)]. If the path PATH [PV (g, i), PE (g, i)] from g to i does not include a buffer clause other than g, g is called a driver clause of i, and driver ( Notation i). FIG.
In the example of (B), the driver clause of section 3 is g1 and the driver clause of section 7 is 0.

Let i be an arbitrary node on the tree, LEAVES be a set of leaves, and V ~ be a set of buffer nodes.

[Outside 1] And If the path PATH [PV from i to k
If (i, k), PE (i, k)] exists and does not include a buffer clause other than k, k is called a terminal clause of i, and the set of terminal clauses of i is TERMINALS (i) Notation. In the example of FIG. 1B, TERMINALS
(0) = {g1,6}.

Let g be a buffer node or root on the tree.
At this time, the path PATH [TV from the g to the terminal node i of the g
(G, i), TE (g, i)] is a set of clauses
Notated as UBNET (g). That is, SUBNET (g) = {TV (g, i) | i {TERMINAL (g)}.

The tree structure as shown in FIG.
This corresponds to the net topology shown in FIG. A branch on the tree corresponds to wiring between elements corresponding to nodes connected by the branches, and a buffer node corresponds to dividing a net by a buffer element corresponding to the node. In the example of FIG. 1B, the buffer node g1 exists on the path from the node 1 to the node 2. In the equivalent net topology of FIG. 1C, a buffer g1 is inserted to decompose the fan-out. That is, the fan-out is determined from the obtained tree structure by SUBN.
ET (0) = {0,1,7,6, g1} and SUBNET
(Gl) = {g1,2,3,4,5}.

Next, a method for constructing a tree on the directed graph will be described. The tree is constructed by searching for a path from the signal output node s to all nodes V {s} other than s on the directed graph. The processing flow is shown below. The tree is constructed by first updating the parameters on the directed graph (19), and from the node set V of the directed graph, the node v having the minimum required delay among the nodes for which a path from the signal output node has not yet been found. (20). Next, a search is made for a route from a node belonging to the already constructed tree to v (21), and the searched route is added to the tree (21).

Generate tree (G (V, E)) G (V, E) is a directed graph; V is a set of nodes; E is a set of directed branches; ｛TV is a set of nodes on a tree; TE is a set of nodes on a tree S is a signal output node; TV = s; TE = φ; repeating the following processing until a route to all nodes is searched. ｛ModifyRoutingParameter (G (E, V), T ( (19) v = GetNotConnectedVertex (V); ... (20) T ~ [TV ~, TE ~] = PathFind (TV, v); ... (21) TV = TV∪TV ~; ... ( 22) TE = TE∪TE ~; ... (22)｝ return T [TV, TE]; パ ラ メ ー タ Parameters given to each node and directed edge on the directed graph are as follows, where s is a root and LEAVES is a set of leaves It is.

[Parameters Given to Directed Branches] C (i, j): Capacitance component parasitic on the metal wiring of the node connected by branch (i, j).

C (i, j) = c * L (i, j), (i, j) ∈E where c is the processing technology of the semiconductor integrated circuit and the components of the semiconductor and the materials used for the metal wiring. This is a parameter determined by components and the like.

R (i, j): A resistance component parasitic on the metal wiring of the node connected by the branch (i, j).

R (i, j) = r * L (i, j), (i, j) ∈E where r is the processing technology of the semiconductor integrated circuit and the components of the semiconductor and the materials used for the metal wiring. This is a parameter determined by components and the like.

[Parameters given to nodes] C (i): Input capacitance of the element corresponding to i {v {s}.

T (i): element delay of an element corresponding to i∈v〜.

R (i): ON resistance of the element corresponding to i {v to {s}.

C + (i): the sum of the parasitic capacitance component and the input capacitance of the branch on the path from i to the terminal node of i.

[0060]

(Equation 1) R- (i): The sum of the parasitic resistance component of the branch on the path from the driver node of i to i and the on-resistance of the driver node.

[0061]

(Equation 2) Dr (i): required value of delay time of signal from s to i {V {s}.

Da (i): delay time of signal from s to i {TV {s}.

[0063]

(Equation 3) p = parent (i) De (i): predicted value of the delay time of the signal from i to v.

[0064]

(Equation 4) Clim (i): upper limit of the capacity that can be added to i {TV {s}. If the upper limit is exceeded, the delay time of the root signal on the tree becomes longer than the required delay time.

[0065]

(Equation 5) Here, Clim- (i) = MIN [(Dr (j) -Da (j)) / R- (j) | j {UPSTREAM (i) {s}] Clim + (i) = MIN [(Dr ( j) -Da (j)) / R- (j) | j∈DOWNSTREAM (i)].

In the route search, a node belonging to the TV is set as a start point, v is set as a target point, and cost is set as a delay time from the signal output node to the target point, and a route with a minimum delay time is searched. The route search on the directed graph is based on the A * algorithm (Yoshiaki Shirai, Junichi Tsujii, "Artificial Intelligence", Iwanami Shoten, Iwanami Koza Information Science 22, 1982).

The A * algorithm is as follows: When an arbitrary node in the graph is i, the estimated value of the minimum cost from the start point to i is g (i), and the predicted value of the minimum cost from i to the target point is h When (i) is set, f (i) = g (i)
In a graph search strategy using + h (i) as an evaluation function, an optimal solution can be searched when the cost from node i to the target point can be predicted. According to the present invention, a route with the minimum delay is searched for by the A * algorithm using the above-described delay prediction time De (i). The processing flow is shown below.

First, a set OPEN, CLO for storing a clause
The SED is prepared, and the node belonging to the TV is stored in OPEN (25). Next, a node i having the minimum predicted delay value is extracted from OPEN (27, 28), and whether i is equal to v (2
9) The following processing is repeated until OPEN becomes empty (26).

For a clause j that satisfies the constraint condition among clauses belonging to the adjacent clause set ADJOIN (i) of i, Ne
Calculate wCost (35), OPEN or CLO
Put the clause not included in SED in OPEN (37),
OldCost (j) = NewCost (38),
The parameter is updated (39), and a pointer pointing to i is attached (40). The clause included in OPEN is NewC
ost and OldCost (j) are compared, and NewCos
If t <OldCost (j) (42), NewCo
st = OldCost (j) (43), the parameters are updated (44), and a pointer to i is attached (4).
5).

The clause included in CLOSED is New
Compare Cost and OldCost (j), and compare NewCo
If st <OldCost (j) (47), OPEN
(48), NewCost = OldCost
(J) (49), the parameters are updated (50), and i
(51).

The cost here is the predicted delay time from the root s to the target point v, that is, the sum of the delay time from the root s to the node i and the predicted delay time from i to the target point t.

The constraint condition is that the predicted delay time from the root s to the target point v is smaller than that required (32), and that the delay time from the root s to i is smaller than that required. 33), the upper limit of the capacity value that can be added is not exceeded (34). This constraint prevents the delay time to the element on the path that has already been discovered from becoming larger than the required delay time.

After the end of the route search (23), the pointer is traced from the target point v to create a route to the TV (2).
4).

PathFind (TV, v) TV is a set of nodes on the tree; v is a target point; ｛A Search (TV, v);... (23) TV〜 = φ (24) TE〜 = φ ( 24) do ｛(24) TV = TV∪ ｛{v}; (24) p = trace back pointer (v); (24) TE〜 = TE∪ ｛{(p, v)}; (24) v = p;... (24)｝ while (v! ； TV); return T〜 [TV〜, TE〜]; Ａ A Search (TV, v) TV is a set of nodes on the tree; Target point; ｛CLOSED, OPEN is a set for storing clauses;… (25) OPEN = φ;… (25) CLOSED = φ;… (25) For each vertex i∈TV ｛… (25) OPEN … (25)｝ while (OPEN ≠ φ)… (26) ｉ i = PopMinCostVertex (OPEN);… (27) OPEN = OPEN ＼ ｛i｝;… (28) CLOSED = CLOSED ∪ ｛i｝ if (i == v) return;… (29) For each vertex j∈ADJOIN (i) ｛… (30) [arv dly, est dly, Clim] = GetObject (i, j, v); … (31) if (arv dly + est dly <Dr (v) &&… (32) arv dly <Dr (j) &&… (33) Clim <Clim (j)… (34)) {NewCost = arv dly + est dly;… (35) if (j! ∈ OPEN AND i! ∈ CLOSED) {… (36) OPEN = OPEN {j};… (37) OldCost (j) = NewCost…… (38) UpdateVertexParameter (i (39) trace back pointer (j) = i; ... (40) {else if (j OPEN)} ... (41) if (NewCost <OldCost (j) ｛... (42) OldCst (J ) = NewCost; ... (43) UpdateVertexParameter (i, j); ... (44) trace back pointer (j) = i; ... (45)｝ {else if (j ∈CLOSED) ∈… (46) if (NewCost < OldCst (j) ｛... (47) OPEN = OPEN∪ ｛j; ... (48) OldCost (j) = NewCost; ... (49) UpdateVertexParameter (i, j); ... (5 0) trace back pointer (j) = i; (51) The value used in the cost calculation and the evaluation of the constraint condition is determined by the following equation. arvdly is the delay time from the root s to the node i and the predicted delay time from j to the target v. Clim is a capacity generated on the path from the start point to node j.

[0075]

(Equation 6)

(Equation 7) In the parameter update, the parameter of the following section j is updated.

[0076]

(Equation 8) Next, an application example of the present method will be described. In an example in which the method is applied after the element arrangement processing, first, all elements are arranged (5).
2), a timing analysis is performed to find a net requiring a delay time longer than the required delay (53), a buffer is inserted and the net is divided by applying the proposed method (54), and a wiring process is performed (55).

[0077] Further, if the above-described method is used, it is possible to insert a buffer element with the minimum change of the wiring path for the data after wiring. FIG. 10 shows an example. FIG.
0 (A) is an example of data after wiring. From this information, a directed graph as shown in FIG. 10B is created.
Here, the nodes numbered in FIG.
Nodes corresponding to the same number of the element of 0 (B) and filled in black correspond to branch points of the wiring path.

For example, the section 101 in FIG.
The node 102 corresponds to the node 104 at the branch point 103 of 0 (A). Directed branches between nodes indicate that a wiring path exists between each element and the branch point in FIG. The directed graph of FIG. 10B is the same as that of FIG.
Has a buffer node and a buffer branch corresponding to a buffer element between nodes as in the directed graph of FIG. The parameters of the parasitic resistance and the parasitic capacitance given to the directed branch are obtained from the wiring length of the actual wiring path.

Next, a tree structure is constructed on the directed graph of FIG. 10B by using the above-described route search method. FIG.
An example of the tree structure obtained at 0 (C) is shown. g1 represents a buffer node used at the time of construction in the tree structure.

Finally, buffer element insertion and rewiring processing are performed from the tree structure of FIG. 10C. FIG. 10D shows final wiring processing and buffer element insertion results. Here, branch 2 connected to the buffer node in the tree of FIG.
Since the wiring paths corresponding to the branches other than 01 and 203 do not need to be re-wired because the path shape has not changed,
If wiring processing is performed only on the portions 205 and 207 corresponding to 201 and 203, a buffer element can be inserted.

FIG. 11 shows an example of a system configuration using the fan-out decomposition method according to the present invention. 301 is a layout processing device, 302 is a timing analysis device, 303 is a database that stores layout data and circuit information,
304 is a fan-out decomposition device according to the present invention. Since the fan-out decomposition processing according to the present invention can be applied at any stage of the layout, the timing analysis is performed in an arbitrary process of the layout processing using the system of FIG. And it is possible to decompose the fan-out.

[0082]

As described above, according to the method of the present invention, a net is represented by a directed graph in consideration of the arrangement position of elements, and a net topology is generated on a directed graph while performing delay calculation including wiring resistance. In addition, a search for a buffer insertion position can be performed, and a delay reduction effect is large, and fan-out decomposition that does not make layout processing difficult becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a proposed method of the present invention.

FIG. 2 is a diagram for explaining a route search process.

FIG. 3 is a diagram for explaining a method of arriving at a tree;

FIG. 4 is an example of the arrangement of elements.

FIG. 5 is a diagram for explaining generation of a directed edge of a directed graph.

FIG. 6 is a diagram for explaining a buffer node.

FIG. 7 is a circuit example for explaining a wiring delay;

FIG. 8 is a model for calculating a wiring delay;

FIG. 9 is a diagram for explaining fan-out decomposition.

FIG. 10 is a diagram for explaining an example of application of the present invention to data after wiring processing.

FIG. 11 is a system configuration diagram using the present invention.

[Explanation of symbols]

 g1 buffer node 201, 203 branch 301 layout processing device 302 timing analysis device 303 database 304 fan-out decomposition device

Claims (1)

(57) [Claims] 1. When performing a fan-out decomposition of a logic circuit, when creating a directed graph having nodes as logic elements, the X-coordinate of the logic element i has the same X coordinate as that of an arbitrary logic element i. A logic element having the closest distance from the logic element i among the logic elements having a larger Y coordinate, and a Y coordinate having the same X coordinate as the X coordinate of the logic element i and smaller than the Y coordinate of the logic element i. And a logic element having the same Y coordinate as the Y coordinate of the logic element i and having a larger X coordinate than the X coordinate of the logic element i. And a logic element having the same Y coordinate as the Y coordinate of the logic element i and having a smaller X coordinate than the X coordinate of the logic element i. Logic element with the shortest distance A logic element having the X-coordinate larger than the X-coordinate of the logic element i and the Y-coordinate larger than the Y-coordinate of the logic element i, which is closest to the logic element i; A logical element having the X coordinate larger than the coordinate and the Y coordinate smaller than the Y coordinate of the logical element i, the logical element having the shortest distance from the logical element i; the Y coordinate larger than the Y coordinate of the logical element i; Among the logic elements having an X coordinate larger than the X coordinate of the logic element i, a logic element closest to the logic element i, a Y coordinate larger than the Y coordinate of the logic element i, and an X coordinate of the logic element i A set of logic elements having the smallest distance from the logic element i among the logic elements having small X coordinates is represented by S
When defined as (i), the logical element set S
(C) extending a directed branch (i, j) from an arbitrary node i to a node j of the directed graph having the logic element as a node so as to extend a directed branch toward a node corresponding to the element included in (i). A node g corresponding to the buffer element; a directed branch (i, g) from the node i to the node g corresponding to the buffer element;
Adding a branch (g, j) from the node g corresponding to the buffer element to the previous node j to the directed graph; and a signal propagation time from an element that outputs a signal to a node on the directed graph corresponding to the logic element. And the step of carrying out the target node from a set of nodes other than the node corresponding to the element outputting the signal, and the directed branch on the directed graph from the node corresponding to the element outputting the signal to the target node. Step of estimating the signal propagation time from the node corresponding to the element to be output to the target node, and estimating the signal propagation time when following the direction of the directed graph on the directed graph. Constructing a tree structure by selecting branches and nodes whose values are equal to or less than the required value, and inserting into the logic circuit the same number of buffer elements as the number of nodes corresponding to the buffer elements on the tree structure Fanout decomposition method characterized by comprising the extent, the.