JP3275570B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP3275570B2 JP3275570B2 JP23911694A JP23911694A JP3275570B2 JP 3275570 B2 JP3275570 B2 JP 3275570B2 JP 23911694 A JP23911694 A JP 23911694A JP 23911694 A JP23911694 A JP 23911694A JP 3275570 B2 JP3275570 B2 JP 3275570B2
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- Japan
- Prior art keywords
- potential
- signal lines
- signal
- shorted
- short
- Prior art date
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- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体メモリ等のバス
ラインの駆動回路に好適な半導体集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit suitable for a bus line driving circuit such as a semiconductor memory.
【０００２】[0002]
【従来の技術】図４は従来のバスライン駆動回路を示す
半導体集積回路図である。図４で１〜４はバスライン、
５〜１２はクロックトインバータ、１３〜１６は負荷容
量である。2. Description of the Related Art FIG. 4 is a semiconductor integrated circuit diagram showing a conventional bus line driving circuit. 4, 1-4 are bus lines,
5 to 12 are clocked inverters, and 13 to 16 are load capacitances.
【０００３】動作を説明する。クロック信号をLからHに
すると、クロックトインバータ５〜８（駆動回路）がオ
ンするためバスライン１〜４に各々クロックトインバー
タ５〜８の入力に応じた信号が出力される。出力がされ
た信号は各々バスライン１〜４を伝達しクロックとイン
バータ９〜１２の入力となる。次にクロック信号をHか
らLにすると、クロックトインバータ５〜８がオフする
ためバスライン１〜４には出力信号に応じた電位が保持
される。The operation will be described. When the clock signal is changed from L to H, the clocked inverters 5 to 8 (drive circuits) are turned on, so that signals corresponding to the inputs of the clocked inverters 5 to 8 are output to the bus lines 1 to 4, respectively. The output signals are transmitted through the bus lines 1 to 4, respectively, and become the input of the clock and the inverters 9 to 12. Next, when the clock signal is changed from H to L, the clocked inverters 5 to 8 are turned off, so that the potentials corresponding to the output signals are held in the bus lines 1 to 4.
【０００４】[0004]
【発明が解決しようとする課題】上記従来技術では、一
般的には配線長が長いため、あるいは駆動すべき回路等
が付加されるためバスライン１〜４の負荷容量１３〜１
６が大きい。したがって、クロック信号がＬからＨにな
ったときに保持されている前の出力信号と反対の信号が
出力された場合には出力電位は電源電位Ｖｄｄ分の電位
変化をしなければならない。そのため、バスラインの信
号の伝達に時間がかかった。また、負荷容量が大きいの
で、その充放電のために消費電流が大きくなる問題があ
った。In the above-mentioned prior art, the load capacitances 13 to 1 of the bus lines 1 to 4 are generally large because the wiring length is long or a circuit to be driven is added.
6 is big. Therefore, when a signal opposite to the previous output signal held when the clock signal changes from L to H is output, the output potential must change by the power supply potential Vdd. Therefore, it took time to transmit the signal of the bus line. In addition, since the load capacity is large, there is a problem that current consumption increases due to charging and discharging.
【０００５】本発明はこの様な問題を解決するもので、
その目的とするところは信号の伝達の動作スピードを向
上させ、かつ、消費電流値の低減を図ることのできるバ
スラインの駆動回路を有する半導体集積回路を得ること
である。The present invention solves such a problem.
An object of the present invention is to provide a semiconductor integrated circuit having a bus line drive circuit capable of improving the operation speed of signal transmission and reducing a current consumption value.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体集積回路
は、複数の信号ラインと、入力信号に基づいて前記複数
の信号ラインをそれぞれ駆動する複数の駆動回路と、前
記入力信号の変化に先立って印加されるクロック信号に
応じて前記信号ラインと前記駆動回路との間を電気的に
切り離す手段と、それぞれの前記駆動回路から切り離さ
れた前記複数の信号ライン間を各々電気的に短絡する手
段と、短絡された前記複数の信号ラインが接続され、接
地電位を基準に前記短絡された前記複数の信号ラインの
電位を検出する電位検出手段と、短絡された前記複数の
信号ラインと前記接地電位との間に接続された電位供給
手段と、を具備し、短絡された前記複数の信号ラインの
電位が前記接地電位と電源電位との間の所定の中間電位
を上まわったことを前記電位検出手段が検出した場合
に、これに対応して、前記電位供給手段は短絡された前
記複数の信号ラインと前記接地電位との間を接続制御す
るよう構成したことを特徴とする。A semiconductor integrated circuit according to the present invention includes a plurality of signal lines, a plurality of drive circuits for respectively driving the plurality of signal lines based on an input signal, and prior to a change in the input signal. Means for electrically disconnecting the signal line from the drive circuit in response to a clock signal applied thereto, and means for electrically short-circuiting each of the plurality of signal lines disconnected from the respective drive circuits. And the plurality of shorted signal lines are connected,
Of the plurality of signal lines short-circuited with respect to ground potential.
And potential detection means for detecting a potential, anda potential supply means connected between said ground potential and said plurality of signal lines are short-circuited, shorted of the plurality of signal lines
If the potential is detected by the potential detection means that exceeded the predetermined intermediate potential between the ground potential and the power supply potential
In response to this, the potential supply means is configured to control connection between the plurality of shorted signal lines and the ground potential.
【０００７】また、本発明の半導体集積回路は、複数の
信号ラインと、 入力信号に基づいて前記複数の信号ラ
インをそれぞれ駆動する複数の駆動回路と、 前記入力
信号の変化に先立って印加されるクロック信号に応じて
前記信号ラインと前記駆動回路との間を電気的に切り離
す手段と、 それぞれの前記駆動回路から切り離された
前記複数の信号ライン間を各々電気的に短絡する手段
と、短絡された前記複数の信号ラインが接続され、電源
電位を基準に前記短絡された前記複数の信号ラインの電
位を検出する電位検出手段と、短絡された前記複数の信
号ラインと前記電源電位との間に接続された電位供給手
段と、を具備し、短絡された前記複数の信号ラインの電
位が前記電源電位と接地電位との間の所定の中間電位を
下まわったことを前記電位検出手段が検出した場合に、
これに対応して、前記電位供給手段は短絡された前記複
数の信号ラインと前記電源電位との間を接続制御するよ
う構成したことを特徴とする。In addition, a semiconductor integrated circuit according to the present invention has a plurality of signal lines, a plurality of drive circuits for respectively driving the plurality of signal lines based on an input signal, and a voltage applied prior to a change of the input signal. means for disconnecting electrically between said driving circuit and said signal line in response to the clock signal, and means for short-circuiting each electrically between each of the drive circuits from the detached plurality of signal lines are short-circuited Connected to the plurality of signal lines,
The potential of the plurality of signal lines short-circuited with reference to the potential.
And potential detection means for detecting the position, anda potential supply means connected between said power supply potential and the plurality of signal lines that are shorted, electric of said plurality of signal lines which are short-circuited
If the position is detected by the potential detection means that falls below a predetermined intermediate potential between the power supply potential and the ground potential,
Correspondingly, the potential supply means is configured to control connection between the plurality of shorted signal lines and the power supply potential.
【０００８】また、本発明の半導体集積回路は、複数の
信号ラインと、入力信号に基づいて前記複数の信号ライ
ンをそれぞれ駆動する複数の駆動回路と、前記入力信号
の変化に先立って印加されるクロック信号に応じて前記
信号ラインと前記駆動回路との間を電気的に切り離す手
段と、それぞれの前記駆動回路から切り離された前記複
数の信号ライン間を各々電気的に短絡する手段と、短絡
された前記複数の信号ラインが接続され、該短絡された
前記複数の信号ラインの電位を検出する電位検出手段
（２６、２８）と、短絡された前記複数の信号ラインと
電源電位との間に接続された第１の電位供給手段と、短
絡された前記複数の信号ラインと接地電位との間に接続
された第２の電位供給手段と、を具備し、短絡された前
記複数の信号ラインの電位が前記電源電位と前記接地電
位との間の第１の中間電位を下まわったことを前記電位
検出手段が検出した場合には、これに対応して、前記第
１の電位供給手段が前記短絡された前記複数の信号ライ
ンと前記電源電位との間を接続制御し、短絡された前記
複数の信号ラインの電位が前記接地電位と前記電源電位
との間の第２の中間電位（但し、第１の電位＜第２の電
位とする）を上まわったことを前記電位検出手段が検出
した場合には、これに対応して、前記第２の電位供給手
段が前記短絡された前記複数の信号ラインと前記接地電
位との間を接続制御し、短絡された前記複数の信号ライ
ンの電位が前記第１の電位と前記第２の電位との間にあ
ることを前記電位検出手段が検出した場合には、前記第
１及び前記第２の電位供給回路はいずれも接続制御しな
いよう構成したことを特徴とする。Further, the semiconductor integrated circuit of the present invention has a plurality of signal lines, a plurality of drive circuits respectively driving the plurality of signal lines based on an input signal, and is applied prior to a change in the input signal. means for disconnecting electrically between said driving circuit and said signal line in response to the clock signal, and means for short-circuiting each electrically between each of the drive circuits from the detached plurality of signal lines, short
The plurality of signal lines are connected, and the
Potential detecting means for detecting potentials of the plurality of signal lines
(26, 28), first potential supply means connected between the plurality of shorted signal lines and a power supply potential, and connected between the plurality of shorted signal lines and a ground potential. And a second potential supply means, wherein the potential of the shorted signal lines falls below a first intermediate potential between the power supply potential and the ground potential.
If the detecting means detects, the corresponding
One potential supply unit controls connection between the plurality of short-circuited signal lines and the power supply potential, and sets a short-circuit potential of the plurality of short-circuited signal lines between the ground potential and the power supply potential. The potential detecting means detects that the potential exceeds the intermediate potential of 2 (where, the first potential is smaller than the second potential).
In this case, the second potential supply means
Stage to the connection control between said ground potential and said shorted said plurality of signal lines, near between the potential of the short-circuited the plurality of signal lines and said first potential second potential
The first and second potential supply circuits are configured not to perform connection control when the potential detection means detects that the potential has been changed .
【０００９】また、本発明の半導体集積回路は、前記第
１及び第２の中間電位は、それぞれ前記電位検出手段を
構成する第１のトランジスタ（２５）及び第２のトラン
ジスタ（２９）のしきい値電位によって決定されること
を特徴とする。Further, in the semiconductor integrated circuit according to the present invention, the first and second intermediate potentials may be respectively set to a first transistor (25) and a second transistor constituting the potential detecting means.
It is determined by the threshold potential of the transistor (29) .
【００１０】[0010]
【作用】上記手段によれば、バスラインの電位を電位の
変化前に予め中間電位に設定しておくため、電位の変化
量が小さくなり高速動作と、電流値が低減できる。According to the above means, the potential of the bus line is preset to the intermediate potential before the potential is changed, so that the amount of change in the potential is reduced, so that the high-speed operation and the current value can be reduced.
【００１１】また、中間電位の設定にはバスラインに保
持されている電荷を利用するため、中間電位の設定に要
する電流は小さく低消費電力化が可能である。Since the electric charge held in the bus line is used for setting the intermediate potential, the current required for setting the intermediate potential is small and low power consumption can be achieved.
【００１２】[0012]
【実施例】図１は本発明の実施例を示す半導体集積回路
図である。図１で１〜４はバスライン、５〜１２はクロ
ックトインバータ、１３〜１６は負荷容量、１７はイン
バータ、１８〜２０はＰｃｈトランジスタ、２１〜２３
はＮｃｈトランジスタ、２４、２７は電位供給回路であ
り各々Ｐｃｈトランジスタ２５、２６、Ｎｃｈトランジ
スタ２８、２９より成る。FIG. 1 is a semiconductor integrated circuit diagram showing an embodiment of the present invention. 1, 1-4 are bus lines, 5-12 are clocked inverters, 13-16 are load capacitors, 17 is inverters, 18-20 are Pch transistors, 21-23
Is an Nch transistor, and 24 and 27 are potential supply circuits, which are composed of Pch transistors 25 and 26 and Nch transistors 28 and 29, respectively.
【００１３】動作を説明する。バスライン１〜４に各々
クロックトインバータ５〜８の入力に応じた信号が出力
がされている状態で、クロック信号をＨからＬにすると
クロックトインバータ５〜１２はオフ、トランジスタ１
８〜２３、２５、２９は全てオンになる。The operation will be described. When signals corresponding to the inputs of the clocked inverters 5 to 8 are being output to the bus lines 1 to 4, respectively, when the clock signal is changed from H to L, the clocked inverters 5 to 12 are turned off and the transistor 1
8 to 23, 25, and 29 are all turned on.
【００１４】説明を容易にするために負荷容量１３〜１
６の値が各々等しく、電位供給回路２４、２７が無い場
合を仮定する。まずトランジスタ１８〜２３がオンであ
るからバスライン１〜４は各々短絡され同電位となる。
この場合バスライン１〜４の電位レベルが全てＨの場合
は電位は電源電位Ｖｄｄのままであるが、バスライン１
〜４の電位レベルの内３本がＨの場合は短絡すると３／
４Ｖｄｄ、２本がＨの場合は１／２Ｖｄｄ、１本がＨの
場合は１／４Ｖｄｄ、全てがＬの場合は接地電位、０と
なる。For ease of explanation, load capacitances 13 to 1
It is assumed that the values of 6 are equal and the potential supply circuits 24 and 27 are not provided. First, since the transistors 18 to 23 are on, the bus lines 1 to 4 are respectively short-circuited and have the same potential.
In this case, when the potential levels of the bus lines 1 to 4 are all H, the potential remains at the power supply potential Vdd.
When three of the potential levels of ~ 4 are H, a short
4 Vdd, 1/2 Vdd when two are H, 1/4 Vdd when one is H, and ground potential when all are L, 0.
【００１５】次に電位供給回路２４、２７がある場合を
説明する。電位供給回路２４はトランジスタ２６のしき
い値電位をＶｔｈｐとするとバスラインの電位がＶｄｄ
−Ｖｔｈｐ以下であるとオンする。したがって、Ｖｔｈ
ｐを例えば１／２Ｖｄｄ＞Ｖｄｄ−Ｖｔｈｐ＞１／４Ｖ
ｄｄに成るように設定すると、バスライン１〜４の内１
本がＨの場合と、全てがＬの場合、バスラインの電位は
Ｖｄｄ−Ｖｔｈｐまで引き上げられる。同様に電位供給
回路２７はトランジスタ２８のしきい値電位をＶｔｈｎ
とするとバスラインの電位がＶｔｈｎ以上であるとオン
する。したがって、Ｖｔｈｎを例えば３／４Ｖｄｄ＞Ｖ
ｔｈｎ＞１／２Ｖｄｄに成るように設定すると、バスラ
イン１〜４の内３本がＨの場合と、全てがＨの場合、バ
スラインの電位はＶｔｈｎまで引き下げられる。バスラ
イン１〜４の内２本がＨの場合は電位供給回路２４、２
７は両方オフであるから１／２Ｖｄｄのままである。Next, the case where the potential supply circuits 24 and 27 are provided will be described. When the potential supply circuit 24 sets the threshold potential of the transistor 26 to Vthp, the potential of the bus line becomes Vdd.
Turns on when the voltage is −Vthp or less. Therefore, Vth
p is, for example, １ ／ Vdd> Vdd−Vthp >＞ V
dd, one of the bus lines 1 to 4
When the book is H and when all are L, the potential of the bus line is raised to Vdd-Vthp. Similarly, the potential supply circuit 27 sets the threshold potential of the transistor 28 to Vthn.
When the potential of the bus line is equal to or higher than Vthn, it turns on. Therefore, Vthn is set to, for example, 3/4 Vdd> V
When the setting is made so that thn> 1/2 Vdd, the potential of the bus lines is reduced to Vthn when three of the bus lines 1 to 4 are H and when all are H. When two of the bus lines 1 to 4 are H, the potential supply circuits 24, 2
7 remains at 1/2 Vdd because both are off.
【００１６】次にクロック信号をＬからＨにするとクロ
ックトインバータ５〜１２はオン、トランジスタ１８〜
２３、２５、２９は全てオフになりバスライン間の短絡
も解除される。バスライン１〜４にはクロックトインバ
ータ５〜８の新たな入力に応じた信号が出力されるが、
その電位の変化量は出力信号がＨの場合はＶｄｄ−Ｖｔ
ｈｎ、１／２Ｖｄｄ、Ｖｔｈｐの何れかであり、出力が
Ｌの場合はＶｄｄ−Ｖｔｈｐ、１／２Ｖｄｄ、Ｖｔｈｎ
のいずれかとなる。Next, when the clock signal is changed from L to H, the clocked inverters 5 to 12 are turned on, and the transistors 18 to 18 are turned on.
23, 25 and 29 are all turned off and the short circuit between the bus lines is also released. Signals corresponding to the new inputs of the clocked inverters 5 to 8 are output to the bus lines 1 to 4,
The amount of change in the potential is Vdd-Vt when the output signal is H.
hn, Ｖ Vdd, or Vthp, and when the output is L, Vdd−Vthp, Ｖ Vdd, Vthn
Will be one of
【００１７】したがって、図２に示すように出力電位は
従来例のようにＶｄｄ分の変化をする必要がなくその分
（Δｔ分）バスラインの信号の伝達の高速化が可能とな
る。また、電位変化量が小さくなるためその分負荷容量
を充放電するための消費電流値を低減できる。Therefore, as shown in FIG. 2, the output potential does not need to change by Vdd as in the conventional example, and the transmission of the signal of the bus line can be speeded up by that much (Δt). Further, since the amount of change in potential is small, the current consumption for charging and discharging the load capacitance can be reduced accordingly.
【００１８】また、電位の設定には、バスラインを短絡
することによってバスラインに保持されている総電荷を
分割した形で利用するため、電位の設定に要する電流は
小さく低消費電力化が可能である。Further, in setting the potential, the total electric charge held in the bus line is used in a divided form by shorting the bus line, so that the current required for setting the potential is small and low power consumption can be achieved. It is.
【００１９】また、電位供給回路２４、２７は同時には
オンしないためここに流れる貫通電流はない。Since the potential supply circuits 24 and 27 are not turned on at the same time, there is no through current flowing here.
【００２０】尚、本実施例では簡単のため４本のバスラ
インで説明したがこれは４本に限らず複数であれば何本
であっても良い。In this embodiment, four bus lines have been described for simplicity. However, the number of bus lines is not limited to four and may be any number as long as a plurality of bus lines are provided.
【００２１】また、複数の配線とそれに伴う負荷容量が
あればバスラインという名称にとらわれることなく本実
施例が適応できる。Further, if there are a plurality of wirings and associated load capacitances, the present embodiment can be applied irrespective of the name of the bus line.
【００２２】また、Ｖｔｈｐの設定は例えば１／４Ｖｄ
ｄ＞Ｖｄｄ−Ｖｔｈｐ＞０、Ｖｔｈｎの設定は例えばＶ
ｄｄ＞Ｖｔｈｎ＞３／４Ｖｄｄであっても良く、同様の
効果がある。The setting of Vthp is, for example, 1/4 Vd
The setting of d>Vdd−Vthp> 0 and Vthn is, for example, V
dd>Vthn> 3 / 4Vdd, and the same effect is obtained.
【００２３】また、電位供給回路２４、２７は同時には
オンしない設定であるが、例えばトランジスタ２６、２
８がなく電位供給回路２４、２７を同時にオンさせて、
バスラインをある中間電位に設定してもそこに流れる貫
通電流が増えるが高速動作に対しては効果がある。The potential supply circuits 24 and 27 are set not to be turned on at the same time.
8 and turn on the potential supply circuits 24 and 27 simultaneously,
Even if the bus line is set at a certain intermediate potential, the through current flowing there increases, but this is effective for high-speed operation.
【００２４】また、電位供給回路２４、２７は必ずしも
両方必要ではなく、例えば電位供給回路２４だけの場合
は出力信号がＨからＬに切り替わる場合の高速動作に対
して効果がある。The potential supply circuits 24 and 27 are not necessarily required. For example, only the potential supply circuit 24 is effective for a high-speed operation when the output signal switches from H to L.
【００２５】また、Ｖｔｈｐ、Ｖｔｈｎを作るのに特別
なしきい値電位を持つトランジスタ２６、２８を使用し
たが、図３に示すようにノーマルなＰｃｈトランジスタ
３０〜３２あるいはＮｃｈトランジスタ３３〜３５を各
々ダイオード接続させて、それらのしきい値電位の和と
して作っても良い。Although transistors 26 and 28 having special threshold potentials are used to generate Vthp and Vthn, as shown in FIG. 3, normal Pch transistors 30 to 32 or Nch transistors 33 to 35 are diode-connected, respectively. They may be connected and made as the sum of their threshold potentials.
【００２６】[0026]
【発明の効果】以上述べた様に本発明によれば、バスラ
インの電位を電位の変化前に予め中間電位に設定してお
くため、電位の変化量が小さくなり信号の伝達の高速動
作が可能となる。また、電流値が低減できる。As described above, according to the present invention, the potential of the bus line is previously set to the intermediate potential before the potential change, so that the amount of change in the potential is reduced and the high speed operation of signal transmission is achieved. It becomes possible. Further, the current value can be reduced.
【００２７】また、中間電位の設定にはバスラインに保
持されている電荷を利用するため、中間電位の設定に要
する電流は小さく低消費電力化に対して有効となる。Since the electric charge held in the bus line is used for setting the intermediate potential, the current required for setting the intermediate potential is small, which is effective for reducing the power consumption.
【図１】本発明の実施例における半導体集積回路図。FIG. 1 is a semiconductor integrated circuit diagram according to an embodiment of the present invention.
【図２】本発明の実施例における電位変化図。FIG. 2 is a potential change diagram according to the embodiment of the present invention.
【図３】本発明の実施例における第２の電位供給回路
図。FIG. 3 is a second potential supply circuit diagram according to the embodiment of the present invention.
【図４】従来の実施例における半導体集積回路図。FIG. 4 is a diagram of a semiconductor integrated circuit in a conventional example.
１〜４ バスライン ５〜１２ クロックトインバータ １３〜１６ 負荷容量 １７ インバータ １８〜２０、２５、２６ Ｐｃｈトランジスタ ２１〜２３、２８、２９ Ｎｃｈトランジスタ ２４、２７ 電位供給回路 1-4 Bus line 5-12 Clocked inverter 13-16 Load capacitance 17 Inverter 18-20, 25, 26 Pch transistor 21-23, 28, 29 Nch transistor 24, 27 Potential supply circuit
Claims (4)
動する複数の駆動回路と、 前記入力信号の変化に先立って印加されるクロック信号
に応じて前記信号ラインと前記駆動回路との間を電気的
に切り離す手段と、 それぞれの前記駆動回路から切り離された前記複数の信
号ライン間を各々電気的に短絡する手段と、短絡された前記複数の信号ラインが接続され、接地電位
を基準に前記短絡された前記複数の信号ラインの電位を
検出する電位検出手段と、 短絡された前記複数の信号ラインと前記接地電位との間
に接続された電位供給手段と、を具備し、 短絡された前記複数の信号ラインの電位が前記接地電位
と電源電位との間の所定の中間電位を上まわったことを
前記電位検出手段が検出した場合に、これに対応して、
前記電位供給手段は短絡された前記複数の信号ラインと
前記接地電位との間を接続制御するよう構成したことを
特徴とする半導体集積回路。A plurality of signal lines; a plurality of driving circuits for respectively driving the plurality of signal lines based on an input signal; and a plurality of signal lines in response to a clock signal applied prior to a change in the input signal. Means for electrically disconnecting the plurality of signal lines from the drive circuit, means for electrically shorting between the plurality of signal lines disconnected from the respective drive circuits, and the plurality of shorted signal lines being connected. And ground potential
The potential of the plurality of shorted signal lines with reference to
Potential detecting means for detecting, and a potential supplying means connected between the plurality of short-circuited signal lines and the ground potential, wherein the potentials of the plurality of short-circuited signal lines are equal to the ground potential. that exceeded the predetermined intermediate potential between the power supply potential
When the potential detecting means detects, in response to this,
2. The semiconductor integrated circuit according to claim 1, wherein said potential supply means controls connection between said plurality of short-circuited signal lines and said ground potential.
動する複数の駆動回路と、 前記入力信号の変化に先立って印加されるクロック信号
に応じて前記信号ラインと前記駆動回路との間を電気的
に切り離す手段と、 それぞれの前記駆動回路から切り離された前記複数の信
号ライン間を各々電気的に短絡する手段と、短絡された前記複数の信号ラインが接続され、電源電位
を基準に前記短絡された前記複数の信号ラインの電位を
検出する電位検出手段と、 短絡された前記複数の信号ラインと前記電源電位との間
に接続された電位供給手段と、を具備し、 短絡された前記複数の信号ラインの電位が前記電源電位
と接地電位との間の所定の中間電位を下まわったことを
前記電位検出手段が検出した場合に、これに対 応して、
前記電位供給手段は短絡された前記複数の信号ラインと
前記電源電位との間を接続制御するよう構成したことを
特徴とする半導体集積回路。2. A plurality of signal lines, a plurality of drive circuits for respectively driving the plurality of signal lines based on an input signal, and the signal line according to a clock signal applied prior to a change in the input signal. Means for electrically disconnecting the plurality of signal lines from the drive circuit, means for electrically shorting between the plurality of signal lines disconnected from the respective drive circuits, and the plurality of shorted signal lines being connected. Power supply potential
The potential of the plurality of shorted signal lines with reference to
Potential detecting means for detecting, and a potential supply means connected between the plurality of shorted signal lines and the power supply potential, wherein the shorted potentials of the plurality of signal lines are equal to the power supply potential. That the voltage falls below a predetermined intermediate potential with the ground potential.
When the potential detected by the detecting means and corresponds to,
2. The semiconductor integrated circuit according to claim 1, wherein said potential supply means controls connection between said plurality of short-circuited signal lines and said power supply potential.
動する複数の駆動回路と、 前記入力信号の変化に先立って印加されるクロック信号
に応じて前記信号ラインと前記駆動回路との間を電気的
に切り離す手段と、 それぞれの前記駆動回路から切り離された前記複数の信
号ライン間を各々電気的に短絡する手段と、短絡された前記複数の信号ラインが接続され、該短絡さ
れた前記複数の信号ラインの電位を検出する電位検出手
段（２６、２８）と、 短絡された前記複数の信号ラインと電源電位との間に接
続された第１の電位供給手段と、 短絡された前記複数の信号ラインと接地電位との間に接
続された第２の電位供給手段と、を具備し、 短絡された前記複数の信号ラインの電位が前記電源電位
と前記接地電位との間の第１の中間電位を下まわったこ
とを前記電位検出手段が検出した場合には、これに対応
して、前記第１の電位供給手段が前記短絡された前記複
数の信号ラインと前記電源電位との間を接続制御し、 短絡された前記複数の信号ラインの電位が前記接地電位
と前記電源電位との間の第２の中間電位（但し、第１の
電位＜第２の電位とする）を上まわったことを前記電位
検出手段が検出した場合には、これに対応して、前記第
２の電位供給手段が前記短絡された前記複数の信号ライ
ンと前記接地電位との間を接続制御し、 短絡された前記複数の信号ラインの電位が前記第１の電
位と前記第２の電位との間にあることを前記電位検出手
段が検出した場合には、前記第１及び前記第２の電位供
給回路はいずれも接続制御しないよう構成したことを特
徴とする半導体集積回路。3. A plurality of signal lines, a plurality of drive circuits respectively driving the plurality of signal lines based on an input signal, and the signal line according to a clock signal applied prior to a change in the input signal. Means for electrically disconnecting the plurality of signal lines from the drive circuit, means for electrically shorting between the plurality of signal lines disconnected from the respective drive circuits, and the plurality of shorted signal lines being connected. The short circuit
Potential detecting means for detecting the potentials of the plurality of signal lines
A stage (26, 28), first potential supply means connected between the plurality of shorted signal lines and a power supply potential, and connection between the plurality of shorted signal lines and a ground potential; comprising a second potential supply means being, and this potential of shorted said plurality of signal lines falls below the first intermediate potential between the ground potential and the power supply potential
When the potential detecting means detects
The first potential supply means controls connection between the plurality of short-circuited signal lines and the power supply potential so that the short-circuited potentials of the plurality of signal lines are equal to the ground potential and the power supply potential. That the potential exceeds a second intermediate potential (here, first potential <second potential).
If the detecting means detects, the corresponding
2 potential control means controls connection between the plurality of short-circuited signal lines and the ground potential, and the short-circuited potentials of the plurality of signal lines are equal to the first potential and the second potential. Between the electric potential detecting means
If the stage is detected, the semiconductor integrated circuit characterized by being configured so as not to connect control both said first and said second potential supply circuit.
れ前記電位検出手段を構成する第１のトランジスタ（２
５）及び第２のトランジスタ（２９）のしきい値電位に
よって決定されることを特徴とする請求項３記載の半導
体集積回路。Wherein said first and second intermediate potential, it
It is a first transistor constituting the potential detecting means (2
4. The semiconductor integrated circuit according to claim 3, wherein the threshold voltage is determined by 5) and the threshold potential of the second transistor .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23911694A JP3275570B2 (en) | 1994-10-03 | 1994-10-03 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23911694A JP3275570B2 (en) | 1994-10-03 | 1994-10-03 | Semiconductor integrated circuit |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001266363A Division JP3541822B2 (en) | 2001-09-03 | 2001-09-03 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08102655A JPH08102655A (en) | 1996-04-16 |
| JP3275570B2 true JP3275570B2 (en) | 2002-04-15 |
Family
ID=17040039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23911694A Expired - Fee Related JP3275570B2 (en) | 1994-10-03 | 1994-10-03 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3275570B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2083044A1 (en) | 2008-01-23 | 2009-07-29 | Reagens S.p.A. | Composition for stabilizing halogen-containing polymers |
| EP2151475A1 (en) | 2008-08-01 | 2010-02-10 | Reagens S.p.A. | Composition comprising sodium formate for stabilizing halogen-containing polymers |
| EP2404960A1 (en) | 2010-07-08 | 2012-01-11 | Reagens S.p.A. | Stabilizing composition for halogen-containing polymers |
| EP2662403A1 (en) | 2012-05-11 | 2013-11-13 | Reagens S.p.A. | Stabilizing resin formulation of halogen-containing polymers |
| EP3243869A1 (en) | 2016-05-12 | 2017-11-15 | Reagens S.p.A. | Compositions and products for stabilizing halogen-containing polymers |
| WO2020053157A1 (en) | 2018-09-10 | 2020-03-19 | Reagens S.P.A. | A stabilized chlorinated polyvinylchloride and an article made therefrom |
| WO2024175568A1 (en) | 2023-02-20 | 2024-08-29 | Reagen S.P.A. | Stabilizing composition for halogen-containing polymers |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3177960B2 (en) | 1998-02-18 | 2001-06-18 | 日本電気株式会社 | Signal change acceleration bus drive circuit |
-
1994
- 1994-10-03 JP JP23911694A patent/JP3275570B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2083044A1 (en) | 2008-01-23 | 2009-07-29 | Reagens S.p.A. | Composition for stabilizing halogen-containing polymers |
| EP2151475A1 (en) | 2008-08-01 | 2010-02-10 | Reagens S.p.A. | Composition comprising sodium formate for stabilizing halogen-containing polymers |
| EP2404960A1 (en) | 2010-07-08 | 2012-01-11 | Reagens S.p.A. | Stabilizing composition for halogen-containing polymers |
| WO2012004377A1 (en) | 2010-07-08 | 2012-01-12 | Reagens S.P.A. | Stabilizing composition for halogen-containing polymers |
| EP2662403A1 (en) | 2012-05-11 | 2013-11-13 | Reagens S.p.A. | Stabilizing resin formulation of halogen-containing polymers |
| EP3243869A1 (en) | 2016-05-12 | 2017-11-15 | Reagens S.p.A. | Compositions and products for stabilizing halogen-containing polymers |
| WO2020053157A1 (en) | 2018-09-10 | 2020-03-19 | Reagens S.P.A. | A stabilized chlorinated polyvinylchloride and an article made therefrom |
| WO2024175568A1 (en) | 2023-02-20 | 2024-08-29 | Reagen S.P.A. | Stabilizing composition for halogen-containing polymers |
| WO2024175174A1 (en) | 2023-02-20 | 2024-08-29 | Reagens S.P.A. | Stabilizing composition for halogen-containing polymers |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08102655A (en) | 1996-04-16 |
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