JP3266764B2 - A / D conversion input interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion input interface circuit for converting an analog signal from a potentiometer into a signal that can be input to an A / D terminal of a CPU.

[0002]

2. Description of the Related Art In speed control of a traction motor of an electric vehicle, a potentiometer is mounted on a pedal or a lever corresponding to an accelerator pedal for operating a throttle valve in an internal combustion engine vehicle, and an analog signal from the potentiometer is transmitted to a CPU by a CPU. In some cases, the drive of the motor is controlled after A / D conversion.

FIG. 4 shows an example of a circuit configuration from the potentiometer to the CPU at this time. In this circuit, each terminal of the resistance element of the potentiometer 2 is connected to the power supply and the ground, respectively, and the output line from the slider is connected to the power supply at the node A via the resistor R1. Thus, the displacement of the slider of the potentiometer 2 linked to the pedal or lever operated by the driver is detected as a change in the voltage value. An analog signal represented by this voltage value is supplied to a voltage follower circuit 4 composed of an operational amplifier IC1 and a resistor R for limiting a current to the CPU 3.
8 is input to the A / D terminal of the CPU 3 via the A / D conversion processing input interface circuit 21 composed of

[0004]

By the way, in such a conventional input interface circuit 21 for A / D conversion processing, for example, the lead lines L1, L2, L3 from the potentiometer 2 and the lead lines L1, L2 If a short circuit or disconnection occurs in the connector 7 connecting L3 to the power supply, the CPU 3 and the ground, or the potentiometer 2 is damaged, if the power supply voltage is, for example, 5V, the A / D terminal of the CPU 3 The applied voltage is 5V
Or 0V. For example, in the connector 7, a first terminal P1 for connecting a lead wire L1 connected to one end of the resistance element of the potentiometer 2 to a power supply,
When the lead L2 connected to the slider is short-circuited to the second terminal P2 connecting the CPU 3, the input voltage becomes 5V. On the other hand, when the second terminal P2 and the third terminal P3 that connects the lead L3 connected to the other end of the resistance element to the ground are short-circuited, the input voltage becomes 0V. If any of the lead wires L1, L2, L3 is disconnected, the input voltage becomes 5V.

If the CPU 3 attempts to detect the above-mentioned abnormality based on the input voltage, it is necessary to use, for example, a rated input in the CPU 3 in order to make it possible to reliably determine whether the motor is in a stopped state or in a maximum speed state in a normal state. If the lower limit of the voltage range is 0 V and the upper limit is 5 V, the input voltage in the stopped state, which is the minimum in normal operation, is set to 0.5 V, and the input voltage in the maximum speed state, which is the maximum, is set to 4.5 V. However, in this case, the CPU 3
During the / D conversion, while the digital value allocated to the portion below 0.5 V and the portion exceeding 4.5 V are wasted, the number of states of the digital value used for the normal state detection is reduced, so that the detection is performed. There is an inconvenience that the resolution is reduced.

[0006] The present invention has been devised to solve such disadvantages of the prior art, and its main objects are as follows.
An object of the present invention is to provide an input interface circuit for A / D conversion processing configured to be able to reliably determine an abnormality without lowering the detection resolution in a normal state.

[0007]

According to the present invention, an analog signal from a potentiometer is converted to a C signal.
A for converting to a signal that can be input to the A / D terminal of the PU
An input interface circuit for / D conversion processing, wherein the analog signal from the potentiometer in a normal state fluctuates over a range from near the lowest value to near the highest value in the rated input voltage range of the CPU. A voltage amplifying means for amplifying a voltage, and an output of the voltage amplifying means at the time of abnormality due to a short circuit or disconnection affecting the analog signal, a predetermined voltage capable of recognizing the maximum value when the analog signal of power supply voltage level is generated. A voltage limiting means for limiting to a predetermined voltage level at which the minimum value can be recognized when the analog signal of the ground level is generated. It is achieved by doing.

[0008]

With this configuration, the voltage amplifying means amplifies the input voltage of the CPU so as to fluctuate over substantially the entire range of the rated input voltage range, thereby avoiding a decrease in the normal detection resolution. . On the other hand, when an analog signal of a power supply voltage level or a ground level is input to the voltage amplifying means for amplifying the analog signal in such a way as to be short-circuited or disconnected in a connector or a lead wire, the output becomes excessive. Is limited by voltage limiting means to protect the CPU. At this time, since the input voltage of the CPU is outside the rated input voltage range and is limited to a voltage level at which the highest value or the lowest value can be recognized, the input voltage is changed to a digital value of either all 0s or all 1s. A / D conversion can be performed reliably.
It is enough to secure the state. In this way, it is possible to reliably discriminate between the abnormal state and the normal state without substantially lowering the detection resolution in the normal state. For example, in the case of 8 bits, 254 states obtained by subtracting 2 states for abnormality detection from 256 states can be used for signal detection in a normal state.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction of the present invention will be described below in detail with reference to specific embodiments shown in the accompanying drawings.

FIG. 1 shows an input interface circuit for A / D conversion processing to which the present invention is applied. The input interface circuit 1 converts an analog signal from the potentiometer 2 into a signal that can be input to an A / D terminal of the CPU 3, and includes a voltage follower unit 4, a voltage amplifying unit 5, and a voltage limiting unit 6. Have. The signal from the potentiometer 2 is transmitted to the input interface circuit 1
Is the same as the above-described conventional circuit configuration (see FIG. 4), and a detailed description thereof will be omitted.

In the voltage follower section 4, the potentiometer 2
Is connected to the positive-phase input terminal of the operational amplifier IC1, and the output side node B is connected to the negative-phase input terminal. This operational amplifier IC1 has, for example, a voltage of ± 1.
It operates with a positive and negative power supply of 2V (dual power supply type). The negative power supply side may be grounded (single power supply type).

The voltage amplifier 5 includes an operational amplifier IC2 and variable resistors VR1 and VR for fine adjustment of offset and gain.
2 and resistors R2 to R7. Operational amplifier I
C2 is ± V (V) (V = 5 + 1.5 or more, for example, 1
It operates with the positive and negative power supplies of 2). An output line from the voltage follower unit 4 is connected to a positive-phase input terminal of the operational amplifier IC2 via a resistor R2. This resistor R2 and the operational amplifier IC
2 has a resistor R at node C.
3 is grounded.

On the other hand, the negative-phase input terminal of the operational amplifier IC2 is connected to the slider of the variable resistor VR1 via the resistor R4. One end of the variable resistor VR1 is connected to a power supply (5 V) via a resistor R5, and the other end is grounded.
A node D between the resistor R4 and the negative-phase input terminal of the operational amplifier IC2 is connected to a slider of the variable resistor VR2 via a resistor R6. One end of the resistance element of the variable resistor VR2 is connected to the node E of the output line of the operational amplifier IC2, and the other end is grounded via a resistor R7. The output line of the voltage amplifying unit 5 thus configured is connected to the voltage limiting unit 6 via a resistor R8 for preventing an excessive current from being generated.

The voltage limiting section 6 has a cathode connected to a power source (5).
V2), a diode D1 and a diode D2 whose anode is grounded.
Are connected in series across a node F to which the output line of the resistor R8 is connected. The diodes D1 and D2 are C
It is a low voltage drop type that satisfies the input standard V _CC ± 0.5 (V) of PU3. The output line of the voltage limiter 5 connected to the node F is connected to a capacitor C1 whose other end is grounded at the node G. The capacitor C1 constitutes a noise filter together with the resistor R8, and absorbs application of a surge voltage until the diodes D1 and D2 operate.

Here, a potentiometer 2 having a maximum resistance value of 5,000 Ω incorporated in a pedal or lever operated by a driver (not shown), for example, has a resistance value of a minimum resistance according to the operation of the pedal or lever. Value R _L = 100
(Ω) to the maximum resistance value R _H = 1,100 (Ω). At this time, if the power supply voltage is 5V,
The output voltage of the voltage follower unit 3, that is, the input voltage V _IN of the voltage amplifying unit 5 varies between 0.1V and 1.1V.

This is amplified by the voltage amplifier 5 to a predetermined output voltage V _OUT . Now, assuming that the rated input voltage range in which the A / D conversion is accurately performed in the CPU 3 is from 0 V to 5 V, for example, the output voltage V _OUT is amplified so as to fluctuate between 0.2 V and 4.8 V ( (See FIG. 2). That is, the minimum input voltage V _INL = 0.1 becomes the minimum output voltage V _OUTL = 0.2, and the maximum input voltage V _INH = 1.1
Is set to the maximum output voltage V _OUTH = 4.8, the amplifier gain G of the operational amplifier IC2 and the offset adjustment V _OFS are set. This amplifier gain G
Is (4.8-0.2) / (1.1-0.1) = 4.6
(Times), and the offset adjustment V _OFS is 0.2-0.
From 1 = G × V _OFS , V _OFS = 21.7 (mV).

As described above, when the output voltage V _OUT of the voltage amplifying unit 5 in the normal state is set to fluctuate between 0.2 V and 4.8 V, the connector 2 and the lead wires L1 and L
When a short circuit or disconnection occurs in 2.L3 or the like, the output voltage V _OUT tends to indicate a voltage value exceeding the input standard of the CPU 3. For example, if the first and second terminals P1 and P2 of the connector 2 are short-circuited, or if any of the lead wires L1, L2 and L3 is broken, the input voltage V _IN of the voltage amplifying unit 5 becomes approximately 5V. _Therefore, the output voltage V _OUT of the voltage amplifier 5 becomes (5
+ V _OFS ) × G, which far exceeds 5V. At this time, the current flows to the power supply side via the resistor R10 and the diode D1, and as a result, the input voltage _{VA / D} to the CPU 3 is 5 + VF _(D1) (VF _(D1) is the forward voltage of the diode D1 _). Descent).

The second and third terminals P of the connector 7
When 2 · P3 is short-circuited, the input voltage V _IN of the voltage amplification unit 5 becomes approximately 0 V, and the output voltage V _OUT becomes (0−V _OFS ) × G.
As a result, the voltage falls below 0V. At this time, since a current flows from the ground via the diode D2 and the resistor R10, the input voltage _{VA / D} to the CPU 3 is 0-VF _(D2) (V
_{F (D2)} is the forward voltage drop of the diode D2). In this way, the input voltage V _{A / D} to the CPU 3 is limited to within the input standard, and the CPU 3 is protected.

On the other hand, the input voltage V _{A / D} to the CPU 3 at the time of abnormality is 5 <V _{A / D} ≦ 5 +
Since VF _(D1) satisfies 0−VF _(D2) ≦ V _{A / D} <0 in the low determination mode, the input voltage V
_{The A / D} is reliably A / D converted to a digital value of either all 0 or all 1. Therefore, it is sufficient to secure two states for abnormality detection. For example, in the case of 8 bits, 254 states obtained by subtracting two states for abnormality detection from 256 states can be used for signal detection in a normal state. The resolution hardly decreases.

The voltage follower 4 and the voltage amplifier 5 may be replaced with a low-pass filter 12 and a voltage amplifier 13, respectively, as shown in FIG.
The low-pass filter section 12 includes a resistor R9 connected to the voltage follower section 4.
R10 and capacitors C2 and C3 are added, and the voltage amplifying unit 13 is obtained by providing the voltage amplifying unit 5 with a capacitor C4 in parallel with the resistor R6.

[0021]

As described above, according to the present invention, it is possible to reliably determine an abnormal state such as a short circuit or a disconnection, and to avoid a decrease in resolution in a normal state. In addition, since the resistance fluctuation range of the potentiometer can be set arbitrarily, it is not necessary to strictly adjust the movable ranges of the potentiometer when assembling the potentiometer to the pedal or lever operated by the driver, and the degree of freedom in design is reduced. The advantage of improvement is obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an input interface circuit for A / D conversion processing configured according to the present invention.

FIG. 2 is a graph showing a voltage amplification state in the voltage amplification unit shown in FIG.

FIG. 3 is a circuit diagram showing another example of the input interface circuit for A / D conversion processing configured according to the present invention.

FIG. 4 is a circuit diagram showing a conventional input interface circuit for A / D conversion processing.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input interface circuit 2 Potentiometer 3 CPU 4 Voltage follower part 5 Voltage amplifying part 6 Voltage limiting part 7 Connector 11 Input interface circuit 12 Low-pass filter part 13 Voltage amplifying part 21 Input interface circuits L1-L3 Lead wires P1-P3 Terminals R1-R10 Resistor IC1 ・ IC2 Operational amplifier C1-C4 Capacitor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G08C 13/00 G01D 3/08 G06F 3/05 351 H03M 1/12 H03M 1/18

Claims (1)

(57) [Claims] An input interface circuit for A / D conversion processing for converting an analog signal from a potentiometer into a signal that can be input to an A / D terminal of a CPU, wherein the analog signal from the potentiometer in a normal state is provided. Voltage amplifying means for amplifying the voltage so as to vary over a range from the vicinity of the lowest value to the vicinity of the highest value in the rated input voltage range of the CPU; The output of the voltage amplifying means is limited to a predetermined voltage level at which the highest value can be recognized when the analog signal of the power supply voltage level is generated, and the predetermined value at which the lowest value can be recognized when the analog signal at the ground level is generated. And a voltage limiting means for limiting to a voltage level of A / D conversion processing. Interface circuit.