JP3264267B2 - Integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly to a method of reducing the change in potential difference between adjacent wirings by changing the potential of adjacent wirings in phase, thereby reducing the amount of charge / discharge for the capacitance between the wirings. The present invention relates to an improvement in power consumption in a signal driving unit for a wiring having a configuration using a method of improving a signal transmission speed by performing a signal transmission.

[0002]

2. Description of the Related Art Integrated circuit devices have hitherto increased the operating speed of circuits by increasing the speed of active elements. However, in recent years, the speed of active elements has become sufficiently high, and the signal propagation speed of wiring has become an important factor in determining the operation speed of an integrated circuit device. One of the major factors in lowering the signal transmission speed of a wiring is a wiring capacitance which is a parasitic capacitance generated in the wiring, and it is necessary to reduce the wiring capacitance in order to increase the signal transmission speed.

In order to respond to this demand, for example, Japanese Patent Application Laid-Open Nos. 5-82646, 8-306867, and JP-B-2-24375 disclose wirings for transmitting signals to circuit elements, in other words. There is disclosed an integrated circuit device in which upper and lower lines, left and right lines, or a combination of these lines to be driven are arranged, and adjacent lines which change in phase to reduce the wiring capacitance of the lines to be driven are arranged adjacently.

FIG. 8 is a sectional view schematically showing a main part of a large-scale integrated circuit disclosed in Japanese Patent Publication No. 2-24375. In FIG. 8, reference numeral 812 denotes a wiring to be driven;
Reference numerals 3 and 814 denote wirings which are provided to reduce the horizontal capacitance of the wiring 812 and are driven in the same phase.
Reference numeral 16 denotes a buffer provided for driving the wirings 813 and 814 in the same phase as the wiring 812. A driving circuit 817 drives the wiring 812. An interlayer film 805 separates the substrate and the wiring. That is, the wirings 813 and 814 whose potential changes in the same phase as the wiring 812 to be driven
Are arranged on both sides of the wiring 812. These wirings 813 and 814 are connected to buffers 815 and 816
Is driven in the same phase as the wiring 812 to be driven. Therefore, a change in the potential difference between the wirings 812 and 814 adjacent to the wiring 812 is reduced, so that the effective capacitance between the wirings can be reduced, and the effective capacitance of the wiring 812 is the capacitance between the wiring 812 and the substrate 804. Only, and the signal transmission speed of the wiring 812 to be driven can be increased.

Japanese Patent Application Laid-Open No. 6-61351 discloses that
There is disclosed a method in which the above-mentioned method is improved and provided with driving means for sending out a drive signal of a wiring which changes in phase adjacent to a wiring to be driven earlier than a wiring to be driven.

FIG. 9 is a circuit diagram of a driving circuit which is a main part of an integrated circuit disclosed in Japanese Patent Application Laid-Open No. 6-61351.

In FIG. 9, reference numeral 912 denotes a wiring to be driven;
21 is a sub wiring arranged adjacent to the wiring 912, 92
Reference numerals 3 and 924 denote buffers for driving the wirings 912 and 921, respectively. The input of each buffer is connected to the same signal source. Buffers 923, 924
The sub-wiring 921 can be driven ahead of the wiring 912 to be driven by appropriately adjusting the driving capability of the sub-wiring 912. The signal on the wiring 912 to be driven is accelerated.

[0008]

In applications such as portable computers, there are cases where high-speed operation is required and cases where low-speed operation is required but power consumption is desired to be reduced. However, in the above-described conventional technique, in such an application, the potential of the adjacent wiring is always changed even in a state where signals can be transmitted without changing the potential of the adjacent wiring, such as during a low-speed operation. There is a problem that power for changing the potential is wasted.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and an integrated circuit device capable of transmitting a signal to be transmitted at a high speed at a high speed operation and reducing power consumption at a low speed operation. Is to provide.

[0010]

SUMMARY OF THE INVENTION An integrated circuit device according to the present invention is an integrated circuit device having a plurality of circuit elements,
A first wiring for transmitting a signal to these circuit elements, a second wiring arranged substantially adjacent to the first wiring, and a first drive for outputting a transmission signal to the first wiring Means, second driving means for controlling the potential of the second wiring, and controlling the second driving means to change the potential of the second wiring in phase with the potential of the first wiring; A selection means for selecting whether to hold the potential at a constant level, and an internal or external signal
And selection control means for controlling the selection means based on the control information .

Further , another integrated circuit device according to the present invention
An integrated circuit device having a number of circuit elements, wherein the circuit
A first wiring for transmitting a signal to the element, and a first wiring
A second wiring disposed substantially adjacent to the first wiring;
A first driving unit that outputs the signal to a wiring;
Second driving means for controlling the potential of the wiring of
Controlling the driving means to change the potential of the second wiring to the first level;
Change in the same phase as the wiring potential or keep it at a constant potential
Comprising selecting means for selecting either the at least the second
The driving means is constituted by a three-state buffer.

At this time , the apparatus may further include selection control means for controlling the selection means based on a signal from inside or outside of the integrated circuit device.

The selection control means includes an operation mode setting means for setting whether or not the operation mode of the integrated circuit device is the high-speed operation mode. The potential of the second wiring is set to the first
The selection means may be controlled so as to change the potential of the wiring in the same phase.

Alternatively, the other selection control means may include the first
Speed detecting means for detecting the transmission speed of a signal transmitted by the wiring, and a speed for comparing whether or not the transmission speed of the signal detected by the speed detecting means is higher than a predetermined speed and outputting a comparison result And comparing the potential of the second wiring by the output signal from the speed comparing means only when the transmission speed of the signal to be transmitted on the first wiring is higher than a predetermined speed. It is preferable that the selection control means controls the selection means so as to change the potential in the same phase as the potential.

According to the integrated circuit device of the present invention, (a) when the transmission speed of a signal transmitted through the first wiring is high, the first
By changing the potential of the first wiring and the potential of the second wiring in the same phase, there is no change in the potential difference between the first wiring and the second wiring, and the potential difference between the first wiring and the second wiring is eliminated. (B) When it is desired to reduce the power consumption of the integrated circuit device, the signal transmission speed of the first wiring can be reduced. Although the transmission speed is limited, the potential of the second wiring is controlled by controlling the second driving means, and the power consumption of the second driving means and the power for charging / discharging the wiring capacity of the second wiring are suppressed. It is possible,
They can be selected as needed.

[0016]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a main part of an integrated circuit device according to a first embodiment of the present invention.

Referring to FIG. 1, the integrated circuit device according to the present embodiment includes at least a first wiring 111 for transmitting a signal to a circuit element (not shown) in the integrated circuit device, and a first wiring 111. 111 disposed substantially adjacent to
, A first driving unit 110 whose output is connected to the first wiring 111 and outputs a transmission signal, and a second driving unit 120 whose output is connected to the second wiring 121 and 131, respectively. , 130 and the second driving means 12
There is provided a selection means 140 for controlling whether the potentials of the second wirings 121 and 131 are changed in the same phase as the potential of the first wiring 111 or kept at a constant potential by controlling each of the first and second wirings 0 and 130.

A signal to be transmitted from a signal source (not shown) is transmitted to a first driving unit 11 through a signal line 112.
It is also input to the selection means 140 together with 0.

The selection means 140 is connected to a control signal from the outside of the integrated circuit device or a circuit inside the integrated circuit device, for example, a register circuit for storing an operation speed state (neither is shown). Select signal line 14
2 to output a signal from the signal line 112 or a constant potential (in this case, “low level (L)”).
(Potential) is output. Also, the selection means 140
Is output from the second driving unit 12 by the connection wiring 141.
0,130 are connected to the inputs.

Further, both the first driving means 110 and the second driving means 120 and 130 can obtain the same output for the same input.

Next, the operation of the integrated circuit device according to the first embodiment will be described.

First, when it is necessary to transmit a signal to be transmitted at a high speed, the selection means 140 is made to select to output a signal from the signal line 112 as shown in FIG. Thereby, the signal lines 112 are also provided to the second driving units 120 and 130.
From the second driving means 120 and 130
Second wirings 121 and 131 connected to respective outputs
Of the first wiring 111 changes in phase with the potential of the first wiring 111 connected to the output of the first driver 110 which receives the signal from the signal line 112 and outputs the transmission signal.

Therefore, the power consumed by the second drive means 120 and 130 and the power required to charge and discharge the wiring capacitance of each of the second wirings 121 and 131 are required, so that the power consumption of the integrated circuit device is slightly increased. , The first wiring 111 and the second
Since there is no change in the potential difference between the first and second wirings 121 and 131, the first driving unit 110 does not need to charge and discharge these inter-wiring capacitances.
Since the effective wiring capacitance (floating capacitance) of the first wiring 111 is significantly reduced, the speed of signal transmission by the first wiring 111 can be increased.

If it is not necessary to transmit signals at high speed and it is desired to reduce the power consumption of the integrated circuit device, the selecting means 1
40 is selected so as to output an “L” potential, and when a constant “L” potential is input to the second driving means 120 and 130, the second driving means 120 and 130 are connected to the respective outputs. Since the potentials of the second wirings 121 and 131 are also constant at the “L” potential, the first driving means 110 sees
The stray capacitance of the wiring 111 includes the inter-wiring capacitance between the first wiring 111 and each of the second wirings 121 and 131 and becomes large, so that high-speed signal transmission becomes difficult. The power consumed by the means 120 and 130 and the power for charging and discharging the wiring capacitance of each of the second wirings 121 and 131 become unnecessary, and the power consumption of the integrated circuit device is reduced.

At this time, the second wirings 121 and 131 function as a shield for the first wiring 111, and an effect of reducing noise can be obtained particularly at a low voltage operation where the dynamic range is reduced.

FIG. 2 is a circuit diagram of a specific example of the integrated circuit device according to the first embodiment.

The selecting means is a two-input NAND gate (2NAN).
D) 240, 250, the first drive means is an inversion buffer (INV) 210, and the second drive means is INV 220, 2
30. 2 NAND 240, 25
The outputs of 0 are connected to the inputs of INVs 220 and 230, respectively.

The 2NAND 260 is inserted before the INV 210 in order to match the output timing of the INV 210 with the output timing of the INVs 220 and 230.

One input of each of the two NANDs 240 and 250 is connected to the selection signal line 142, and the other input of each is connected to the signal line 112.

The "H" potential is always applied to one input of the 2NAND 260, and the other input is connected to the signal line 112.
Twelve signals to be transmitted are always inverted. Since the signal output from the 2NAND 260 is input to the INV 110, the potential of the first wiring 111 connected to the output of the INV 110 always changes in phase with the signal to be transmitted.

When a “high level (H)” potential is applied to the selection signal line 142, the 2NANDs 240 and 250
Outputs a signal obtained by inverting the signal on the signal line 112. The signals are further inverted by the INVs 220 and 230, and the second wirings 121 and 121 connected to the respective outputs are output.
The potential of each of the signals 131 changes in phase with the signal to be transmitted on the signal line 112.

When the "L" potential is applied to the selection signal line 142, the "H" potential is always output from the 2NANDs 240 and 250, and the INVs 220 and 230
Output the "L" potential which is further inverted from this, the potentials of the second wirings 121 and 131 become constant at the "L" potential. At this time, the second wirings 121 and 131 are
It functions as a shield for the first wiring 111.

FIG. 3 is a timing chart showing the above operation contents. A signal to be transmitted is always transmitted to the first wiring 111 irrespective of the selection signal, and the potential of each of the second wirings 121 and 131 is such that the selection signal line 142 is “H”.
The potential changes in phase with the signal to be transmitted, and the second wirings 121 and 131 are fixed at a constant potential (“L” potential) when the selection signal line 142 is at “L” potential.

FIG. 4 is a schematic diagram showing an inter-wiring capacitance distribution when the potential of each of the second wirings 121 and 131 is changed in the same phase as the potential of the first wiring.

The first wiring 111, the second wiring 121, 1
31 is provided on the substrate 501 via the insulating film 510, and the upper part is covered with the insulating protective film 511. Further, it is assumed that the first wiring 111 and the second wirings 121 and 131 are all wired with the same wiring width.

C10 is the first wiring 111 and the substrate 501
, C20 and C30 are the capacitances between the second wirings 121 and 131 and the substrate 501, C21 and C30, respectively.
31 denotes a first wiring 111 and a second wiring 12
1, 131. Also, C2X,
C3X is a capacitance between wirings between the second wirings 121 and 131 and a wiring other than the first wiring 111, respectively. In this case, the capacitances C21 and C31 between the wirings
And the potentials of the second wirings 121 and 131 change in the same phase, the potential difference between the wirings does not occur and becomes substantially zero.

FIG. 5 is a schematic diagram showing the capacitance distribution between the wirings when the potential change of each of the second wirings 121 and 131 is stopped and set to a constant potential. Note that the same parts as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

In this case, although the inter-wiring capacitances C21 and C31 between the first wiring 111 and the second wirings 121 and 131 are charged and discharged, the connection between the second wirings 121 and 131 and the substrate 501 is performed. Capacitors C20 and C30 between the first wiring 1
The inter-wiring capacitances C2X and C3X between wirings other than 11 are
Since the potential change of each of the second wirings 121 and 131 is stopped and is kept at a constant potential, charging and discharging are not performed.

That is, when the potential of each of the second wirings 121 and 131 is changed in the same phase as the potential of the first wiring 111, the total capacitance of the capacitors C20, C30, C2X and C3X is
Normally, the sum of the capacitances C21 and C31 when the potential change of each of the second wirings 121 and 131 is stopped and the potential is kept constant is larger. That is, when the potential change of each of the second wirings 121 and 131 is stopped, the power is reduced by that amount, and the operating power of the second driving means 120 and 130 is also reduced. Can be planned.

FIG. 6 is a block diagram showing a configuration of a main part of an integrated circuit device according to a second embodiment of the present invention. In addition, parts common to FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

Referring to FIG. 6, in the integrated circuit device according to the present embodiment, the selection control means 600, which receives a signal from the inside or outside of the integrated circuit device from the control signal line 601 based on this signal, selects the selection means 140 Is controlling.

For example, when the selection control means 600 includes an operation mode setting means for setting whether or not the operation mode of the integrated circuit device is the high-speed operation mode, and when the operation mode setting means sets the high-speed operation mode, By outputting the “H” potential and the “L” potential at other times to the selection signal line 142, it is connected to the output of each of the second driving means 120 and 130 only when the integrated circuit device is in the high-speed operation mode. The potentials of the second wirings 121 and 131 can be changed in the same phase as the potential of the first wiring 111 connected to the output of the first driver 110.

Further, the selection control means 600 includes a speed detecting means for detecting at least a transmission speed of a signal transmitted by the first wiring, and a transmission speed detected by the speed detecting means is higher than a predetermined speed. It is also possible to include a speed comparing means for comparing whether or not to output the comparison result and to output a comparison result, and to output the comparison result of the speed comparing means to the selection signal line 142. In this case, the speed comparing means sets the “H” potential when the transmission speed of the signal to be transmitted through the first wiring 111 is higher than a predetermined speed, and sets the “L” potential when the transmission speed is equal to or lower than the predetermined speed. May be output to the selection signal line 142.

Thus, the integrated circuit device according to the present invention provides the second drive unit 12 only when the transmission speed of a signal to be transmitted on the first wiring 111 is higher than a predetermined speed.
0, 130, the second wiring 121 connected to each output,
The potential of 131 can be changed in the same phase as the potential of the first wiring 111 connected to the output of the first driver 110.

In the above description, the second wirings 121, 131
Second driving means 120, 130 for changing respective potentials
Has been described as a normal buffer or an inversion buffer, but at least the second driving means 120 and 130 may be formed as a three-state buffer. Thereby, power can be more effectively reduced.

For example, it is assumed that the integrated circuit device of the present invention has a wiring arrangement as shown in FIG. That is, the second wirings 721 and 721, which are arranged adjacent to both sides of the first wiring 711 connected to the first driving means (not shown) and which are connected to the second driving means (not shown). It is assumed that proximity signal lines 722 and 732 exist further outside 731. With such a wiring arrangement, the second wiring 721,
A case where the potential of 731 is not changed will be described.

First, the output of the second driving means is set to GND (or VDD), and the potentials of the second wirings 721 and 731 are set to G.
When fixed to ND (or VDD), the first wiring 71
The buffer connected to 1 needs power for charging and discharging the inter-wiring capacitance between the first wiring 711 and the second wirings 721 and 731.

On the other hand, when the second driving means is set to high impedance (floating state), the second wiring 7
21 and 731 are also in a high impedance state, and the buffer connected to the first wiring 711 needs power for charging and discharging the capacitance between the first wiring 711 and the adjacent signal lines 722 and 732.

The proximity signal lines 722 and 723 are physically separated from the second wirings 721 and 731 when viewed from the first wiring 711, and the capacitance between the wirings is inversely proportional to the distance between the wirings. Therefore, the power required for charging and discharging can be further reduced as compared with the case where the potentials of the second wirings 721 and 731 are fixed to GND (or VDD).

In each of the above-described embodiments, an example is described in which the second wirings arranged adjacent to the first wiring are arranged one by one on the left and right sides of the first wiring. However, they may be arranged vertically, diagonally, or a combination thereof. The same applies to a plane conductor instead of wiring.

The signal to be transmitted in the present invention is not limited to an analog signal and a digital signal, but can be applied to all electric signal transmission applications.

It should be noted that the present invention is not limited to the above embodiments, and each embodiment can be appropriately changed within the scope of the technical idea of the present invention.

[0054]

As described above, according to the present invention,
Since it is possible to select whether or not to change the potential of the second wiring disposed adjacent to the first wiring for transmitting a signal in the same phase as the signal of the first wiring, it is possible to reduce the signal transmission speed during high-speed operation. The effect of suppressing power consumption early and at the time of low-speed operation can be obtained.

When the second wiring is kept at a constant potential, the second wiring functions as a shield for the first wiring, and the effect of suppressing noise to the first wiring can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a main part of an integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a specific circuit block diagram of a main part of the integrated circuit device according to the first embodiment of the present invention.

FIG. 3 shows a first wiring according to the first embodiment of the present invention;
5 is a timing chart showing potential changes of a second wiring and a selection signal line.

FIG. 4 is a schematic diagram of a wiring capacitance distribution when the potential of a second wiring is changed in the same phase as a signal transmitted through the first wiring in the first embodiment of the present invention.

FIG. 5 is a schematic diagram of a wiring capacitance distribution when a change in potential of a second wiring is stopped in the first embodiment of the present invention.

FIG. 6 is a schematic block diagram illustrating a main part of an integrated circuit device according to a second embodiment of the present invention.

FIG. 7 is a schematic perspective view showing a wiring arrangement example of the integrated circuit device of the present invention.

FIG. 8 is a sectional view schematically showing a main part of a large-scale integrated circuit disclosed in Japanese Patent Publication No. 24375/1990.

FIG. 9 is a circuit diagram of a driving circuit for an integrated circuit disclosed in Japanese Patent Application Laid-Open No. 6-61351.

[Explanation of symbols]

110 first driving means 111, 711 first wiring 112 signal line 120, 130 second driving means 121, 131, 721, 731 second wiring 140 selecting means 141 connection wiring 142 selection signal line 210, 220, 230 Inverting buffer (INV) 240, 250, 260 2-input NAND gate (2N
AND) 501, 804 Substrate 510 Insulating film 511 Insulating protective film 600 Selection control means 601 Control signal line 722, 732 Proximity signal line 805 Interlayer film 812, 912 Wiring to be driven 813, 814 Wiring 815, 816, 923, 924 Buffer 817 Drive circuit 921 Sub wiring

Claims (7)

(57) [Claims] 1. An integrated circuit device having a plurality of circuit elements, comprising: (a) a first wiring for transmitting a signal to the circuit element; and (b) substantially adjacent to the first wiring. (C) first driving means for outputting the signal to the first wiring, (d) second driving means for controlling the potential of the second wiring, (e) selecting means for selecting whether to hold the potential of the second of the second wiring by controlling the drive means to a constant potential alters in the first wiring and the potential of the same phase, (f The said selection means based on an internal or external signal;
And a selection control means for controlling the operation of the integrated circuit device. 2. An integrated circuit device having a plurality of circuit elements.
There, the disposed substantially adjacent to the first wiring and, (b) said first wiring for transmitting a signal to (a) the circuit element
And second interconnection, a first drive for outputting the signal to said first wire (c)
And (d) second driving means for controlling a potential of the second wiring.
If, (e) said second by controlling the drive means of the second wiring
Whether the potential is changed in phase with the potential of the first wiring;
Comprising selecting means for selecting whether to keep to a constant potential, the integrated circuit device, wherein at least said second drive means is a three-state buffer. 3. The integrated circuit device according to claim 2, wherein the selector controls the output of the second driver to a high impedance state when the potential of the second wiring is not changed. 4. The integrated circuit device according to claim 2 or 3 further comprising a selection control means for controlling the selection means on the basis of a signal from the internal or external of the integrated circuit device. 5. The selection control means includes an operation mode setting means for setting whether or not the operation mode is a high-speed operation mode, and the second mode is set only when the operation mode setting means sets the high-speed operation mode.
Integrated circuit device according to claim 1 or 4, the potential of the wiring controlling the selection means to change the first wiring and the potential of the same phase. 6. A selection control means for detecting a transmission rate of a signal transmitted by a first wiring, and a determination whether the transmission rate detected by the speed detection means is higher than a predetermined rate. and a speed comparison means for outputting a comparison result of the comparison whether the integrated circuit device according to claim 1 or 4 for controlling the selection means by the output signal from the speed comparison means. 7. The selection control means sets the potential of the second wiring in the same phase as the potential of the first wiring only when the transmission speed of a signal to be transmitted by the first wiring is faster than a predetermined speed. 7. The integrated circuit device according to claim 6 , wherein the selection unit is controlled so as to change.