JP3260406B2 - Complementary emitter follower - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary emitter follower circuit using a bipolar transistor, and more particularly to a complementary emitter follower circuit suitable for use in a large-scale semiconductor digital integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a circuit using a bipolar transistor (that is, only a bipolar transistor or a bipolar transistor and a CM) is used.
In driving a heavy load in a BiCMOS circuit combined with an OS, an emitter-follower circuit (hereinafter, referred to as a “BiCMOS circuit”) will
(Abbreviated as an emitter follower) is generally used. The emitter follower is, for example, as shown in FIG.
It comprises a transistor Q and a current source I. Of course, the current source can be replaced by a resistor.

As is well known, in an emitter follower, a transistor Q charges a load CL when a signal rises.
Since the current flowing from the transistor Q flows in proportion to the exponential function of the voltage between the base and the emitter, if the rise of the emitter voltage is slightly slower than the base voltage, the voltage between the base and the emitter increases and a large current flows. Charges quickly. Therefore, the rise is very fast. Also,
Since a large current flows basically only at the time of rising transition, both low power consumption and high speed can be achieved.

On the other hand, the fall time is determined by discharging only the current of the current source I. In general, this current must always flow for circuit operation. Becomes larger.

In a digital (pulse) circuit, an emitter follower is frequently used as an output stage of a logic circuit. For example, an ECL circuit as shown in FIG. 3 (having an emitter follower at an output unit) is exclusively used for a logic circuit and a high-speed internal memory circuit in a computer which emphasizes high speed, especially in a large computer and a supercomputer. In such a digital circuit, a large current only needs to flow at least during the transition of the fall in order to speed up the fall.
(A circuit that causes a large current to flow only during a transition at the time of a falling signal is hereinafter referred to as an active pull-down circuit.) Therefore, a desired output is obtained by making use of the fact that a positive and negative output is generated in ECL. To the emitter follower,
An active pull-down circuit that applies an output signal of the opposite polarity to the current source transistor via a capacitor, drives the current source transistor only when the signal falls, flows a large current, and discharges the load has been devised. ing.

FIG. 4 shows a typical circuit (two-input OR / NOR circuit) of such a conventional example. (Japanese Patent Laid-Open No. 61-8
8617, JP-A-62-72221). In this circuit, the OR output (collector of Q3) is connected to the emitter follower
A NOR output (collectors of Q1 and Q2) is applied to the base of the transistor Qef, while a base of the current source transistor QIS is applied to the base of the current source transistor QIS via a coupling capacitor CC. The bias in the steady state of the current source transistor QIS is determined by the resistors R3 and R4. Normally, at steady state, the bias is set so that very little or no current flows through QIS. When no current flows through the QIS, for example, a resistor is connected in parallel with the QIS as shown by a broken line so that a slight current always flows from the Qef. The emitter resistor R5 limits the current of the QIS, but there is no particular problem in operation even without it.

The circuit shown in FIG. 4 operates as follows. When a high-level signal is applied to one or both of the two inputs Vin1 and Vin2, Q1 or Q2 or both are turned on, so that the collector of Q3 goes high. When all the inputs at the high level are switched to the low level, the OR output (Q3
Is switched to a low level, and the NOR output (collectors of Q1 and Q2) is switched to a high level. The NOR signal switched to the high level is applied to the transistor QIS via the capacitor CC. As a result, QIS turns on and discharges the load CL with a large current. Therefore, the output Vout falls rapidly. Of course, in order to drive QIS at high speed, CC may not be driven directly by the collector of Q1 or the like, but may be driven via an emitter follower. If the connection of the emitter follower Qef and the drive signal of the current source QIS are reversed (the connection between OR and NOR is reversed), an output having a phase opposite to that of FIG. 4 can be obtained.

[0008]

By the way, the circuit of FIG. 4 has some basic problems. One is that it is extremely difficult to simultaneously achieve high-speed falling and cycle operations and low power consumption. This will be described with reference to the operation waveform of FIG. FIG. 5A shows the waveform of the input (Vin1 or Vin2) in FIG. When the input falls,
In response to this input, the NOR output rises as shown in FIG. Although not shown, the OR output (base voltage of Qef) falls. This NOR signal is coupled to the coupling capacitor CC.
And applied to the base of the QIS. As is well known, the signal is differentiated by C-coupling, so that the base voltage waveform of QIS is as shown in FIG. This waveform shows the value of CC and QIS
Is determined by the value of the impedance of the base node.
A discharge current flows from QIS in response to the base waveform, and output Vout falls at high speed. However, for load CL, CC
Is smaller than the required value, CL cannot be discharged sufficiently, so that the falling speed is not so high. On the other hand, load C
If CC is larger than a required value for L, a useless excessive discharge current flows, and an undershoot occurs in the output as shown in FIG. Therefore, power consumption increases. In addition, the possibility that the QIS will be saturated and the operation will be slow is increased. Therefore, the value of the coupling capacitor CC has an optimum value according to the load CL. It is inconvenient if it is too large or too small. Subsequently, when the input waveform (a) rises, the NOR output (b) falls, and the base voltage waveform of QIS becomes as shown in FIG. 5 (c). That is, in the case of rising, the voltage is suppressed by the clamping effect of the diode between the base and the emitter of the QIS as shown in FIG. 3C, but in the case of falling, there is nothing to suppress the voltage, so that FIG. As shown by the solid line, the output falls by almost the same amount as the fall of the NOR output. If the amount of fall is too large, the base voltage has not yet returned to a steady state when the subsequent pulse is applied, so the delay before QIS turns on increases and the amount of discharge current decreases. Become. That is, if the cycle time is short, not only does the start of discharge be delayed, but also a sufficient discharge current does not flow, and the fall of the subsequent output voltage is delayed. In order to avoid such cycle dependency, a diode D may be connected to the base of the QIS as shown by a broken line in FIG. With this configuration, the base voltage at the time of falling is clamped, and FIG.
And the effect of the cycle time is reduced. However, even if a diode is connected, it takes a considerable time to reach a steady state. In particular, if CC is increased to drive a large load capacity, the time required to return to a steady state increases, and the cycle dependency increases. In order to reduce the cycle dependency, the resistance values of the resistors R3 and R4 may be reduced in FIG. 4 or the diode D may be made conductive in a steady state. However, when the cycle dependency is reduced by reducing the impedance of the QIS bias circuit in this manner, power consumption increases, and the effect of using the active pull-down circuit is reduced.

Another problem with the circuit of FIG.
If external disturbance is applied to out, there is little ability to recover it. This will be described with reference to FIG. For example, as shown in FIG. 6 (a), when the output Vout is at a high level and positive noise is applied from the outside, the current source transistor QIS is off and the current is drawn to the emitter follower transistor Qef. Since there is no ability, it takes a very long time to return to the original level as shown by the solid line.

When a large load is distributed and its time constant is considerably longer than the switch time of the ECL, the output waveform falls once and rises again as shown in FIG. This is because the waveform falls near the output end due to the discharge current, but the load near the far end is not discharged. Therefore, after the discharge current is cut off, it rises again with the time constant of the load. The illustrated waveform is a waveform near the output end, but at the far end, the discharge current decreases before almost falling. Since the case where the wiring is long and the resistance is considerably large corresponds to such a case, it is difficult to use the active pull-down circuit as shown in FIG. 4 in this case.

On the other hand, a complementary emitter follower combining an npn transistor and a pnp transistor is known as a kind of active pull-down circuit which can avoid these problems, particularly the problem described with reference to FIG. FIG. 7 is a circuit diagram of an example of such a complementary emitter follower (Japanese Patent Application Laid-Open No. 63-171022). In this circuit, when the output goes high, the Vout terminal is charged through Qn. When the output changes to a low level, the Vout terminal is discharged through Qp.

By the way, the npn and pnp transistors Q
When n and Qp are connected in series, the voltage for driving each base needs to have a potential difference of 2VBE. In this example, two diodes are connected in series with the collector load of a current switch (amplifier) transistor, and Qn is determined by the potential difference between both ends, as is often used in conventional analog circuits.
And Qp. In this example, an increase in power consumption does not occur to obtain a potential difference of 2VBE. However, the collector voltage of the driving transistor is set to a desired signal amplitude +2 V
BE (ie, signal amplitude is 0.6V, VBE is 0.7V
(0.6 + 1.4 = 2 V). Therefore, there is a problem that the delay time increases. Also, there is a fatal problem as a logic circuit that the input and output levels do not match.

In FIG. 8 (JP-A-61-234122),
The base potential of the pnp transistor Qp is generated by shifting the level of the collector potential of the current switch by an appropriate potential between the resistor and the transistor. npn
If the base potentials of the pnp transistor and the pnp transistor are completely separated from each other by 2 VBE, a large current flows through the complementary emitter follower. Therefore, it is usually convenient to set this potential difference slightly smaller than 2 VBE. Such setting is difficult with the level shift circuit (two diodes) of FIG. In the circuit shown in FIG. 8, by appropriately selecting the value of the resistor connected to the base of the transistor for level shift, each base potential can be set to an optimum potential. However, in the circuit of FIG. 8, the response of the pnp transistor Qp cannot be freely increased. Because the response speed of Qp is determined by the time constant of the base of Qp, which is determined by the product of the resistance and the capacitance connected to the base. Accordingly, when the value of the resistor is reduced to reduce the time constant for the purpose of speeding up, the current flowing through the level shift circuit increases, and the current flows through the collector load resistor R2 of the current switch. For this reason, the output level decreases, and a desired level cannot be obtained. If only a current that does not affect the output level is passed through the level shift circuit, the base response of the pnp transistor Qp becomes very slow, and therefore the fall of the output voltage becomes very slow, so that the advantage of using the pnp transistor cannot be exhibited. .

FIG. 9 (JP-A-56-58326) shows a pnp without lowering the output level by a level shift circuit.
This is an example of a complementary emitter follower that can speed up the response of the transistor Qp. In this example, the level shift circuit includes an emitter follower and a diode,
The load resistance R2 has 1 / of the current flowing through the level shift circuit.
Since only hFE flows, a sufficient current can be supplied to the level shift circuit to speed up the response of Qp as necessary. However, in the circuit of FIG. 9, in order to make the responses of Qn and Qp the same, it is necessary to make the current flowing through the current switch and the current flowing through the level shift circuit substantially the same. Both power and speed will not change much.

In the complementary emitter follower described above, the output potential is always lower than the input potential. In many logic circuits, there is no problem because the input potential (collector potential) is the highest potential (0 V). However, when the collector potential is lower than this, it is often desired to make the output potential higher than the input. Therefore, there is a problem that the circuit of FIG. 9 cannot meet these requirements.

An object of the present invention is to solve the problems in the above various known examples. That is, an object is to provide an active pull-down circuit with low power consumption, high-speed operation, and high driving capability. More specifically, an object of the present invention is to provide a complementary emitter follower capable of driving a large load at a high speed even if the operating current of the current switch is reduced. Another object of the present invention is to provide a complementary emitter follower provided with a charging circuit (active pull-up circuit in terms of circuit operation) capable of increasing the output potential higher than the input potential.

[0017]

According to the present invention, there is provided a bipolar transistor (Qn, Qp) having different polarities, the emitters of which are connected to each other (VOUT) and the collectors correspond to each other. Power supply (VCC,
VEE), an input signal is directly input to the base (VBn) of one transistor (Qn), and a capacitor (Cc) is connected to the base (VBp) of the other transistor (Qp). , And a current source (IB) for bias current is connected to the base (VBp) of the other transistor (Qp). . (See FIG. 1).

[0018]

FIG. 4 shows a complementary emitter follower having a C-coupled connection between the base of one transistor and the input.
Thus, the C load can be driven without causing overdrive as in the case where C coupling is performed on the npn transistor. Therefore, there is an effect that power consumption can be reduced without consuming unnecessary power.

Further, since the transistor is not saturated, there is an effect that the operation speed can be increased.

Further, the bias circuit of the complementary emitter follower of the present invention only applies the base current. Therefore, unlike the conventional complementary emitter follower, unnecessary current for speeding up is caused to flow in the bias circuit, and a large amount of power is not consumed.

Further, by reversing the connection between the pnp and npn transistors, the output potential can be easily made higher than the input potential. Therefore, there is an effect that the degree of freedom in setting the potential is large. Further, a Darlington connection emitter follower can be easily configured. (FIG. 24 etc.). The Darlington-connected complementary emitter follower has the effect of driving a large C load at high speed. Also, since the load has little effect on the input stage, high-speed operation is possible even if the current in the current switch stage is reduced.

There is an effect that a high-speed gate can be realized with low power consumption.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The circuit of this embodiment operates as follows. First, it is assumed that the input VIN on the left side of the current switch is at a high level. In addition, the base of the transistor Q2 on the right has VI
It is assumed that an input VIN # having a polarity opposite to N or a reference voltage VBB is applied. (Here, VIN￣ represents a VIN bar with an overline above VIN.) At this time, since the left transistor Q1 is on and the right transistor Q2 is off, npn of the right emitter follower is turned off.
The base voltage VBn of the transistor Qn becomes high. Further, since the current IB is constantly drawn from the base of the pnp transistor Qp, the bias current always flows through the emitter of Qp. Therefore, the bias current IB of the pnp transistor flows through the npn transistor Qn as it is. That is, the complementary emitter follower Q
The bias current for p and Qn is determined only by IB. As can be seen from the circuit diagram, the output Vout is the voltage VBn
The base voltage VBp of Qp is further lower by 1 VBE. Therefore, the coupling capacitor CC
Is applied with a voltage of 2 VBE.

When the input VIN switches to a low level, Q2
Is turned on, and its collector voltage, that is, the voltage VBn, switches to a low level. Since the coupling capacitor CC is set to be larger than the parasitic capacitance of a transistor or the like, a change in the voltage VBn directly appears as a change in VBp. That is, even in the transient state of the voltage change, the coupling capacitor C
2VBE is always applied to C, and the output is switched while maintaining the potential difference.

In this embodiment, to drive the load capacitance connected to the output Vout, the coupling capacitor CC
Must be big enough for it. Even if the capacitor CC is sufficiently large, the circuit of the embodiment of FIG. 1 does not cause overdrive as described with reference to FIG. Therefore, no inconvenience is caused thereby. That is, no matter how large CC is, the potential difference between both ends is 2VBE
Irrespective of the magnitude of the load capacity. That is, when the output falls, the greater the load, the greater the discharge current from the transistor Qp. On the other hand, when the load is small, the discharge current from Qp automatically decreases. Therefore, the magnitude of CC should be at least a magnitude that can sufficiently drive the maximum load to be driven. When driving a small load, it is not necessary to pay special attention to the magnitude of CC (it is possible to keep it large). For example, when driving a load up to about 2 pF, a coupling capacitor of 0.1 μF is used.
What is necessary is just about 5 pF. With a value of 0.5 pF, a load in the range of approximately 0 to 2 pF can be driven at very high speed.

According to the circuit configuration of this embodiment, the power consumption of the bias circuit is very small. In the case of FIG. 1, the power consumption of the bias circuit is only due to the base current of the complementary emitter follower. This is necessary to keep a small bias current flowing through the complementary emitter follower. If a small amount of bias current is not supplied, the switching time will be slow. Further, since the active pull-down circuit used in the present invention uses a pnp transistor, there is an advantage that the active pull-down circuit is essentially resistant to noise on the output terminal, which is a problem of the conventional example. In addition,
The electric charge accumulated in the capacitor CC is discharged little by little at every switching. The diode DCL1 and the power supply VCL1 indicated by broken lines in FIG. 1 are for replenishing the charge lost by this discharge. In other words, when the voltage of CC decreases due to the discharge, when switching from the low level to the high level, the base voltage of Qp slightly increases accordingly. This is clamped to the original level by the diode DCL1. Generally, this diode is needed to speed up the cycle time. However, if the cycle is slow enough, this charging is done by IB,
No diode is needed. Conversely, VBE of the bipolar transistor becomes large at the time of switching when a large current flows, and at this time, the base voltage of Qp may be lower than at the time of steady state. To prevent this, DCL2 shown by the dotted line
And VCL2. Of course, these clamp circuits need not be connected if the above-mentioned inconveniences are not noticeable.

FIG. 10 is a circuit diagram showing one embodiment of the bias current circuit used in the embodiment of FIG. This is a current source circuit of a base current IB for determining a bias current. Reference numeral 101 denotes a current source indicated by IB in FIG. 1, and is constituted by one npn transistor QnB. The pnp transistor QpB has the same structure and the same characteristics as the pnp transistor Qp of FIG. 1 and has the same characteristics. A constant current source 10 is connected to the emitter of this QpB.
The current IBIAS is passed from Step 2. Therefore, from its base,
A base current IB necessary for flowing IBIAS flows. This IB flows to the diode-connected npn transistor QD. If npn transistor QnB has the same structure as QD, a current proportional to the ratio of the magnitude of QnB to QD flows through its collector. For example, if the size is the same, IB flows. This IB causes a desired bias current IBIAS to flow through the complementary emitter follower of FIG. Note that reference numeral 102 denotes an example of a constant current circuit for flowing IBIAS, and any other constant current circuit having a desired function may be used. (An example of another constant current circuit is shown in FIG. 11, for example.) The circuit of FIG. 10 uses a transistor having the same (or proportional) size as the transistor of the circuit of FIG. Bias current IBIAS
Have gained. Therefore, when the circuit shown in FIG. 1 and the circuit shown in FIG. 10 are formed on the same chip, it is only necessary to obtain desired pair characteristics in transistor characteristics on the chip. Therefore, even if the characteristics of the pnp transistor and the npn transistor vary between lots or chips, the design value IBI
AS can flow.

In FIG. 10, the transistors QpB and the like are shown as one transistor. When the number of current sources to be driven is small, for example, when hFE is 100 and the number of drives is 10 or less, the circuit of FIG. 10 may be used. However, when the number of current sources to be driven is larger than 10, the total sum of base currents flowing into the current source transistor QnB cannot be ignored compared to IB. In order to compensate for variations in hFE of the transistor, it is necessary to supply a current as close to the current IB as possible to QD. However, when the drive current increases, this condition does not hold. In such a case,
A large number of power supplies are arranged in FIG. 10 to reduce the number of current sources driven by one power supply. Alternatively, for example, n QpB and QD are connected in parallel, and nx is connected to the parallel-connected QpB.
What is necessary is just to let the current of IBIAS flow.

FIG. 12 illustrates the use of a complementary emitter follower with an active pull-down circuit of the present invention.
5 is an embodiment of a two-input ECL gate. Since the operation is the same as that of the embodiment of FIG. 1 except that the number of inputs is increased, a detailed description is omitted.

FIG. 13 is a circuit diagram of another embodiment of the present invention. This is because the input signal VIN1 applied to the base of the npn transistor Qn is connected to the pn via the coupling capacitor CC.
Input signal VIN applied to the base of p transistor Qp
2 is an embodiment in the case where the amplitudes are different.

FIG. 14 is a circuit diagram of an embodiment in which the circuit of FIG. 13 is applied to an ECL circuit. For example, in the circuit shown in FIG. 1 or the like, the amplitude of the signal applied to the base of the pnp transistor Qp may decrease because the signal is divided by CC and the parasitic capacitance. The embodiment of FIG. 14 compensates for this decrease in amplitude by using the circuit of the embodiment of FIG. 13 in an ECL circuit. In FIG. 14, the load resistance R of the current switch
2. Tap at an appropriate point of 2, and use an npn transistor Qn
Driving base. Therefore, the signal applied to the pnp transistor Qp has a larger amplitude than Qn,
It is possible to compensate for the decrease. However, for most applications, this compensation is not necessary and, of course, need not be used in that case.

FIG. 15 shows an embodiment in which the present invention is applied to an NTL gate circuit. The capacitors indicated by broken lines are for speeding up, but may or may not be operational. Since the operation of the NTL gate is well known, its description is omitted here. The operation of the active pull-down circuit is the same as in the previous embodiments.

FIG. 16 shows still another embodiment of the present invention. This embodiment is an example in which a bias circuit is inserted in parallel with the coupling capacitor CC. Since this circuit is an auxiliary for slightly correcting the bias condition, any circuit may be used. For example, by connecting one resistor in parallel with a capacitor, the bias condition of only the current source can be slightly changed. The advantage of the present invention cannot be obtained unless the bias conditions are changed slightly by such parallel circuits.

FIG. 17 shows an emitter follower according to the present invention.
This is an embodiment applied to a gate circuit composed of a bipolar transistor and a MOS transistor. M1 and M2 are load MOSs, and M3 is a current source MOS. An appropriate voltage is applied to the gate of M3 to flow a current. These MOS transistors may be any of an enhancement type, a depletion type, or a combination thereof. The operation of the complementary emitter follower is the same as that of the ECL circuit using only the bipolar.

FIG. 18 is a circuit diagram showing an embodiment of the present invention.
This is another embodiment applied to the gate circuit constituted by. 15 is obtained by replacing the load of the NTL of FIG. 15 with MOS transistors M3 and M4. By using the MOS transistor, the rise of the output can be accelerated. Further, the fall of the output can be accelerated by the capacitor CS connected by the broken line. However, this capacitor does not have to be operational.

FIG. 19 shows an embodiment in which the present invention is applied to a CMOS gate. Since a large current flows through the gate portion and the emitter follower basically only during a transition, a high-speed operation with very low power consumption can be obtained. In this embodiment, the output has a potential lower by 1 VBE than VCC. In order to match the output and the input well, it is preferable that the PMOSs M5 and M6 are of the enhancement type and the NMOSs M7 and M8 are of the depletion type. For example, assuming that the output amplitude is 0.8 V, the threshold voltages of M5 and M6 are set to, for example, -1.0 V
The threshold voltages of M7 and M8 are set to, for example, -1.
It is convenient to set it to about 4V.

In the above embodiment (for example, the combination of FIGS. 1 and 10), the pnp transistor is used with its collector connected to the power supply VEE.
In this case, there is no need to separate the collector of the pnp transistor from the p-substrate.

FIG. 20 is a sectional view of one embodiment of a pnp transistor used in the present invention. FIG. 20A shows a structure in which the collector is not separated from the p-type substrate, and can be used in the above embodiments. FIG. 20B shows a vertical pnp transistor having a normal structure in which the collector is separated from the substrate. When formed on the same chip as the npn transistor, in the structure of FIG. 20B, the thickness of the p-layer of the collector cannot be too large, so that the collector series resistance increases. Therefore, a high-performance pnp transistor is
It is relatively difficult to form simultaneously with n transistors. In the structure of FIG. 20A, a desired structure can be formed by using the p− layer and the p + layer as the collector. Therefore, FIG.
Compared with the structure of (b), a transistor with much higher performance can be easily configured. As described above, in the present invention, there is an advantage that a high-performance pnp transistor can be used.

In the above embodiment, the input signal is directly applied to the base of the npn transistor, while the signal is applied to the base of the pnp transistor via a capacitor.
Since the output voltage is output from the emitter of the npn transistor, it becomes lower than the input voltage. However, depending on the circuit, it may be desirable that the output voltage is higher than the input voltage. For example, in FIG. 3 etc., the power supply to which the collector load resistance is connected is a lower voltage instead of Vcc,
When the input of the complementary emitter follower is considerably lower than Vcc because the current switch or the like is formed by a pnp transistor, a potential higher than the input is often desired as the output voltage.

FIG. 21 shows another embodiment of the present invention suitable for such a case. In this embodiment, the input signal is p
The signal is directly input to the base of the np transistor, and is input to the base of the npn transistor via a capacitor. The base current source IB for flowing the bias current is
Connected to base of npn transistor. The power supply Vcc1,
Vcc2 needs to be set appropriately. These voltages may be supplied from the outside as necessary, or may be generated internally as described later in the description of FIG. The purpose of the clamping diode DCL is the same as the purpose of the clamping diode in FIG. As a base current source for this embodiment, for example, a circuit in which the npn and pnp transistors of FIG. 10 are exchanged can be used as shown below.

FIG. 22 is a circuit diagram of one embodiment of the bias current source used in the embodiment of FIG. The operation of this circuit is the same as that of FIG. 10 if the pnp and npn transistors are exchanged and the polarity of the power supply is reversed. Detailed description is omitted. However, depending on how much the output voltage Vout of FIG. 21 is raised, a positive voltage source is required as the power supplies Vcc1, Vc1, and Vc2 (this situation is the same as in FIG. 21). In that case, it is necessary to use an external positive power supply or generate the power inside the chip. A method for generating a positive voltage inside a chip is well known.

FIG. 23 is a configuration diagram of an example of an auxiliary power supply used in the embodiments of FIGS. 21 and 22. In FIG.
The output of the power supply signal generation circuit 111 is AC-coupled by a capacitor and rectified by the rectification circuit 112 to obtain a desired positive DC voltage. Any circuit may be used as the signal generation circuit 111. For example, 111 may be a multivibrator or a ring oscillator. Further, since a synchronous digital circuit always uses a clock signal, a clock buffer circuit may be used as 111 in FIG. Further, as the rectifier circuit 112, a simple rectifier circuit may be used depending on a desired voltage value, or an appropriate voltage doubler rectifier circuit such as a double voltage or triple voltage rectifier circuit may be used as necessary. These circuits are well known to those skilled in the art and need not be described in detail.

When the complementary emitter follower described above is used, the power consumption of the ECL circuit can be reduced by the amount reduced by the complementary emitter follower. The effect of the load capacitance on the collector time constant of the current switch is reduced to 1 / hFE by the emitter follower. However, the effect of the load capacity still remains. Therefore, the operation current of the current switch cannot be reduced for further high-speed operation. Further, in order to drive a large load at a higher speed, it is necessary to instantaneously supply a large current to the load. Since the diffusion capacitance of the transistor is proportional to the difference between the instantaneous maximum current and the steady-state current, the diffusion capacitance also increases. Therefore, in order to increase the speed, the current in the current switch cannot be reduced. When the C load is large,
The current flowing through the C-coupling portion increases. For this reason, it is necessary to increase the value of the coupling capacitor,
The chip area also increases. As described above, the discharge current from the capacitor CC also increases, and therefore, the diode D1 is also required.

FIG. 24 shows another embodiment of the present invention in which the points described above are improved. By connecting the emitter follower to Darlington, the load drive capability is improved and the characteristics are improved. The transistors Q1, Q2, Q3 constitute a current switch. Q4 and Q5 are Darlington first-stage complementary emitter followers. Q6 and Q7 are
Darlington second stage complementary emitter follower.
CC is a coupling capacitor for the PNP transistor Q5. I2 is a current source for determining the bias current of Q4 and Q5. The bias current flowing through Q4 and Q5 is diode D2,
Flows through D3. For example, the diodes D2 and D3 are formed using transistors having the same structure and the same size as the transistors Q6 and Q7. In this case, the bias current flowing through Q6 and Q7 is the same as the bias current of Q4 and Q5. If the area of the emitters of Q6 and Q7 is n times (n <= 1 or n> 1) the area of the emitters of D2 and D3, the transistor Q
6, the bias current of Q7 can be n times as large as that of transistors Q4 and Q5. Note that the diode D1 has a CC reduced by discharging.
And has the same purpose as the diode D1 in FIG.

In this embodiment, the effect of the load capacitance is about 1 / (hFExhFE) on the collector of the current switch.
Therefore, a large load can be driven with low power consumption and high speed. Also, charging and discharging from the capacitor in one switching operation is reduced. For this reason, the value of the capacitor can be reduced, and the diode D1 can usually be omitted.

FIG. 25 shows another embodiment of the present invention. pn
The p-transistors Q5 and Q6 are Darlington connected.
Q7 and diode D2 are bias circuits for Q4 and Q5. In order to stably bias even if there is a variation in transistor characteristics, the diode D2 is
It is desirable to use an np transistor. Also in this case, since the base current of the pnp transistor Q6 is extremely small, the capacity of the capacitor CC may be small. Also, the diode D1 is unnecessary in most cases.

FIG. 26 shows still another embodiment of the present invention in which a capacitor is connected in parallel with a diode. A capacitor CC2 is connected in parallel with the diodes D2 and D3. This CC2 is a coupling capacitor for the transistor Q7. Its purpose is the same as capacitor CC1 for transistor Q5. (However, normally, the charging and discharging of the transistor Q7 is sufficiently performed by the transistor Q5 or the diodes D2 and D3. Therefore, unlike the case of CC1, this capacitor CC2 is not necessary in most cases.) FIG. 9 is a still further embodiment of the present invention.
24 omits the diodes D2 and D3 in FIG. In this case, the bias current flowing through the transistors Q5 and Q6 is hFE times the bias current flowing through the transistors Q3 and Q4. In this embodiment, the bias currents of Q3 and Q4 are all Q
To avoid the base current of 6, a resistor or the like may be connected as shown by a dotted line instead of the diode in FIG. 24 to partially bypass the current.

In the embodiments shown in FIGS. 1 to 27, the output is taken only from the positive side of the current switch. Of course, it goes without saying that it can be taken out from the negative side if necessary. FIG. 28 and FIG.
The present invention is applied to a logic circuit other than the current switch,
This is another embodiment. FIG. 28 shows an embodiment in which the Darlington connection complementary emitter follower according to the present invention is applied to an NTL circuit. FIG. 29 shows an embodiment in which the Darlington connection complementary emitter follower according to the present invention is applied to a CMOS gate circuit.

In these embodiments, Darlington-connected transistors are used for both the npn and pnp transistors. However, if the purpose is to reduce the coupling capacitor CC or to use a clamp diode, only the pnp transistor should be Darlington-connected as shown in FIG. As can be seen from these embodiments, the present invention is effective even when added to various logic circuits.

The current source circuit of the base current IB for determining the bias current of the Darlington-connected complementary emitter follower of the present invention may be basically the same as the current source circuit shown in FIG. That is, 101 in FIG. 10 is the current source I2 shown in FIG. 24, and is constituted by one npn transistor QnB. The pnp transistor QpB is shown in FIG.
It is convenient that transistors having the same structure and the same size as the pnp transistor Q4 have the same characteristics. of course,
Even if the characteristics are slightly different, the operation does not matter. The constant current source 102 supplies IB to the collector of the pnp transistor.
Apply IAS current. Therefore, a base current IB necessary for flowing IBIAS as a collector current flows from the base. This current flows through the diode-connected npn transistor QD. If the npn transistor QnB has the same structure as QD, a current proportional to the ratio of QnB to QD flows through its collector. For example, if the size is the same, IB flows. Due to this base current, the desired bias current IBI is applied to the complementary emitter follower of FIG.
AS flows. Note that reference numeral 102 denotes an example of a constant current circuit for flowing IBIAS, and any other constant current circuit may be used. This circuit allows the design value IBIAS to flow even if the characteristics of the pnp and npn transistors relatively vary between wafers or chips.

FIG. 30 shows still another embodiment of the present invention using a Darlington connection. A signal is directly input to the Darlington-connected pnp transistor, and a signal is applied to the Darlington-connected npn transistor via a capacitor. This embodiment is a circuit having the same characteristics as the embodiment of FIG. 24. In FIG. 24, the output voltage is lower than the input voltage by 2 VBE, whereas in this embodiment, the output voltage is lower than the input voltage. Is also increased by 2VBE. Therefore, the input signal of this circuit is
Generally, a signal having a value lower than 0 V by 2 VBE or more is applied. The power supplies VCC1, VCC2, VCC3, and VCL may be stabilized by an auxiliary power supply as shown in FIG. 23 or the voltage of the auxiliary power supply may be stabilized by an appropriate stabilizing circuit as necessary (for example, +
An appropriate voltage (such as 1 V or +2 V) is applied. For example, when the high level of the output is desired to be 0 V, VCC3
Is preferably about 1 VBE or more, Vcc2 is about 2 VBE or more, and VCC1 and VCL are preferably about 3 VBE or more. Further, it is desirable that the diodes D2 and D3 are formed by npn and pnp transistors, respectively. As in the embodiment of FIG. 24, in this embodiment, since the influence of the load capacitance hardly appears on the input side, a sufficiently high-speed circuit is configured even if the power consumption of the input signal generation circuit (eg, current switch) is reduced. it can. Further, the value of the coupling capacitor CC may be small, and the diode D1 is often unnecessary.

FIG. 31 shows still another embodiment of the present invention. Contrary to FIG. 25, of the complementary emitter followers,
Only npn transistors are Darlington connected.
As in the embodiment of FIG. 25, also in this embodiment, the base current of the Darlington transistor Q4 is small, so that CC can be small, and D1 is unnecessary in most cases.

FIG. 32 shows still another embodiment of the present invention in which the present invention is applied to a portion where a load is heavy. 210 and 211 indicated by solid squares indicate logic circuit blocks on the same chip or logic circuits on different chips. The logic circuit blocks such as 210 and 211 are
In general, they may be located far apart. In that case, to transmit a signal between the blocks, the output circuit 200
Therefore, a circuit having a large driving capability is required. If a logic circuit to which the complementary emitter follower (the coupling CC is relatively large) or the complementary Darlington emitter follower of the present invention is added to the circuit 200, a large driving capability can be obtained with low power consumption. .

Other circuits 201 in the logic block
202 may be a normal logic circuit, for example, a logic circuit using a normal emitter follower. (Alternatively, a logic circuit may be added to the complementary emitter follower of the present invention to which the coupling CC is relatively small.
It goes without saying that the complementary Darlington circuit of the present invention may be used as 201 and 202 if necessary. In the case where the complementary Darlington emitter follower of the present invention is used as 200, the output level is shifted by 1 VBE as compared with the case where the complementary emitter follower or the conventional emitter follower is used. Therefore, it is necessary to shift the threshold voltage of the input circuit 201 by that amount as compared with the other circuits 202. By using the combination as in this embodiment, high speed, low power consumption, and high packaging density can be satisfied together.

Although the present invention has been described with reference to an example in which the present invention is applied to a digital circuit, it will be apparent to those skilled in the art that the load driving capability can be similarly increased by applying the present invention to an analog circuit.

[0055]

As described above, the circuit configuration of the conventional complementary emitter follower has the configuration shown in FIGS. 7 to 9, so that both low power consumption and high speed operation are achieved. There was a problem that it could not be done.

According to the present invention, as shown in FIG. 1, the input signal is directly applied to the base of one of the emitter follower transistors constituting the complementary emitter follower, and the input signal is applied to the base of the other current source transistor. An input signal is applied via a capacitor. Further, a constant base current is drawn from the base of the current source transistor. For this reason, there is an effect that power consumption becomes almost zero in a steady state. Further, since the current source transistor is not overdriven, saturation of the transistor can be prevented. Therefore, there is an effect that high-speed operation can be realized. Further, when the output signal is at a high level, even if positive pulse noise is applied from the outside and the output further rises, there is a discharge path formed by the current source transistor. Therefore, the potential can be immediately restored to the original high-level potential. Therefore, there is an effect that a noise margin for external noise is large.

According to the present invention, a diode for clamping can be connected to the base of the current source transistor. In this case, when the input signal rises, the amount of fall of the base voltage of the current source transistor (the amount of rise of the emitter follower output signal) is clamped by the diode, and the cycle of the input signal can be reduced even with a large capacitive load. Not affected by time. Therefore, there is an effect that a stable high-speed driving operation can be realized.

According to the present invention, a bias circuit can be connected in parallel with the capacitor. By finely adjusting the bias condition by this bias circuit, there is an effect that an optimum bias current can be always maintained.

Further, according to the present invention, one of the transistors of the complementary emitter follower can be combined (Darlington connection). As a result, the size of the coupling capacitor can be reduced. In most cases, a diode for clamping is not required.

Further, according to the present invention, the other one of the complementary emitter follower transistors can be combined (Darlington connection). Thus, there is an effect that a large load can be driven at high speed with low power consumption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional emitter follower.

FIG. 3 is a circuit diagram of a conventional two-input ECL circuit.

FIG. 4 is a circuit diagram showing a conventional example of an active pull-down circuit using an npn transistor.

FIG. 5 is an operation waveform diagram of the circuit of FIG. 4;

FIG. 6 is a diagram illustrating a problem of the circuit in FIG. 4;

FIG. 7 is a circuit diagram showing a conventional example of an active pull-down circuit using a pnp transistor.

FIG. 8 is a circuit diagram showing another conventional example of an active pull-down circuit using a pnp transistor.

FIG. 9 is a circuit diagram showing still another conventional example of an active pull-down circuit using a pnp transistor.

FIG. 10 is a circuit diagram showing one embodiment of a bias current circuit used in the embodiment of FIG. 1;

11 is an example of another constant current circuit used for the bias current circuit of FIG.

FIG. 12 is a circuit diagram of an embodiment in which the present invention is applied to an ECL circuit.

FIG. 13 is a circuit diagram of another embodiment of the present invention.

FIG. 14 is a circuit diagram of an embodiment in which the circuit of FIG. 13 is applied to an ECL circuit.

FIG. 15 is a circuit diagram of an embodiment in which the present invention is applied to an NTL circuit.

FIG. 16 is a circuit diagram of still another embodiment of the present invention.

FIG. 17 is a circuit diagram of an embodiment in which the present invention is applied to a gate circuit composed of bipolar and MOS.

FIG. 18 is a circuit diagram of another embodiment in which the present invention is applied to a gate circuit composed of bipolar and MOS.

FIG. 19 is a circuit diagram of an embodiment in which the present invention is applied to a CMOS gate circuit.

FIG. 20 is a sectional view of an embodiment of a pnp transistor used in the present invention.

FIG. 21 is a circuit diagram of another embodiment of the present invention.

FIG. 22 is a circuit diagram of one embodiment of a bias current source used in the embodiment of FIG. 21;

FIG. 23 is a configuration diagram of an example of an auxiliary power supply used in the embodiments of FIGS. 21 and 22;

FIG. 24 is a circuit diagram of another embodiment of the present invention.

FIG. 25 is a circuit diagram of still another embodiment of the present invention.

FIG. 26 shows a capacitor connected in parallel with a diode.
FIG. 10 is a circuit diagram of still another embodiment of the present invention.

FIG. 27 is a circuit diagram of still another embodiment of the present invention.

FIG. 28 is a circuit diagram of another embodiment in which the present invention is applied to an NTL gate.

FIG. 29 is a circuit diagram of another embodiment in which the present invention is applied to a CMOS gate.

FIG. 30 is a circuit diagram of still another embodiment of the present invention.

FIG. 31 is a circuit diagram of still another embodiment of the present invention.

FIG. 32 is a circuit diagram of still another embodiment of the present invention in which the present invention is applied only to a heavy load portion.

[Explanation of symbols]

101 Current source of bias current IB 102 Constant current source Cc, CC1, CC2 Coupling capacitor Qn npn transistor Qp pnp transistor DCL, DCL1, DCL2, D1 Clamping diode Q1, Q2 Current switch transistor IB Base current for bias IB, R2 Collector load resistance of current switch (ECL)

Continued on the front page (72) Kunihiko Yamaguchi 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Kazuo Kanaya 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Yoji Dei 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Yoshiaki 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (56) References JP-A-1-259623 (JP, A) JP-A-3-226009 (JP, A) JP-A-3-208413 (JP) , A) JP-A-3-171921 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 19/086 H03K 17/00-17/70

Claims (5)

(57) [Claims] 1. A complementary emitter follower in which two bipolar transistors having different polarities have their emitters connected to each other and their collectors connected to corresponding power supplies, respectively. An input signal is directly applied to the base of one of the transistors. A complementary emitter follower, wherein an input signal is input to the base of the other transistor via a capacitor, and a current source for bias current is connected to the base of the other transistor. 2. The complementary emitter follower according to claim 1, wherein a clamp diode is further connected to said base of said other transistor. 3. A complementary emitter follower according to claim 1, wherein a bias circuit for correcting a bias condition is connected in parallel with said capacitor. 4. The other transistor has a configuration in which two transistors are combined (Darlington connection).
4. The method according to claim 1, wherein the first and second parts are formed.
5. The complementary emitter follower according to item 1. 5. The device according to claim 4, wherein both the one transistor and the other transistor are formed by combining two transistors (Darlington connection). Complementary emitter follower.