JP3260395B2 - Multi-input fuzzy logic operation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuzzy information processing apparatus which performs a MAX operation or MI
The present invention relates to a multi-input fuzzy logic operation circuit for performing N operation.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, the IEEE Journal of Solid-State Circuit
State Circuits) 25 [2] (1990-4) (US) H. Wa
tanabe, W. Dettloff, K. Yount, "AVS
A VLSI Fuzzy Logic Controller with Reconfigurabl
e, Cascadable Architecture) " 376-382.

Conventionally, as described in the above-mentioned literatures and the like, in a fuzzy information processing apparatus, when integrating the operation results of each rule of fuzzy synthesis or rule type inference, a large number of arguments MAX / MIN operations, which are fuzzy logic operations, are often used. FIG. 2 shows an example of the circuit configuration.

FIG. 2 is a block diagram showing an example of a configuration of a conventional multi-input fuzzy logic MAX arithmetic circuit described in the above-mentioned literature and the like.

This multi-input fuzzy logic MAX operation circuit comprises a plurality of stages of 2-input MAX operation units 1-1 to 1-8, 2-
1-2-4, 3-1, 3-2, and 4 are connected to a binary tree structure. Then, a plurality of input data consisting of binary numbers (binary numbers) is converted into a plurality of MAX arithmetic units 1- 1 of the input stage.
In steps 1 to 1-8, a MAX operation is performed to compare each bit and select the larger one. Each MAX computing unit 1 of this input stage
The outputs of -1 to 1-8 are output to a plurality of MAX arithmetic units 2- in the next stage.
1 to 2-4, each of which performs a MAX operation, and further outputs the operation result to a plurality of MAX operation units 3-1 and 3-
After the MAX operation in step 2, the MAX operation unit 4 in the final stage
The MAX operation is performed and the operation result is output.

FIG. 3 is a block diagram showing the configuration of the 2-input MAX computing unit in FIG.

In this two-input MAX calculator, two inputs are compared by a comparator 5, and a selector 6 performs a selecting operation based on the comparison result, and outputs the larger of the two inputs. The selector 6 includes an AND gate and a NO
It is composed of an R gate and the like.

[0008]

However, in the arithmetic circuit having the above configuration, when the number of input data to be compared, that is, the number of arguments increases, the amount of hardware (circuit scale) increases, and the operation speed further decreases. There is a problem.
Therefore, if the fuzzy information processing device provided with the multi-input fuzzy logic operation circuit is integrated or the like, there is a problem that the chip size increases, and it has been difficult to solve it.

The present invention provides a multi-input fuzzy logic operation circuit which solves the problem of the prior art, in that when the number of arguments increases, the amount of hardware increases and the operation speed decreases. Is what you do.

[0010]

To solve the previous SL problems SUMMARY OF THE INVENTION The first aspect of the present invention, when the fuzzy inference execution
Of the plurality of input data A _j (where j = 1, 2,...,
m) MAX operation is performed bit-serial, and the plurality of
A multi-input file for obtaining the maximum value data D in the input data A _j
In the fuzzy logic operation circuit, sent from the upper side
i-th (where i = 0, 1,..., n) plural transmission signals
_Signal Q _ji and the i-th bit a in each of the input data A _j
a first group of control gates for _obtaining a logical product with _ji ;
Obtaining OR of output data of the first control gate group
Multiple-input for outputting the i th bit d _i in the data D
A gate, wherein each bit and the inverted data of the bit d _i
a two-input gate group for calculating the logical sum with a _ji
2. Each output data of the input gate group and each transmission signal Q _ji
And (i-1) th transmission
Second control gate group for outputting signal Q _{j (i-1)} to the lower side
And

[0011] A second aspect of the present invention provides a method for executing a plurality of fuzzy inferences.
M of input data A _j (where j = 1, 2,..., M)
Performs an IN operation in a bit-serial manner and outputs
Multi-input fuzzy theory for finding the minimum data D in A _j
In the arithmetic operation circuit, the i-th
(Where, i = 0,1, ......, n ) a plurality of transmission signals Q _ji of
When the the i-th bit a _ji in each input data A _j
A first group of control gates for respectively calculating a logical sum,
The logical product of the output data of one control gate group is obtained and
Multi-input gate for outputting the i th bit d _i in over data D
When, the inverted data of the bit d _i wherein each bit a _ji
A two-input gate group for calculating the logical product of
Theory of each output data of the force gate group and each transmission signal _Qji
The respective sums are obtained, and the (i-1) th transmission signal Q
_{j (i-1)} to the lower side.
I have.

[0012]

According to the present invention, since the configuration of the multi-input fuzzy logic circuit as described above, a plurality of input data A _j
Is input, i-th bit in the respective input data A _j
And bets a _ji, i th plurality of transmission sent from the host side
The signal Q _ji is _ANDed (or _argued) by the first group of control gates.
Riwa) is taken. Output of this logical product (or logical sum)
Data is ORed (or ANDed) with multiple input gates
It is, i th bit d _i in the output data D is obtained
You. And inverted data bit d _i, in each input data A _j
Bit _aji is a logical OR (or logical
Product). The each output data and the transmission signal Q _ji
But the logical AND (or logical sum) of the second control gate group is
And the (i-1) th transmitted signal _{Qj (i-1)} is calculated and
Output to the digit. Such first and second control gates
Group, multi-input gate, and 2-input gate group to output data D
If cascade connection is provided with the number of bits of
In the most significant bit (MSB) of data D, the first and
2 are omitted because the control gate group is unnecessary, and the output data D
At the least significant bit (LSB) of
Beauty omitted for the second control gate group is not required), MAX operation result to a plurality of input data A _j, or MIN operation result is obtained.

In the present invention , multi-input is performed at the level of a basic logic element such as an AND gate or an OR gate, and the multi-input OR
MAX operation and M using a multi-input AND gate
Since IN operation can be performed, even if the number of input data is large,
The amount of hardware can be reduced and the calculation speed can be increased. Therefore, the above problem can be solved.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the configuration of a multi-input fuzzy logic operation circuit according to an embodiment of the present invention, the fuzzy inference algorithm used in this embodiment and the MAX / MIN operation used in this embodiment are converted into bit serial data. The calculation algorithm will be described.

When considering parallel execution of rule type fuzzy inference in order to increase the processing speed, since the processing is independent for each rule, the processing of one rule should be selected as a unit for parallel execution. Is natural. However,
When the number of rules increases, the following problem occurs. In other words, in order to process each rule completely independently, one processing unit must be assigned to each rule, and an increase in the number of rules causes an increase in circuit scale. Further, in the process of integrating the inference results, since the MAX operation is performed on the arguments of the number of rules, when the number of rules increases, the processing speed of integrating the inference results of each rule decreases. For this reason, it is advantageous to increase the processing unit of the parallel processing as the number of rules increases. on the other hand,
In most cases, the number of types of membership functions is ten or less from the application examples.

Therefore, in the present embodiment, a group of rules having the same consequent label (type of membership function) is collected to create one new rule. By using this new rule as a unit of parallel processing, the number of processing units can be reduced to the number of labels in the consequent part, and the number of arguments of the operation for integrating the inference results can also be the number of labels.

Number of inputs 2, number of outputs 1, number of labels of consequent part 2
Considering the case of the following example, four rules 1 to 1 of the following equation (1)
4 is summarized in two rules 11 and 12 of the following equation (2).

Rule 1: if x1 is A11, x2 is A12 then is B1 Rule 2: if x1 is A21, x2 is A22 then is B2 Rule 3: if x1 is A31, x2 is A32 then B2 rule : If x1 is A41, x2 is A42 thenis B1 ... (1) where if x1 is A11, etc .; antecedent proposition protest, isy B1, etc .; consequent proposition x1, x2; input variable y, result (output) A11 to A41, A12 to A42; parameters B1, B2 representing the antecedent part membership function (label); parameters representing the consequent part membership function (label) "," in the antecedent part; AND join rule 11: if (x1 is A11, x2 is A12) or (x1 is A41, x2 is A42) theny is B1 Rule 12: if (x1 is A21, x2 is A22) or (x1 is A31, x2 is A32) theny is B2 ... (2) In the expression (2), the antecedent part Is an additive standard form. Also, in the inference process, if the or combination corresponds to the rule integration operation, the same result as the inference result before the rules are put together is obtained. When the MAX / MIN inference method is adopted, the fitness w1 of the input x1 = x1 ', x2 = x2' with respect to the antecedent is obtained by the following equation (3). w1 = [A11 (x1 ') ∧A12 (x2')] ∨ [A41 (x1 ') ∧A42 (x2')] (3) where ∧; MIN operation ∨; MAX operation The inference result Bi ′ for the label Bi is obtained as Bi ′ (y) = wi · Bi (y) i = 1, 2,... (4). The inference result B 'of the entire rule is obtained by the following equation (5) from the inference result of each rule.

B ′ (y) = ΣBi ′ (y) = Σwi · Bi (y) (5) If a definite value y ′ is required, for example, the following equation is obtained from the membership function B ′ using the center of gravity method. It can be calculated in (6).

[0020]

(Equation 1)

Next, a description will be given of an algorithm for calculating the MAX / MIN operation bit-serially used in processing the above fuzzy inference.

For example, D = MAX (A,
B, C) will be described. Where A,
B, C, and D are n-bit binary numbers (binary numbers);
a _i , b _i , c _i , d _i = 0, 1 (i = 0, 1,...,
n) represents the i-th bit of A, B, C, and D, respectively. d _i can be calculated by the following recurrence formulas (7) to (9). _{d i = (Qa i · a} i) + (Qb i · b i) + (Qc i · c i) ... (7) Qa i-1 = Qa i · (c i / + a i) ... (8) Qb _{i-1 = Qb i · (} c i / + b i) ... (9) Qc i-1 = Qc i · (d i / + c i) ... (10) However, "-", "+" is binary logic Operation, OR operation, c _i / is the inverted bit of c _i , Qa _i , Qb _i , Qc
_i is a state variable that holds the comparison result from the MSB to the i-th bit. Let recurrence equations (7) to (10) be i = n-1
By repeating the process from 0 to 0 with the initial value Qan _-1 1 = Qbn _-1 = Qcn _-1 , D = MAX (A, B, C) is obtained.

In the case of the MIN operation, D = MIN (A, B,
The recurrence formula of C) is a dual formula with the formulas (7) to (10).

[0024] _{d i = (Qa i + a} i) · (Qb i + b i) · (Qc i + c i) ... (11) Qa i-1 = Qa i + (c i / · a i) ... (12) _{Qb i-1 = Qb i +} (c i / · b i) ... (13) Qc i-1 = Qc i + (d i / · c i) ... (14) However, the initial value Qa _n-1 = Qb _n-1 = Qc _n-1 = 0 The recurrence formula of the MAX / MIN operation can be easily multi-input. An example will be described in which D = MAX (A ₁ , A ₂ ,..., _Am ). Where A _j (j = 1, 2,..., M), D is an n-bit binary number, a _ji , d _i = 0, 1 (i = 0,
1,..., N) represent the i-th bit of A _j and D , respectively. The recurrence formula for obtaining d _i is as follows.

D _i = (Qa _1i · a _1i ) + (Qa _2i · a _2i ) + ... + (Qa _mi · a _mi ) = d _1i + d _2i + ... + d _mi (15) d _ji = Qa _ji · _{a ji ... (16) Qa j} (i-1) = Qa ji · (d i / + a ji) ... (17) However, di /; using d _i MAX / MIN calculation algorithms described above the inverted bit Thus, in order to configure a multi-input fuzzy logic MAX operation circuit, a circuit configuration that executes equations (15) and (16) may be used. FIG. 1 shows an example of the configuration.

FIG. 1 is a circuit diagram of a multi-input fuzzy logic MAX operation circuit showing one embodiment of the present invention.

In FIG. 1, MAX of three inputs A, B, C
An example in which the calculation D = MAX (A, B, C) is performed is shown. Here, A _{2 to} A ₀ are each bit of the first input A (A ₂ is the MSB), B _{2 to} B ₀ are each bit of the second input B, and C _{2 to} C ₀ are the third. Of the input C, D _{2 to} D ₀ respectively represent the bits of the output D.

In the three-input fuzzy logic MAX operation circuit, a three-input OR which is a multi-input gate is provided for each bit position.
Gates 10, 20, and 30 are provided, respectively. Inverters 11 and 21 for inverting the output bits D ₂ and D ₁ are provided on the output side of each of the OR gates 10 and 20, respectively. On the output side of the inverters 11 and 21, a plurality of 2-input OR gates 12 as a 2-input gate group are provided.
-1 to 12-3 and 22-1 to 22-3 are respectively connected.

A ₂ , B which is the MSB of each input A, B, C
_2, C ₂ is 3 to the input side of the input OR gate 10 and two-input OR gate 12-1 to 12-3 are connected respectively.

The lower bits A ₁ , B ₁ , C _{1 of} each of the inputs A, B, C and transmission signals QA ₂ , Q from the MSB
B ₂ and QC ₂ are connected to a 3-input OR gate via 2-input AND gates 23-1 to 23-3 as a first control gate group.
It is connected to the input side of the gate 20. The output bit D ₁ of the three-input OR gate 20 is inverted by the inverter 21, and its inverted output and the lower bit A of each of the inputs A, B, and C are output.
₁ , B ₁ , and C ₁ are two-input OR gates 22-1 to 22-2, respectively.
2-3 are connected to the input side. Each transmission signal QA ₂ ~QC ₂ from MSB, the OR gate 22-
The outputs of 1 to 22-3 are connected to the input side of each of the two-input AND gates 24-1 to 24-3 as the second control gate group .

Each of the two-input AND gates 24-1 to 24-3
The transmission signals QA ₁ , QB ₁ , and QC ₁ output from the _first and the LSBs A ₀ , B ₀ , and C _{0 of the} inputs A, B, and C are the _first signals .
Each 2-input AND gates 33-1～ a control gate group
33-3 is connected to the input side. The output side of the 2-input AND gates 33-1 to 33-3 are three-input is connected to the OR gate 30, from the three-input OR gate 30 has a configuration in which the LSBD ₀ output D is output.

Next, the operation will be described.

First, MSBA ₂ , B of each input A, B, C
_2, the logical sum of C ₂ is determined by an OR gate 10, the output bit is D _2. Output bit D ₂ is inverter 1
1, the inverted signal and the input bits A ₂ , B ₂ ,
Logical sum of the C ₂ is determined at each OR gate 12-1 through 12-3. The transmission signals QA ₂ , QB ₂ , and QC ₂ output from each of the OR gates 12-1 to 12-3 are MSBA ₂ ,
In comparison with B ₂ and C ₂ , the signal corresponding to the larger one becomes logic “H”, and the others correspond to logic “L”.

For example, A ₂ = “H”, B ₂ = “H”, C
_{When 2} = “L”, QA ₂ = “H”, QB ₂ = “H”,
QC ₂ = “L”. MSBA ₂ , B ₂ , C ₂
Are all "L", it is considered to be all large,
The transmission signals QA ₂ , QB ₂ , and QC ₂ all become “H”. Transmission signals QA _i , QB _i , QC _i (i = 2,1)
Is a signal for transmitting the comparison result from the upper bit to the bit i to one lower bit.

Next, the logical product of the transmission signal QA ₂ from the MSB and the input bit A ₁ , the logical product of QB ₂ and B ₁ , QC ₂
A logical product of C ₁ is, each respective AND gates 23-1～
Obtained in 23-3, the logical sum of the output is determined by the OR gate 20, whose output bits are D _1. The output bit D ₁ is inverted by the inverter 21, and the OR of the inverted signal and the input bits A ₁ , B ₁ , C ₁ is obtained by the OR gates 22-1 to 22-3. OR gate 22-1
Output transmission signal QA ₂ of ~22-3, QB _2, logical product of the QC ₂ are each respective AND gates 24-1～24-
3 and their outputs are transmitted signals QA ₁ , QB
_1, the QC _1.

Finally, in the LSB, the logical product of the transmission signal QA ₁ and the input bit A ₀ , the logical product of QB ₁ and B ₀ ,
The logical product of C ₁ and C ₀ is added to each AND gate 33
Obtained in -1～33-3, by obtaining the logical sum of the output OR gate 30, the output of OR gate 30 is the output bit D _0.

As described above, the three-input fuzzy logic MAX operation circuit shown in FIG. 1 does not employ a conventional binary tree structure but directly employs OR gates, AND gates, and basic logic elements of inverters. Since the arithmetic circuit is configured, even if the number of input data is large, the amount of hardware can be reduced, and MAX operation can be performed at high speed. Therefore, if such a multi-input fuzzy logic MAX operation circuit is provided in a fuzzy information processing device and the device is integrated, the chip size can be reduced.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications.

(I) In FIG. 1, a 3-bit comparison operation is performed. However, when a 3-bit or more comparison operation is performed, MSB and L
Except for SB, the output bit D ₁ and the transmission signals QA ₁ , Q
It is sufficient to provide a logic circuit for obtaining B ₁ and QC ₁ in an increasing number of bits. (Ii) Although the three-input fuzzy logic MAX operation circuit has been described in FIG. 1, the number of inputs can be increased by the same configuration method as in FIG. In this case, a multi-input OR gate (10, 20) is required, but can be easily realized by using, for example, a dynamic logic circuit.

(Iii) In the above embodiment, an example of the multi-input fuzzy logic MAX operation circuit is shown.
Based on the equation (14), a multi-input fuzzy logic MIN operation circuit can be constituted by the dual circuit shown in FIG. In this case, for example, the three-input OR gates 10 , 20, and 30 in FIG. 1 are replaced with three-input AND gates and two-input OR gates 12-1 to 12-12.
-3 , 22-1 to 22-3 are 2-input AND gate , 2-input
Force AND gates 23-1 to 23-3, 24-1 to 24-
3, 33-1 to 33-3 may be replaced with a 2-input OR gate .

(Iv) In the circuit shown in FIG.
The gates 10, 20, 30 may be changed to other multi-input gates, or two-input OR gates 12-1 to 12-3, 22-1 to 22
22-3 can be changed to another two-input gate, or two-input AND gates 23-1 to 23-3, 24-1 to 24-
3, 33-1 to 33-3 may be changed to other control gates. In addition, various modifications are possible, such as adding another gate to the circuit of FIG.

[0042]

As described in detail above, the first and second embodiments are described .
According to the second invention, for example, a multi-input fuzzy logic operation circuit using a multi-input gate, a two-input gate group , and first and second control gate groups using basic logic elements such as an AND gate, an OR gate, and an inverter Therefore, even if the number of arguments is large in fuzzy synthesis or rule integration operation in rule-type fuzzy inference, the amount of hardware can be reduced as compared with the conventional arithmetic circuit having a binary tree structure. MAX operation or MIN operation can be performed at high speed. Therefore, if the arithmetic circuits of the first and second inventions are mounted on a fuzzy information processing apparatus,
This makes it possible to reduce the size of the device and increase the calculation speed.

The arithmetic circuit according to the first and second aspects of the present invention is not limited to a fuzzy information processing apparatus. For example, if the arithmetic circuit is applied to an arithmetic unit of a priority encoder required for image processing of a multi-window system, which window should be displayed. Decisions can be made quickly. In addition, it can be applied to various application fields.

[Brief description of the drawings]

FIG. 1 shows a multi-input fuzzy logic MA showing an embodiment of the present invention.
FIG. 3 is a circuit diagram of an X operation circuit.

FIG. 2 is a configuration block diagram of a conventional multi-input fuzzy logic MAX operation circuit.

FIG. 3 is a configuration block diagram of a two-input MAX computing unit in FIG. 2;

[Explanation of symbols]

10, 20, 30 3-input OR
Gate 11, 21 Inverter 12-1 to 12-3, 22-1 to 22-3 2-input OR
Gates 23-1 to 23-3, 24-1 to 24-3, 33-1 to 3
33-3 2-Input AND Gate

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takeshi Katshiro 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Koichi Nakagawa 1-7-12 Toranomon, Minato-ku, Tokyo No. Oki Electric Industries Co., Ltd. (58) Field surveyed (Int. Cl. ⁷ , DB name) G06N 7/02 G06F 7/00

Claims (2)

(57) [Claims] 1. A plurality of input data when executing fuzzy inference
A _j (where, j = 1,2, ......, m ) a MAX operation bicycloalkyl
Go to Ttoshiriaru, the most in the input data A _j of the plurality of
Multi-input fuzzy logic operation circuit for finding large value data D
The i-th (i = 0, 1,...) Sent from the upper side
..., a plurality of transmission signals Q _ji of n), each input data A
_Find the logical product of the ith bit a _{ji in j}
Seeking a first control gate group, the logical sum of the output data of said first control gate group
Multiple-input for outputting the i th bit d _i in the data D
Logical of the gate, and the inverted data and the respective bit a _ji of the bit d _i
A two-input gate group for calculating a sum, each output data of the two-input gate group, and each transmission signal Q
The logical product with _ji is calculated, and the (i-1) th
Second control gate group for outputting the arrival signal _{Qj (i-1)} to the lower side
And a multi-input fuzzy logic operation circuit characterized by comprising:
Road. 2. A plurality of input data during execution of fuzzy inference
The MIN operation of A _j (where j = 1, 2,.
Go to Ttoshiriaru, the most in the input data A _j of the plurality of
Multi-input fuzzy logic operation circuit for finding small value data D
The i-th (i = 0, 1,...) Sent from the upper side
..., a plurality of transmission signals Q _ji of n), each input data A
_Calculate the logical sum with the ith bit a _{ji in j}
Seeking a first control gate group, the logical product of the output data of said first control gate group
Multiple-input for outputting the i th bit d _i in the data D
Logical of the gate, and the inverted data and the respective bit a _ji of the bit d _i
A two-input gate group for calculating the logical product, each output data of the two-input gate group, and each of the transmission signals Q
The logical sum with _ji is calculated, and the (i-1) th
Second control gate group for outputting the arrival signal _{Qj (i-1)} to the lower side
And a multi-input fuzzy logic operation circuit characterized by comprising:
Road.