JP3258095B2 - Method of manufacturing and forming integrated circuits with complementary n-channel and p-channel devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VLSI semiconductor CMOS.
It relates to the process and more particularly to the implantation of dopants in the p-wells and n-wells that make up the n-channel and p-channel memory arrays and associated peripheral circuits. The invention is particularly dynamic
Random access memory device (DRAM
Applicable to S).

[0002]

2. Description of the Related Art Electronic circuits are formed by patterning regions in a substrate and patterning layers on the substrate.
It is chemically and physically integrated within a substrate such as a wafer. These regions and layers can be made conductive to create conductors and resistors. These regions can also be of different types of conductivity, which is essential for the fabrication of transistors and diodes. The degree of resistance, capacitance, or conductivity is controllable because the physical dimensions and location of the patterned regions and layers allow for circuit integration.

In this embodiment, "n" is conductively treated with an atom having four or more valence electrons (group V or higher), such as arsenic or phosphorus, which introduces most of the negatively charged carriers into silicon. "P" represents the most positively charged carrier, such as boron, which introduces most carriers.
Represents silicon doped with atoms having the following valence electrons (below Group III): Most charged carrier types are also referred to as conductive types. + or-of n or p
The subscripts indicate the doping weight.

[0004] Where electrical functions and connections are described, it is understood that expensive circuitry may be used within the scope of the present invention for the purpose of performing the functions described. You. As an example, a transistor can be used as a diode or a resistor. Similarly, two electrical components that are connected can have an intermediary component that physically separates the two components. Thus, the term "connected" is intended to include a component that is in electrical communication regardless of its intervening components.

A dynamic random access memory utilizing both n-channel and p-channel transistors and their associated bit or digit lines.
Access memory (DRAM) cells are generally well known in the art and have been made using state of the art photolithographic masking and etching techniques as well as ion implantation doping methods. In many of these DRAM cells, integrated circuit storage capacitors are optically formed, formed on top of the DRAM cell bit lines and receive and store charge during operation of the memory circuit and bit line transistors through word line transistors. It operates so that it may be transmitted to and received from. Such a multilayer capacitor type DRAM integrated circuit is described in IED, which is incorporated herein by reference.
Kimura et al. In a 1988 International Electron Devices Conference (IEDM) paper entitled "New Multilayer Capacitor DRAM Cell Featuring Storage Capacitors on Bit Line Structure", pp. 596-599 of the M. Bulletin. Has been disclosed.

[0006]

These multilayer capacitors D of the type disclosed in the aforementioned publication by Kimura et al.
The conventional method of making a RAM cell is to first optically form, then the n-channel and p-channel transistor gates are formed on the surface of the semiconductor substrate in a simple optical step, then the NMOS and Perform photomasked ion implantation doping for the PMOS transistor gate. Using this method, the formation of ion implantation steps for n-channel and p-channel transistors in both the memory data storage area and the peripheral interconnect circuit area of the semiconductor substrate is processed in parallel. In the case of this conventional process of forming both NMOS and PMOS transistors in a single mask step, the PMOS device is photomasked when the required NMOS implantation is completed and also for the required PMOS implantation. Is required. This means, for example, that during the formation of the n-channel transistor and the p-channel transistor, the p-channel transistor and the n-channel transistor must be alternately masked for ion implantation doping of the other transistor conductivity type. It was meant to be. Each type of transistor (NM
OS and PMOS) require at least two steps of ion implantation doping, which in turn requires only individual masking schemes to form the aforementioned n-channel and p-channel DRAM memory arrays and their peripheral driver circuits. Was meant to be.

The need for this multiple masking step, in order to provide the required selective ion implantation described above into the semiconductor substrate, increases wafer processing costs and lowers process yield, It also reduces the reliability of the device. In addition, as described above, p
The above prior art method, in which the -channel transistor and the n-channel transistor are processed in parallel, exposes the peripheral PMOS circuit to all of the temperature cycling used in the construction of the memory array data storage circuit. This fact has a negative effect on the reliability and performance of p-channel devices in peripheral array circuits.
There is a possibility to bring, also, of the PMOS device scale
Minimize Scaleability . Additional temperature cycling (used for NMOS S / D)
The high diffusivity of boron (used for PMOS S / D) as compared to arsenic is even more critical for PMOS devices. These peripheral devices include, for example, logic arrays, sense amplifiers, decoders, driver circuits, and the like, typically created on the peripheral area of the semiconductor substrate immediately adjacent to the internal memory array area. As an example, the above-described temperature cycling exposure of the peripheral array circuit during the parallel processing described above can be achieved by first forming a PMOS transistor in the peripheral array circuit during the entire process.
This means that the P + S / D junction is then exposed to the entire process of temperature cycling. This Oiyari in deeper semiconductor substrate PMOSP + S / D junctions of the peripheral array circuit conversely, it is a PMOS transistor scan
There is a tendency to reduce kale capacity . Thus, this processing characteristic tends to reduce the high frequency performance of these circuit types where otherwise short channel PMOS transistors are preferred.

[0008] The split-type multi-DRAM process dramatically reduces the number of processing steps including a masking step which directly affects the cost, reliability and manufacturability of a product. The latest generation of DRAM products requires downsizing to further reduce geometry. This has a significant effect on the cost of performing the photolithographic process. There are many causes for this cost increase.
Investment costs associated with "as is" photolithographic equipment are high. Finer geometries increase the number of optical processing steps per level, and also increase the required equipment, increasing costs and requiring the use of expensive and extremely clean room floor space. The defect density inevitably increases with each additional photomasking layer, which compensates for line yield, probe yield and reliability. All optical layers require subsequent steps such as implantation or etching. These steps are additional steps that lead to high costs.

[0009] Inverse multi-steps were initially developed for NMOS steps with the aim of reducing the number of mask steps and providing improved alignment of circuit components formed in the multiple masking steps of the DRAM step. An embodiment of this processing method using two polysilicon layers is described in U.S. Pat. No. 4,871,688.

Although the present invention is described with reference to a DRAM, this is only the preferred embodiment in which the inventive technique was developed. DRAM processing techniques also include video random access memory (VRAM) and other multi-port RAMs.
It is applicable to other semiconductor circuit devices that use DRAM design techniques, such as related semiconductor circuit devices including S, as well as optical detection arrays. In particular, DRAM processing techniques are generally applicable to other types of semiconductor devices. In this regard, DRAM technology is considered a "pioneer technology" over other integrated circuit technologies, and it is therefore expected that the inventive technology will be applicable to other types of integrated circuits.

[0011]

SUMMARY OF THE INVENTION The general and main objects of the present invention are to reduce the manufacturing cost and increase the performance of a device simultaneously while increasing the process yield. To provide a new alternative method for the parallel processing method.

Another object of the present invention, p- channel device in key memory array circuit around,
Transistor <br/> over the bit line process及beauty related certain temperature cycling all be implemented in a continuous manner as not exposed to a n- channel and p- channel used in the production of the main memory array It is an object of the present invention to provide a new and improved method of forming a complementary integrated circuit structure. As a result, to improve the reliability and performance of the whole device of an integrated circuit that the characteristic portion is produced by it this.

To achieve this and other related objects, a multi-level layer of conductive material and a multi-level layer of insulating transistor gate material are formed and the main memory array portion and the peripheral array of the semiconductor substrate are formed. New and improved complementary n extending across both parts
-Channel and p-channel metal oxide semiconductors (M
It has been found that an OS) method has been developed. Then, n
The channel transistor gate is optically formed and fabricated, including the gate in the main memory array portion of the semiconductor substrate, while leaving the gate electrode layer on the p-channel transistor in place.

In a preferred embodiment of the present invention, bit lines or digit lines in the memory array portion of the device are formed adjacent to access internal transistors to provide charge storage for the integrated circuit memory. The laminated capacitor structure is provided. Furthermore,
A p-channel transistor gate electrode and an n-channel transistor in both the memory and peripheral portions of the device
Isolation oxide spacers are provided on both sidewalls of the transistor gate electrode and adjacent to the digit / bit line structure in the memory array portion. These isolation spacers serve to provide the required electrical isolation between the various components of the integrated circuit device being created, and to optimize the overall incremental and high frequency performance of these devices. Useful.

The foregoing objects, advantages and other novel features of the present invention will become more readily apparent from the following description of the accompanying drawings.

[0016]

Referring now to FIG. 1, there is shown a semiconductor substrate 10 of starting material, in which the semiconductor substrate is p-type silicon and is subjected to a conventional ion implantation or diffusion doping method. The n-type well 12 is formed by using this.

The semiconductor substrate 1 as a p-type silicon substrate
The top surface of O is treated in a conventional manner using known oxide deposition and masking and etching methods to form a thin surface gate dielectric 14. Preferably, the surface gate dielectric 14 is oxidized SiO ₂ merging into extending to and illustrated several thick field oxide portions 16, 18 and 20 as a whole upper surface across the lateral direction of the semiconductor substrate 10 It is a physical layer. This thick field oxide portion 16,
18 and 20 are used in a known manner to provide electrical isolation of transistors and other electrical devices created on each side of these thick field oxide portions 16, 18 and 20 in the manner described below.

The integrated circuit structure of FIG. 1 has three consecutive matched layers 22, 24 and 2 completely across the surface of the structure.
6 is deposited first and deposited sequentially using semiconductor and insulating layer formation methods, each of which is well known in the art and described in further detail below. The first layer 22 is polycrystalline silicon, also referred to herein as poly 1 and the second layer 24 is tungsten silicide, also referred to herein as WSix-1. Third
Is a layer of silicon dioxide, SiO ₂ , also referred to herein as oxide 1.

Three layers of polysilicon 22, 24 and 26
After that, tungsten silicide and silicon dioxide are deposited across the entire surface of the semiconductor substrate 10, which is the p-type silicon substrate including the n-type well 12, as previously shown, and the three corresponding layers described above. Conventional state-of-the-art photolithographic masking and etching methods are used to form the plurality of openings 28, 30, 32 and 34 completely through 22, 24 and 26. As shown, after these openings 28, 30, 32 and 34 have been formed, the integrated circuit structure shown in FIG. 1 is transferred to a conventional ion implantation station where n-type ions such as phosphorus are implanted, A plurality of corresponding n-type surface channel regions 36, 38, 40, 42 and 44 for the transistors and other devices of the integrated circuit thus formed are formed.

The area 46 shown in FIG.
The area 48 shown in FIG. 1 has been created to accommodate future storage node contacts to the integrated circuit storage capacitor, while the line or digit line contacts have been created to accommodate the line or digit line contacts. Continuing from left to right, as shown in FIG. 1, the region 50 shown in FIG. 1 has been created for the purpose of accommodating future spacer insulation regions, and FIG.
The areas 52 and 54 of the integrated circuit structure shown in FIG. 3 are processed to accommodate future hedge isolation barriers and future p-channel transistors from left to right.

Various n-type surface channel regions 36, 3
The above-described phosphorus ion implantation process used for forming the gates 8, 40, 42 and 44 is for setting the gate voltage of the transistor formed on the surface of the semiconductor substrate 10 as the silicon substrate or for inputting the voltage V. Is referred to as a lightly doped drain (LDD) implant used in US Pat. After completion of this implantation step, the structure shown in FIG. 1 is first transferred to a spacer oxide deposition, anisotropic etching station where the polysilicon layer 22, tungsten silicide layer 24 and silicon dioxide layer 2
A plurality of spacer oxide regions of silicon dioxide are formed around all four edges of the previously created island or pattern in 6.

Referring now to FIG. 2, these silicon dioxide spacers are shown in FIG.
6, 58, 60, 62, 64, 66, 68, 70 and 7
These regions are represented by four complex islands of polysilicon, tungsten silicide and silicon dioxide.
4, 76, 78 and 80 are etched with matching geometries shown on the sides. These spacers are also simultaneously formed on the side of the future hedging portion 52 surrounding the area of the p-type transistor 54 shown above the field oxide region portion 18 and on the right side of FIG. As is well known in the art, sidewall regions 56, 58, 60, 62, 64, 66, 6 which are spacer oxide regions.
8, 70 and 72 serve to electrically isolate the various devices formed on the silicon chip, and these sidewall regions initially extend over all exposed top surfaces of the overall structure shown in FIG. A continuous oxide layer (not shown), and then composite islands 74, 76, 78 and 8
Anisotropic etchant to remove the spacer oxide previously covering the top of the layer of
It is formed by applying to the iO2 layer. This step is performed using an anisotropic dry etch, thus leaving the oxide spacer sidewall regions 56, 58, etc. in the conforming geometry shown in FIG. Therefore, for example, the side wall region 5
Spacer oxides in areas such as 8 and 60 are now deeply arsenic ions in and through the central region 82 of the n-type surface channel region 38, which is a lightly etched drain implant for the composite island 76, which is the access transistor structure. It can act as an ion implantation mask for the ion implantation process used to form the implant.

This arsenic ion implantation step may also include a deeper arsenic implantation region 84, as shown from left to right in FIG.
86 and 88, and a field oxide region 90
An n + storage node is also formed for the stacked capacitor structure formed above the arsenic implanted region 84 on the left side of FIG. This field oxide region 90 connects the stacked capacitor cells created in the open region 92 on one side of the layer of the composite island 78 to the composite island 7.
8 serves to electrically isolate it from other devices formed on the right side. Thus, the sidewall regions, such as 58 and 60, which are the oxide spacers, are shown at 74 and 7 in FIG.
Electrically separating adjacent complex islands such as 6;
It also serves the dual purpose of serving as an ion implantation mask that exposes a central region 82, which is a deeper arsenic implantation region that transfers charge back and forth from the access transistor. The access transistor is created in the composite island 76 shown in FIG. 2 and charge is transferred to the transistor from which future bit or digit lines are subsequently formed in region 94 as shown in FIG. Transferred to contacts.

Referring now to FIG. 3, a schematic cross-sectional abbreviated view shown in this figure is first deposited to a thickness of about 1500 ° on the exposed top surface of the integrated circuit structure shown in FIG. It is intended to illustrate that a thin layer 96 of silicon dioxide is first formed using a modified and standard tetraethylorthosilicate (TEOS) oxide deposition process. T
After the formation of the thin layer 96 of EOS silicon dioxide is completed, a subsequent layer 98 of polycrystalline silicon (or poly 2) is formed on top of the SiO2 layer 96 as shown, followed by a _second layer of tungsten silicide WSix. Layer 100 is formed on top of second layer 98 of polycrystalline silicon as shown.

As mentioned above, three additional matching layers 9
After completion of 6, 98 and 100, the intermediate structure being processed is transferred to an oxide deposition station where a third coating layer 102 of approximately 4500 ° of silicon dioxide is applied over the second tungsten silicide layer 100 as shown. Is deposited in a tetraethylorthosilicate or TEOS oxide deposition process to cover the exposed surface of.

Referring now to FIG. 4, the previously formed thick TEOS silicon dioxide layer 102 previously described with reference to FIG. 3 has a photoresist strip as shown on the left side of FIG. The mask processing is selectively performed only in the area 104 using the mask 106. The photoresist mask 106 serves to protect the TEOS SiO ₂ oxide strip 104, which in turn is the composite islands 74 and 76 previously described with reference to FIGS.
(See FIG. 2) to protect the bit lines or digit lines extending in the region 94 between them. Thick TE
The OS SiO ₂ layer 102 is removed by etching.
The etching process, thus leaving a thick oxide strip 104 on the bit line formed in region 94, continues, as best understood on the left side of FIG. 4, with tungsten silicide 108 and polysilicon. 2) Continue etching through the layer underlying 110.

As shown, the stacked layers 104, 10
The etching process used to define the aforementioned geometries in 6, 108 and 110 is based on the previously formed TE.
Continue down to the surface of thin layer 96, the OS layer, and then continue to etch to some extent into the surface of thin layer 96, the TEOS oxide layer. Thus, this etching step reduces the thickness of the SiO ₂ layer 96 from its original thickness of approximately 1500 ° to a new thickness of approximately 1000 °.

The intermediate integrated circuit structure shown in FIG. 4 is again transferred to a conventional photoresist deposition and masking station where a thick pattern of photoresist 11 is formed.
2, 114 are deposited and formed into the geometry shown in FIG. Using this masking method, the digit or bit lines, the access transistors and the storage capacitors created in the previously defined regions 94, 76, 92, 78 in FIG. For a subsequent ion implantation step used to create either a p-channel transistor for the peripheral device of the integrated circuit or an n-channel transistor in the n-type well 12 as shown in the lower portion. The photoresist pattern 112 is completely masked.

Thus, while the photoresist pattern 112 currently shown on the left side of FIG. 5 completely covers the device in this portion of the integrated circuit and the silicon chip in the main memory area of the integrated circuit chip, Photoresist pattern 114, as shown on the right side of FIG. 5, has a geometry illustrated to provide openings 118, 120 in preparation for p-type BF ₂ ion implantation in the peripheral device infrastructure of this figure. Is configured. This BF
_{2 The} p-type implant step is used to form the p + source region 126 and the drain region 128 of the p-channel transistor, shown as centered within the previously formed n-type well region 12. Are indicated by p-type ions. This forms an n-type phosphorus "halo" implant that improves short channel PMOS device performance.

Referring now to FIG. 6, the thick photoresist mask 11 previously described with reference to FIG.
2, 114 have been removed. After removal of the photoresist mask, a plurality of second silicon dioxide spacers 13
1 to 141 are formed. As shown in FIG. 6, these silicon dioxide spacers 131-141 are formed in a manner similar to that previously used to form the first SiO ₂ spacer described in connection with FIG. This method involves the combination of the deposition of a silicon dioxide layer followed by an anisotropic etch, and does not require any masking for the purpose of forming the matching regions 131-141 of the spacer shown in FIG. These spacers are used to provide electrical isolation between the various circuit devices being formed. In particular, these spacers are used to provide isolation between the girder lines and future multiple storage nodes.

At this point, a BF ₂ implant can be provided that provides a source / drain implant for the p-channel transistor. BF ₂ is a p-type implant,
Oxide thin layer 96 or photoresist layer 112 (FIG. 5)
Prevents significant implantation into the semiconductor substrate 10, which is a p-type silicon substrate. To the extent that BF ₂ is implanted into semiconductor substrate 10, which is a p-type silicon substrate, this semiconductor substrate 10 provides compensation for other implantations in order to avoid the need for an additional photomask. Alternatively, a BF ₂ injection can be provided at a later stage, as described in connection with FIG.

Referring now to FIG. 7, the structure described above with reference to FIG. 6 is first transferred to a deposition station where a thin layer of oxide 145 is exposed to the integrated circuit structure shown in FIG. Deposited on the surface. A thin layer of oxide 145 is preferably deposited as TEOS oxide.

This structure is then etched to
An opening 152 is provided as shown in FIG. Third layer 113 of polysilicon positioned within region 154 of the IC structure
Forms one layer of a stacked capacitor formed over the thick field oxide region 90 described above in connection with FIG.

Next, a thin capacitor cell dielectric layer 156 of silicon nitride (Si ₃ N ₄ ) is
3 to a thickness of approximately 100 ° on the exposed surface, thus providing the desired high dielectric constant and low thickness for the capacitor dielectric layer, thus maximizing the capacitance per unit area for the laminated capacitor thus formed. To Next, the polycrystalline silicon (poly4) diode 158 is replaced with the thin silicon nitride Si ₃ shown in FIG.
Deposited on top of N ₄ 156 to form a second upper plate of stacked capacitor cells created in general area 154 over thick field oxide area 90. To leave a protective coating against this portion of the integrated circuit, a thin layer 156 of Si ₃ N ₄ on the exposed surface of the right or peripheral portion of the integrated circuit as shown in this figure is also formed.

As shown in FIG. 8, the upper multi-layer is a PMO
It is removed from the periphery of the wafer including the S transistor. This allows for subsequent metal mask connection of the circuitry in the peripheral portion, and also allows any BF ₂ implants to
Applicable to MOS transistors. As shown in FIG. 9, it is possible to use a mask for the purpose of avoiding the blanket implant of BF _2.

Various modifications can be made to the above-described embodiments without departing from the spirit and scope of the present invention.
In addition, there is only a single bit or digit line, a single access transistor, a single stacked capacitor storage cell and only a single p-channel transistor in the perimeter area of the associated word line and integrated circuit structure on each side. The illustrations omitted above for the formation of only a few hundred representatives, and thousands of these devices that can be formed simultaneously during a large scale integrated circuit fabrication process. It will be appreciated by those skilled in the art that they are merely representative.

[Brief description of the drawings]

FIG. 1 shows a preformed n-well, gate oxide (“gate ox”), field oxide (“field o”) with a first layer of polysilicon WSix and a dielectric layer thereon.
x "), showing a schematic cross-sectional view of a wafer being etched.

FIG. 2 is a schematic cross-sectional view showing the formation of an insulating sidewall and another doping of a p-well portion of a wafer.

FIG. 3 is a schematic cross-sectional view showing a deposited dielectric layer on which a silicide layer and a dielectric layer are overlaid.

FIG. 4 is a schematic cross-sectional view showing etching of a silicide layer.

FIG. 5 is a schematic cross-sectional view showing the etching and doping of a wafer on an n-well to form a transistor gate.

FIG. 6 is a schematic cross-sectional view illustrating the use of sidewall formation and blanket BF ₂ implantation.

FIG. 7 is a schematic cross-sectional view illustrating the deposition of multiple layers forming a capacitor plate.

FIG. 8 is a schematic cross-sectional view showing multiple etchings from the periphery.

FIG. 9 is a schematic cross-sectional view showing an optional injection stage used at the periphery.

[Explanation of symbols]

 Reference Signs List 10 semiconductor base material 12 n-type well 14 surface gate dielectric 16 field oxide portion 18 field oxide portion 20 field oxide portion 22 layer 24 layer 26 layer 28 opening 30 opening 32 opening 34 opening 36 n-channel Surface area 38 n-type channel surface area 40 n-type channel surface area 42 n-type channel surface area 44 n-type channel surface area 46 area 48 area 50 area 52 area 54 area 56 side wall area 58 side wall area 60 side wall area 62 side wall area 64 side wall Region 66 sidewall region 68 sidewall region 70 sidewall region 72 sidewall region 74 composite island 76 composite island 78 composite island 80 composite island 82 central region 84 arsenic implanted region 86 arsenic implanted region 88 arsenic implanted region 90 field oxide Area 92 open area 94 area 96 thin layer 98 layer 100 second layer 102 third covering layer 104 area 106 piece 108 tungsten silicide 110 polysilicon 112 pattern 114 pattern 118 opening 120 opening 126 p + source area 128 p + drain Regions 131-141 silicon dioxide spacer 145 thin layer 152 opening 153 third layer 154 region 156 capacitor cell dielectric layer 158 fourth layer

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Tyler A. Lowry East Plateau, Boise 8383 Idaho, USA 2599 (56) References JP-A-58-43556 (JP, A) JP-A-62- 165355 (JP, A) JP-A-62-226055 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/08

Claims (10)

(57) [Claims] A 1. A phase auxiliary type n- channel and method of manufacturing an integrated circuit comprising a p- channel device, a) forming a PMOS and NMOS region (10, 12),
A conductive (22, 24) and non-conductive (1) extending across a peripheral array portion adjacent to a memory array portion of a semiconductor substrate being processed to form a semiconductor device.
4, 26) forming a multi-level layer (14, 22, 24, 26) of transistor gate material; b) generalizing the PMOS region in the peripheral array portion;
The gate electrode layer over the next transistor region.
An n-channel transistor gate is optically formed in the memory array portion and in the NMOS region in the peripheral array portion while remaining in place (photo-d
efining) c) a bit for the n-channel transistor
Implanting n-type dopant ions in a region of said memory array portion adjacent said n-channel transistor gate towards a line or a digit line and in said NMOS region in said peripheral array portion; d) Simultaneously depositing and etching a dielectric spacer in said memory array portion and said NMOS region in said peripheral array portion; e) in said NMOS region in said peripheral array portion and in front of said substrate. The source / drain area (12
6, 128) implanting; f) defining a p-channel transistor (116)
To (to Defining) step, g) forming a simultaneously dielectric spacer to the bit line or digit line and the PMOS transistor, h) an upper portion of said bit line or digit line for the n- channel transistors Forming a multilayer capacitor structure on the memory array , i) ion implantation over the memory array portion
Against while leaving the mask (112), said step of forming a p- channel transistor gates in a semiconductor substrate said peripheral array portion of optically, and, j) for the digit line and the PMOS transistor dielectric
Following the step of simultaneously forming a spacer, is injected into the region of the peripheral array portion adjacent p-type or n-type dopant ions to each p- channel or n- channel transistor gate, said peripheral array Forming said bit line or digit line in a part
Manufacturing method consisting of steps . A 2. A phase complement type n- channel and method of manufacturing an integrated circuit comprising a p- channel devices of: a) forming a PMOS and NMOS regions (10, 12), to form a semiconductor device Multi-level layers (14,22) of conductive (22,24) and non-conductive (14,26) transistor gates extending across a peripheral array portion adjacent to a memory array portion of a semiconductor substrate being processed , 24, 26); b) generalization of the PMOS region in the peripheral array portion;
The gate electrode layer over the next transistor region.
Optically forming an n-channel transistor gate in the NMOS region in the memory array portion and the peripheral array portion, while remaining in place ; c) a bit for the n-channel transistor ;
Implanting an n-type dopant ion implant in a region of said memory array portion adjacent to said n-channel transistor gate towards a line or digit line and in said NMOS region in said peripheral array portion; d) concurrently induced in said memory said digit lines in the array portion and the NMOS region of the peripheral array portion
E) depositing and etching an electrical spacer; e) source / drain regions (1) in the NMOS region in the memory array portion and in the peripheral array portion.
26,128) to an implant formed (Implanting) step, f) depositing a dielectric layer, g) the purpose deposition of the forming a bit contact opening
Etching through the formed dielectric layer ; h) depositing another conductive layer; i) forming a p-channel transistor (116); j) said bit line or digit line; the step of simultaneously forming a dielectric spacer for the PMOS transistor, k) before Symbol forming a capacitor structure in a memory array, l) in ion implantation across the memory array portion
Optically forming a p-channel transistor gate in the peripheral array portion of the semiconductor substrate while leaving a corresponding mask (112) ; and m) for the bit line or digit line and the PMOS transistor. Following the step of simultaneously form formed a dielectric spacer Te, manufacturing method and adjacent to the transistor gate comprises the step of implanting dopant ions in the region of the peripheral array portion. 3. The method according to claim 1, further comprising the step of improving the short- channel characteristics and bit line of the p-channel and n-channel transistors by improving the n-channel gate and the p-channel transistor. -Including insulating spacers formed on the side walls of the channel gate, further between adjacent stacked capacitor structures and
- producing side including forming an insulating spacer positioned on top of the channel transistor gate
Law . 4. The method of claim 1 or claim 2, further comprising a first level of polycrystalline silicon, tungsten silicide.
A second layer of ten and a third layer of silicon dioxide in this order.
Forming the n-channel and the p-channel.
A method of manufacturing comprising forming a gate . 5. A method according to claim 1 or claim 2, further first level of polycrystalline silicon, silicide Tangs
A second layer of ten, a third layer of silicon dioxide, and a
Capacitor layers in this order.
Manufacturing the multilayer capacitor structure.
How . 6. The method according to claim 1, further comprising a first level of polycrystalline silicon, tungsten silicide.
A second layer of ten and a third layer of silicon dioxide in this order.
Forming the n-channel and the p-channel.
Manufacturing including forming Le transient Star Gate
How . 7. The manufacturing method according to claim 1, further comprising: a polycrystalline silicon adjacent to a surface of the semiconductor substrate.
A first layer of silicon, a layer formed on top of the polycrystalline silicon layer.
A second layer of tungsten silicide and the tungsten silicide
A third layer of silicon dioxide formed on top of the
And the n-channel gate and
P-channel gate and multilayer capacitor structure
A manufacturing method including the step of forming a . 8. A phase auxiliary type n- channel and the method of forming the integrated circuit having a p- channel device, a) forming a PMOS and NMOS regions (10, 12), to form a semiconductor device Multi-level layers (14,22) of conductive (22,24) and non-conductive (14,26) transistor gates extending across a peripheral array portion adjacent to the memory array portion of the semiconductor substrate being processed , 24, 26); b) generalization of the PMOS region in the peripheral array portion;
The gate electrode layer over the next transistor region.
Optically forming an n-channel transistor gate in the NMOS region in the memory array portion and the peripheral array portion, while remaining in place ; c) a bit for the n-channel transistor ;
Implanting an n-type dopant ion implant in a region of said memory array portion adjacent to said n-channel transistor gate towards a line or digit line and in said NMOS region in said peripheral array portion; d. E.) Simultaneously depositing and etching dielectric spacers in said NMOS region in said peripheral array portion and in said memory array portion; e) said NMOS in said memory array portion and in said peripheral array portion. source / drain regions in the area (1
26) and 128), f) forming a p-channel transistor (116), and g) simultaneously forming a dielectric spacer on the bit line or digit line and the PMOS transistor. step, h) stacked capacitor structure on top of the bit line or digit line for the n- channel transistors
Forming a step, i) the ion implantation across the memory array portion
Optically forming a p-channel transistor gate in the peripheral array portion of the semiconductor substrate while leaving a corresponding mask (112) ; and j) simultaneously forming a dielectric spacer on the bit line or the gate line.
Continues to forming the digit lines and PMOS transistors, said by implanting p-type or n-type dopant ions into the region of the peripheral array portion, respectively adjacent to the p- channel or n- channel transistor gate integrated circuit forming method comprises the step of forming the bit lines or digit lines in the peripheral array portion. 9. The method of forming an integrated circuit according to claim 8, further comprising a first level of polycrystalline silicon, tungsten silicide.
Second level of ten, third level of silicon dioxide, and above
Form the stacked capacitor plate layers in this order
A method of forming an integrated circuit including steps . 10. The method of forming an integrated circuit of claim 8, further comprising a first level of polycrystalline silicon and a second level of tungsten silicide.
Layer and a third layer of silicon dioxide in this order.
And the n-channel transistor gate
And form an n-channel transistor gate
An integrated circuit forming method including steps .