JP3255155B2 - ATM cell buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to ATM cell data communication, and more particularly to an ATM cell buffer circuit that can quickly start up a PHY layer after recovery when the PHY layer recovers from a failure.

[0002]

2. Description of the Related Art An example of a conventional ATM data transmission system is described in Japanese Patent Application Laid-Open No. 10-107799. The cell transmission rate decoupling method described in this publication is based on the SAR layer bandwidth allocation table.
Scheduling the cell data obtained from the layer, creating scheduling information for valid cells and invalid cells, transmitting a cell control signal indicating the number of valid cells based on the valid cell information for valid cells in the scheduling information, A transmission cell is generated based on the transmission cell start signal notified from the layer to the invalid cell processing unit, the cell control signal is compared with the transmission cell, and only the valid cell is output to the PHY layer.

[0003]

[Problems to be solved by the invention] Utopia lev
Also in the el2 system, when the PHY layer side has a module configuration, cells may stay in the ATM layer due to the module not being mounted in addition to the failure of the PHY layer. In order to discard cells on the ATM layer side, it is necessary to measure the residence time of cells for each cell unit, which has a problem that the circuit becomes very complicated. If no countermeasures are taken against the failure of the PHY layer, the ATM cell for the PHY layer is used when the PHY layer is changed from not mounted or when the PHY layer is reset due to a failure. There is a possibility that a large number of stagnant cells exist in the buffer, and these ATM cells are sent to the PHY layer, causing an overload in the PHY layer and making it impossible to process them.

An object of the present invention is to, when the PHY layer recovers from a failure, forcibly return a transfer enable in response to an inquiry as to whether transfer is possible from the ATM layer.
Drain the remaining ATM cells in the TM layer,
ATM that the HY layer discards the cell received at this time and can quickly start up the PHY layer after recovery
An object of the present invention is to provide a cell buffer circuit.

[0005]

An ATM cell buffer circuit according to the present invention includes a header generation / deletion of ATM cells, a multiplexing / demultiplexing of said ATM, and a virtual path included in at least a layer configuration of an asynchronous transfer mode (ATM). An ATM layer for converting an identifier and a virtual channel identifier; and a physical layer for performing speed matching and synchronization of the ATM cells, generation / restoration and adaptation of a transmission frame, and error control of a header, and an address signal line and a data signal. In an ATM cell buffer circuit that connects the ATM layer and the physical layer via a line and a transfer transmission enable signal line, an acceptability and transfer request from the physical layer is transmitted from the physical layer to the ATM layer. Cl
Oko stomach in av signal, the physical layer, the physical Rei
And an OR circuit for transmitting a transmission enable signal of the
While the physical layer is reset, the OR circuit forcibly
Transmission permission is returned to the ATM layer .

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As an ATM cell transfer method, U
topia (Universal Test & Open
rates PHY Interface for
ATM) system. In the Utopia method, ATM cells are transferred from an upper layer ATM layer to a lower layer PHY layer.

In the Utopia level 2 system, the PHY layer responds with a Clav signal to an inquiry as to whether transfer is possible from the ATM layer. However, when the PHY layer resets the Clav signal output from the PHY layer, the PHY layer is forced to reset. By allowing transmission to
The cells staying in the buffer in the ATM layer are forcibly discharged from the TM layer. Here, the PHY layer is a Physical Layer Device: a physical layer device.

The configuration of an embodiment of the present invention will be described in detail with reference to FIG. FIG. 1 is a diagram showing a configuration of a circuit of an ATM cell buffer according to the present invention. As shown in FIG. 1, the circuit of the ATM cell buffer according to the present invention comprises an ATM layer 10 and a plurality of PHY layers 12-1, 12-2,..., 12-n (n is a natural number). It is connected via a line 16 and a transfer transmission enable signal line 18.

[0009] The PHY layer 12 has an OR circuit 20 for transmitting a transmission enable signal of the PHY layer 12. A
The TM layer 10 has a data signal line 1 connected to the PHY layer 12.
ATM cell buffer 2 for sending data through
2

The ATM layer 10 is connected to a plurality of PHY layers 12-1,..., 12-n. The ATM layer 10 is connected to an address line 14 for selecting the PHY layer 12 in order to inquire the PHY layer 12 whether transmission is possible. The PHY layer has the address line 14
Is monitored and when the user is selected, the transmission enable signal
It is returned to the TM layer 10. In addition, it has an OR circuit 20 immediately before transmitting the transmission enable signal of the PHY layer 12,
While the Y layer 12 is reset, the transmission permission is forcibly returned to the ATM layer 10.

FIG. 2 shows the Utopia level of the present invention.
FIG. 2 is a diagram showing an ATM cell transfer of the l2 system. FIG. 3 is a diagram showing the flow of the Clav signal of the present invention. FIG. 4 is a diagram for drawing the Clav signal of the present invention into the ATM layer. FIG. 5 is a diagram illustrating a method of determining a PHY layer to be transferred by a Clav signal according to the present invention.

The Utopia level 2 system uses the AT
A plurality of PHY layers are connected to the M layer 10,
The PHY layer is managed by the ATM layer. Ut below
The opia Leave2 system will be described with reference to FIG.

From the ATM layer 10 side to the PHY layer 12
The one that transfers ATM cells to the ATM layer is called Tx, and the one that transfers ATM cells from the PHY layer 12 to the ATM layer 10 is called Rx. Tx and Rx operate independently and in parallel. Here, ATM cell transfer is ATM
Of one cell (53 bytes).

In the case of Tx, the ATM layer 10 analyzes the header of the ATM cell and determines a PHY layer number that requires cell transfer. The ATM layer 10 is used for the P which needs cell transfer.
The acceptability of the PHY layer 12 is confirmed with respect to the HY layer 12, and only when the acceptability is accepted, the ATM layer
Selects the PHY layer 12-n and performs ATM cell transfer.

In the case of Rx, the ATM layer 10
It inquires of the HY layer 12 whether there is an ATM cell transfer request, and only when there is a request, the ATM layer 10
Select the PHY layer 12-n for M cell transfer,
The ATM cell is transferred to the Y layer 12-n.

Since ATM cell transfer is performed on a cell basis, the PHY
The layer must make an acceptance (for Tx) or a transfer request (for Rx) on a cell-by-cell basis. PHY
Acceptance from the layer (in the case of Tx) and transfer request (in the case of Rx) are performed by a Clav signal from the PHY layer to the ATM layer.

Next, the Clav signal will be described in detail with reference to FIG. The Clav signal is PHY during Tx operation.
Indicates that the cell can be accepted at layer 12, and when Rx is operating, P
Indicates that there is a cell to be transferred in the HY layer. If there are multiple transferable PHY layers,
Choose one to be fair.

FIG. 4 shows an actual circuit in which the Clav signal operates.
Shown in In an actual circuit, when the Clav signal is drawn from each PHY layer 12-n as a signal line to the ATM layer 10, the number of lines increases, so that the Clav signal is time-divided into one Clav signal line. ATM layer 10 to control time sharing
And polls the PHY layer 12-n.

The polling result is taken into the ATM layer 10 and the Clav taken into the ATM layer 10
FIG. 5 shows a method of determining a PHY layer 12 to be transferred by a signal.
This will be described with reference to FIG. In the case of Tx, the ATM layer 10
There is an ATM cell to send to buffer 22 in
A condition is required that the Clav signal on the PHY layer 12 side can be transferred. ATM cell transfer is performed for the PHY layer 12 that meets this condition. When there are a plurality of PHY layers 12 that meet the conditions for enabling ATM cell transfer, one is selected and ATM cell transfer is performed so as to be fair.

As described above, the PHY is transmitted from the ATM layer 10 to the PHY.
When sending an ATM cell to the layer 12, the ATM layer 10
Makes an inquiry to the PHY layer 12 as to whether transfer is possible, and starts transfer only when transfer is possible. If the transfer is not possible, it temporarily stays in the cell buffer in the ATM layer.

If there is a failure in a particular PHY layer,
When an inquiry is made from the ATM layer to the PHY layer as to whether transfer is possible, the transfer is always disabled and cells for the failed PHY layer stay in the ATM layer.
Thereafter, when the failure of the PHY layer is recovered, a large amount of the staying cells may be sent to the PHY layer, and the PHY layer may be overloaded.

In order to solve this problem, when the PHY layer recovers from the failure, it responds to the inquiry as to whether the transfer is possible from the ATM layer and forcibly returns the transfer possibility, and stops staying in the ATM layer. The discharged ATM cell is discharged. The PHY layer discards the cell received at this time. By doing so, the PH recovered from the failure
The Y layer can start up immediately after restoration.

Next, the operation of the embodiment of the present invention will be described.
ATM layer 10 is always PHY layer 12 and PH
The Y layer 4 is monitored. In the monitoring method, all PHY layers are sequentially polled using the address lines 14 from the ATM layer 10. The PHY layer 12 compares the address line 14 sent from the ATM layer 10 with the address assigned to itself, and if the addresses match, the ATM line
The transfer permission or non-transfer is returned to the layer 10 using the transfer permission signal.

When there is an ATM cell to be transmitted to the PHY layer 12, the ATM layer 10
It is determined from the past polling result whether or not transfer is possible. If transfer is possible, the ATM layer 1 is transmitted through the data signal line 16.
From 0, the ATM cell is transferred to the corresponding PHY layer 12.

When a failure occurs in the PHY layer 12,
In response to an inquiry from the ATM layer 10 to the PHY layer 12 that the transfer is possible by polling, the PHY layer 12 always returns a transfer impossible. At this time, ATM cells to be sent to the PHY layer 12 in the ATM layer 10 are stored in the buffer 22.
Accumulate inside. Thereafter, when the PHY layer 12 is restored by resetting, the reset signal in the PHY layer 12 is input to the OR circuit 14 provided at the output terminal of the transfer enable signal, forcing the transfer enable signal to appear to be transmittable.

The ATM layer 10 has been able to transmit the transfer enable signal of the PHY layer 12,
The accumulated ATM cells for the PHY layer 12 are
Send to Y layer 12. At this time, the PHY layer 12
Since the ATM cell is still being reset, the ATM cell sent from the ATM layer 10 is discarded. By this operation, unnecessary cells in the ATM layer 10 are discarded immediately before the PHY layer 12 starts up, and unnecessary cells are prevented from being received immediately after the PHY layer 12 starts up. Thereafter, the PHY layer 12 completes the reset and rises, and normally returns a transfer enable signal to the ATM layer 10.

Another embodiment of the present invention will be described. By providing, from the PHY layer 12 to the ATM layer 10, means for notifying that the PHY layer 12 has been initialized, separately from the transmission enable signal, the ATM layer 10 can transfer the ATM cells that have accumulated so far to the ATM layer. It can be discarded in the layer 10 buffer. According to this method, since cell discarding can be performed in the ATM layer 10, the cell discarding can be performed without applying a load on the Utopia signal line.

[0028]

As described above, when the PHY layer has a failure, the failure PHY
When a large number of ATM cells for the layer stay in the buffer in the ATM layer and the PHY layer is subsequently restored,
ATM cells remaining in the TM layer are already old information, and are unnecessary for the PHY layer.

The circuit of the ATM cell buffer of the present invention has a P
When the buffer of the ATM layer is emptied at the same time when the HY layer is reset, it is possible to start up quickly without applying an extra load due to the PHY layer receiving old information.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an ATM cell buffer of the present invention.

FIG. 2 shows A of the Utopia level 2 system of the present invention.
It is a figure which shows TM cell transfer.

FIG. 3 is a diagram showing a flow of a Clav signal of the present invention.

FIG. 4 is a diagram for drawing a Clav signal of the present invention into an ATM layer.

FIG. 5 is a diagram illustrating a method of determining a PHY layer to be transferred by a Clav signal according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ATM layer 12 PHY layer 14 Address line 16 Data signal line 18 Transfer enable signal line 20 OR signal 22 Buffer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-11-215141 (JP, A) JP-A-10-107799 (JP, A) JP-A-2000-324131 (JP, A) ATM Forum Utopia Level 12, Version 1.0 af-phy-0039.000 (June 1995) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/56 H04L 12/40 H04L 29/02

Claims (5)

(57) [Claims] An ATM layer included in an asynchronous transfer mode (ATM) layer configuration for generating / deleting an ATM cell header, multiplexing / demultiplexing the ATM, and converting a virtual path identifier and a virtual channel identifier; and a physical layer for performing the error control generation and restoration and adaptation header of velocity matching and synchronization with the transmission frame of the cell, the ATM layer via the address signal line and the data signal line and a transfer-send signal line and in the circuit of ATM cell buffer that connects the physical layer, the receiving-friendly and transfer requests from the physical layer, to put a have a signal having the information of the transfer request from the physical layer towards the ATM layer, the physical layer Sends a transmission enable signal of the physical layer
Further comprising an OR circuit for resetting the physical layer.
During transmission, the ATM circuit confirms that transmission is possible by the OR circuit.
An ATM cell buffer circuit for sending back to an ear . 2. The ATM layer inquires of all the physical layers whether there is an ATM cell transfer request. Only when there is a request, the ATM layer selects the physical layer to perform the ATM cell transfer, and In the physical layer, the A
2. The ATM cell buffer circuit according to claim 1 , wherein the ATM cell buffer performs a TM cell transfer. 3. The ATM layer, when drawing a signal having the information of the transfer request from the plurality of physical layers into the ATM layer as a signal line, time-division-divides the signal of the signal having the information of one transfer request. 3. The ATM cell buffer circuit according to claim 2 , wherein an address line is output from the ATM layer to control time division, and the physical layer is polled. 4. The ATM layer always monitors a plurality of the physical layers using the address signal line, polls all the physical layers in order, and the physical layer is transmitted from the ATM layer. 4. The ATM according to claim 3 , wherein the signal on the address signal line is compared with an address assigned to the ATM layer, and if the address matches, the ATM layer is returned to the ATM layer using a transfer enable signal indicating whether transfer is possible or not. Cell buffer circuit. 5. The ATM layer, when a transmission enable signal of the physical layer becomes available for transmission, an ATM for the physical layer.
5. The ATM cell buffer circuit according to claim 4 , wherein an M cell is sent to the physical layer, and the ATM cell transmitted as the physical layer is still being reset is discarded.