JP3250422B2 - Ferroelectric memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device.

[0002]

2. Description of the Related Art In recent years, a ferroelectric memory device has been devised which realizes non-volatility of stored data by using a ferroelectric material for a capacitor of a memory cell. The ferroelectric capacitor has a hysteresis characteristic, and even when the electric field is zero, remnant polarization having different polarities according to the history remains. A nonvolatile memory device is realized by expressing stored data by remanent polarization of a ferroelectric capacitor.

US Pat. No. 4,873,664 discloses two types of ferroelectric memory devices. In the first type, a memory cell is composed of one transistor and one capacitor (1T1C) per bit. For example, one dummy memory cell (reference cell) for every 256 main body memory cells (normal cells) Is provided. In the second type, a memory cell is composed of two transistors and two capacitors (2T2C) per bit without providing any dummy memory cell, and a pair of complementary data is stored in a pair of ferroelectric capacitors. Is done.

[0004] Ferroelectric materials constituting a capacitor include KNO ₃ (potassium nitrate), PbLa ₂ O ₃ -ZrO ₂
—TiO ₂ (PLZT), PbTiO ₃ —PbZrO _{3 and the} like are known. PCT International Publication No. WO93 / 125
According to No. 42, it is suitable for a ferroelectric memory device,
There is also known a ferroelectric material having extremely small fatigue as compared with PbTiO ₃ -PbZrO ₃ .

According to the 1T1C type ferroelectric memory device disclosed in the above-mentioned US Pat. No. 4,873,664, the dummy memory cell capacitor has at least twice the capacity of the main body memory cell capacitor, that is, at least twice as large. With area. In addition, the main body memory cell capacitor returns to the original polarization state after the polarization is inverted or retains the original polarization state without being inverted, according to the stored data at the time of reading. On the other hand, the dummy memory cell capacitor retains the original polarization state without inversion regardless of the data stored in the main memory cell. In other words, the main memory cell capacitor operates the voltage applied between the electrodes at both positive and negative electrodes, while the dummy memory cell capacitor always operates the voltage applied between the electrodes at one electrode. The voltage applied to the cell plate electrode of the main memory cell capacitor, the voltage applied to the cell plate electrode (dummy cell plate electrode) of the dummy memory cell capacitor, the voltage applied to the word line connected to the gate electrode of the main memory cell transistor, and the dummy voltage The voltage applied to the word line (dummy word line) connected to the gate electrode of the memory cell transistor is equal to the power supply voltage, and
V.

[0006]

In the conventional 1T1C type ferroelectric memory device, the power supply voltage of 5 V is applied to the frequently activated dummy memory cell capacitor as described above, and the number of times of activation is increased. As the number increases, the deterioration of the dummy memory cell capacitor due to the voltage application is quick. Further, the dummy memory cell capacitor retains the original polarization state without being inverted, and always operates in one pole. For this reason, if the characteristics of the ferroelectric memory cell capacitor vary, the set capacitance value of the dummy memory cell capacitor varies with respect to the capacitance value of the main body memory cell capacitor, leading to malfunction.

[0007] In addition, 1T1C type and 2T2
Regardless of the C type, when the power supply voltage becomes high, the voltage applied to the main body memory cell capacitor deteriorates the characteristics of the main body memory cell capacitor and reduces the operation margin.

An object of the present invention is to alleviate the influence of voltage application to a ferroelectric capacitor and prevent malfunction of a ferroelectric memory device.

[0009]

In order to achieve the above object, according to the first to seventh aspects of the present invention, a plurality of ferroelectric capacitors are connected in series to reduce the voltage applied to each ferroelectric capacitor. I have.

[0010] In order to reduce the variation of the set capacitance value of the dummy memory cell capacitor, a plurality of ferroelectric capacitors of the same size are connected in series and in parallel in order to reduce variation in the set capacitance value of the dummy memory cell capacitor. Is what you do.

The tenth to eleventh aspects of the present invention relate to the structure of a ferroelectric capacitor in a ferroelectric memory device. In the eleventh aspect, the connection electrodes of the ferroelectric capacitors connected in series are formed of the same electrode wiring layer .

A twelfth aspect of the present invention provides a first ferroelectric capacitor comprising a first ferroelectric capacitor and a second ferroelectric capacitor, and a third ferroelectric capacitor and a fourth ferroelectric capacitor. Are connected in parallel with each other, and the voltage direction applied to the first series
Of the dummy memory cell capacitor having means for making the voltage directions applied to the series-connected bodies of the above-described series opposite to each other.

[0013]

[0014]

According to the ferroelectric memory device of the present invention, the voltage value applied to the main memory cell capacitor is relaxed, and the ferroelectric memory device has a long life and high reliability. Further, a desired capacitance value can be formed in a direction having a margin with respect to variation. Further, the capacitance value of the dummy memory cell can be formed in a direction having a margin with respect to the characteristic fluctuation of the ferroelectric capacitor.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a ferroelectric memory device according to the present invention will be described below in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention, and FIG. 2 is a diagram showing an operation timing thereof. The ferroelectric memory cell according to the present embodiment has one-bit data composed of two transistors and two ferroelectric capacitors. Complementary data is stored in each ferroelectric capacitor.

In FIG. 1, WL0 to WL255 are word lines, BL and / BL are bit lines, CP is a cell plate electrode, BP is a bit line precharge control signal, SAE is a sense amplifier control signal, VSS is a ground voltage, SA Is a sense amplifier, C0 to C255, C0B to C255B are main body memory cell capacitors each having two ferroelectric capacitors connected in series, and Qn0 to Qn255, Qn0
B to Qn255B and QnBP0 to QnBP2 are N-channel MOS transistors.

First, the circuit diagram of FIG. 1 will be described. The bit lines BL and / BL are connected to the sense amplifier SA. The sense amplifier SA has a sense amplifier control signal S
Controlled by AE. The main body memory cell capacitor C0 is composed of two ferroelectric capacitors connected in series. Here, electrodes at both ends not connected to each other are defined as a first electrode and a second electrode, respectively. The first electrode of the main body memory cell capacitor C0 has a gate electrode connected to the word line W.
It is connected to the bit line BL via the memory cell transistor Qn0 connected to L0, and the second electrode is connected to the cell plate electrode CP. A first electrode of a main body memory cell capacitor C0B formed of two ferroelectric capacitors connected in series and forming a pair with the main body memory cell capacitor C0 has a gate electrode connected to a word line WL0. Bit line / B via Qn0B
L, and the second electrode is connected to the cell plate electrode CP. Other main body memory cell capacitors C1 to C
255, C1B to C255B have the same configuration and connection relationship as the main body memory cell capacitors C0 and C0B. The bit lines BL and / BL are N-channel type M
Connected by the OS transistor QnBP2 and the bit line BL
And ground voltage VSS, and bit line / BL and ground voltage VSS are N-channel MOS transistors QnBP0, QnBP0, respectively.
The gate electrodes of the N-channel MOS transistors QnBP0 to QnBP2 are connected to the bit line precharge control signal BP.

The operation of the circuit of this embodiment will be described with reference to the operation timing chart of FIG. First, in order to read data from the memory cell, the bit line precharge control signal BP is set to the logic voltage “H”, so that the bit lines BL and / BL are set to the ground voltage VSS which is the logic voltage “L”. Further, the word lines WL0 to WL25
5. The cell plate electrode CP is set to the logic voltage “L”. Next, the bit lines BL and / BL are brought into a floating state by setting the bit line precharge control signal BP to the logic voltage “L”. Next, the word line WL0 and the cell plate electrode CP are set to the logic voltage “H”, and the data of the main body memory cell capacitors C0 and C0B are transferred to the bit lines BL and /.
Each is read out to BL. Next, the sense amplifier control signal SAE is set to the logic voltage “H” to operate the sense amplifier SA. Next, the cell plate electrode CP is set to the logic voltage “L”.
, The main memory cell capacitors C0, C0
Rewrite 0B data. Next, the word line WL0
To the logic voltage "L", the main memory cell capacitors C0 and C0B are connected to the bit lines BL and / BL, respectively.
Disconnect from Next, the operation of the sense amplifier SA is stopped by setting the sense amplifier control signal SAE to the logic voltage “L”. Next, by setting the bit line precharge control signal BP to the logic voltage “H”, the bit line B
Let L and / BL be the ground voltage VSS.

As described above, according to the present embodiment, the main memory cell capacitor is composed of two ferroelectric capacitors connected in series, so that the voltage applied to each ferroelectric capacitor is reduced to the voltage applied to the whole. For example, when a total voltage of 5 V is applied, only a voltage of 2.5 V is applied to one ferroelectric capacitor. When the applied voltage is halved, the life of the ferroelectric capacitor is increased by 10 times or more, so that the reliability is greatly improved. However, it is necessary to determine the size of the ferroelectric capacitor while paying attention to the fact that the capacitance value is also reduced to about 1/2 in design. Here, an example in which two ferroelectric capacitors are connected in series is described. However, a configuration in which three or more ferroelectric capacitors are connected in series is also possible. For example, when three ferroelectric capacitors are connected in series, only one third of the voltage is applied to each ferroelectric capacitor.

[Embodiment 2] FIG. 3 is a diagram showing a circuit configuration of a second embodiment of the present invention, and FIG. 4 is a diagram showing an operation timing thereof.

The ferroelectric memory cell in this embodiment is
One-bit data is composed of one transistor and one ferroelectric capacitor.

In FIG. 3, WL0 to WL255 are word lines, DWL0 and DWL1 are dummy word lines, and BL and //.
BL is a bit line, CP is a cell plate electrode, DCP is a dummy cell plate electrode, BP is a bit line precharge control signal, SAE is a sense amplifier control signal, VSS is a ground voltage, SA is a sense amplifier, and C0 to C255 are main body memory cells. Capacitors 101 and 102 each have DC0A
And dummy memory cell capacitors Qn0 to Qn255, Q0B, DC0B, DC1A and DC1B
nD0, QnD1, QnBP0, and QnBP1 are N-channel MOS transistors.
5 is a main memory cell transistor, QnD0, QnD1
Are called dummy memory cell transistors.

First, the circuit diagram of FIG. 3 will be described. The bit lines BL and / BL are connected to the sense amplifier SA. The sense amplifier SA has a sense amplifier control signal S
Controlled by AE. Dummy memory cell capacitor 101
Is a serial connection of dummy memory cell capacitors DC0A and DC0B. Here, electrodes at both ends not connected to each other are defined as a first electrode and a second electrode.
The first electrode of the dummy memory cell capacitor 101 is connected to the bit line / B via a dummy memory cell transistor QnD0 whose gate electrode is connected to the dummy word line DWL0.
L, and the second electrode is a dummy cell plate electrode D
Connected to CP. Similarly, the dummy memory cell capacitors 102 are also dummy memory cell capacitors DC1A and DC1D.
C1B are connected in series, and electrodes at both ends not connected to each other are referred to as a first electrode and a second electrode. A first electrode of the dummy memory cell capacitor 102 is connected to a bit line BL via a dummy memory cell transistor QnD1 whose gate electrode is connected to a dummy word line DWL1, and a second electrode is connected to a dummy cell plate electrode DCP. ing. On the other hand, the first electrode of the main body memory cell capacitor C0 is connected to the bit line BL via the main body memory cell transistor Qn0 whose gate electrode is connected to the word line WL0, and the second electrode is connected to the cell plate electrode CP. Have been. First of the main body memory cell capacitor C1
Are connected to the bit line / B via a main body memory cell transistor Qn1 having a gate electrode connected to the word line WL1.
L, and the second electrode is connected to the cell plate electrode CP.

The operation timing for reading the data held in the main body memory cell capacitor C0 will be described with reference to FIG.

First, the bit line precharge control signal BP is set to the logic voltage "H" as an initial state,
The bit lines BL and / BL are set to the logic voltage “L”. Also,
Word lines WL0 to WL255, dummy word line DWL
0, DWL1, the cell plate electrode CP, and the dummy cell plate electrode DCP are set to the logic voltage “L”. Next, the bit lines BL and / BL are brought into a floating state by setting the bit line precharge control signal BP to the logic voltage “L”. Next, by setting the word line WL0, the dummy word line DWL0, the cell plate electrode CP and the dummy cell plate electrode DCP to the logic voltage “H”, the data of the main body memory cell capacitor C0 is transferred to the bit line BL and the dummy memory cell capacitor DC0 is turned on. Is read out to the bit line / BL. Next, the sense amplifier SA is operated by setting the sense amplifier control signal SAE to the logic voltage “H”. Next, the dummy memory cell capacitor DC0 is disconnected from the bit line / BL by setting the dummy word line DWL0 to the logic voltage "L". Next, by setting the cell plate electrode CP to the logic voltage “L”, the main memory cell capacitor C
0 is rewritten. Also, the dummy cell plate electrode DCP is set to the logic voltage “L”. Next, by setting the word line WL0 to the logic voltage “L”, the main body memory cell capacitor C0 is disconnected from the bit lines BL and / BL. Next, the operation of the sense amplifier SA is stopped by setting the sense amplifier control signal SAE to the logic voltage “L”. Next, by setting the bit line precharge control signal BP to the logic voltage “H”, the bit lines BL, /
BL is set to the ground voltage VSS.

According to the present embodiment, the dummy memory cell capacitor used more frequently than the main body memory cell capacitor is constituted by two ferroelectric capacitors connected in series, so that each of the ferroelectric capacitors is reduced. The voltage is set to の of the voltage applied to the whole,
As a result, the life of the entire memory device can be extended.

[Third Embodiment] A third embodiment of the present invention is an improvement of the configuration of the dummy memory cell capacitor 101 or 102 in the second embodiment, and each ferroelectric capacitor of two ferroelectric capacitors connected in series. In this configuration, the body capacitor can be securely initialized. FIG. 5 is a circuit configuration diagram thereof. FIG. 6 is a diagram showing operation timing.

DWL0 is a dummy word line, BL is a bit line, DCP is a dummy cell plate electrode, DCRST0,
DCRST1 is a control signal for initializing dummy memory cell data, VRST0 and VRST1 are dummy memory cell data initializing voltage signals, DC0A to DC0B are dummy memory cell capacitors, QnD0, QnR0 and QnR1 are N-channel MOS transistors, and N501 and N502 are Nodes P1 and P2 are periods.

First, the circuit diagram of FIG. 5 will be described. Dummy memory cell capacitor DC0A is connected between nodes N501 and N502, and dummy memory cell capacitor DC0B is connected between node N502 and dummy cell plate electrode DCP. Node N50
1 and the bit line BL, and the gate is the dummy word line DWL.
0 through an N-channel type MOS transistor QnD0, the node N501 and the dummy memory cell data initialization voltage signal VRST0 are connected to the control signal DRST at the gate.
N-channel MOS transistor Qn which is CRST0
The node N502 and the dummy memory cell data initialization voltage signal VRST1 are connected via an R-channel MOS transistor QnR1 whose gate is the control signal DCRST1.

The operation of the circuit of the dummy memory cell capacitor will be described with reference to the operation timing chart of FIG. The feature of the operation of this circuit is that the dummy cell plate electrode DCP side of the dummy memory cell capacitor DC0B is reset to a high voltage in the period P1, and the node N502 side of the dummy memory cell capacitor DC0A is reset to a high voltage in the period P2. While keeping the electrodes floating in each ferroelectric capacitor.

According to the present embodiment, each of the two ferroelectric capacitors connected in series can be reliably initialized, a stable capacitance value can be obtained as a dummy memory cell, and a stable operation can be achieved.

[Embodiment 4] Embodiment 4 of the present invention is characterized by a configuration for initializing each ferroelectric capacitor, and is a reset circuit of nodes connected in series as in Embodiment 3. And initialization is performed according to the voltage conditions applied to the electrodes of each ferroelectric capacitor.

FIG. 7 is a diagram showing the circuit configuration. FIG.
, DWL0 is a dummy word line, BL is a bit line, DCP is a dummy cell plate electrode, DCRST0 is a control signal for initializing dummy memory cell data, VRST0
Is a dummy memory cell data initialization voltage signal, DC0A,
DC0B is a dummy memory cell capacitor, QnD0, Qn
nR0 is an N-channel MOS transistor, N701,
N702 is a node. Nodes N501 and N502
Are connected to each other, and a dummy memory cell capacitor DC0B is connected between the node N502 and the dummy cell plate electrode DCP. The node N501 and the bit line BL are connected via an N-channel MOS transistor QnD0 whose gate is a dummy word line DWL0. The node N501 and the dummy memory cell data initializing voltage signal VRST0 are connected to a control signal DCRST0. They are connected via a certain N-channel MOS transistor QnR0.

The operation of the circuit of the dummy memory cell capacitor will be described with reference to the operation timing chart of FIG. The feature of the operation of this circuit is that the voltage of the first electrode is changed from the same voltage state of the first and second electrodes at both ends of the two ferroelectric capacitors connected in series, Execute the case of changing the voltage of the electrode,
Initializing the two ferroelectric capacitors together.

First, DCRST0 is set to the logic voltage "H", the dummy cell plate electrode DCP and the dummy memory cell data initialization voltage signal VRST0 are both set to the logic voltage "L", and the voltage difference between both electrodes is set to 0. Time t1
Then, the dummy cell plate electrode DCP is set to the logic voltage “H”, and the dummy memory cell capacitor DC0B is initialized. Next, at time t2, the dummy memory cell data initialization voltage signal VRST0 is set to the logic voltage “H”, and the voltage difference between the two electrodes is set to 0. At time t3, the dummy memory cell data initialization voltage signal VRST0 is set to the logic voltage "L", and the dummy memory cell capacitor DC0A is initialized. Next, the dummy cell plate electrode DCP is set to the logic voltage "L", and the voltage difference between the two electrodes is set to 0, and then the DCRST0 is set to the logic voltage "L" to complete the initialization operation.

According to the present embodiment, each of the two ferroelectric capacitors connected in series can be securely initialized with a simpler dummy memory cell circuit configuration than that of the above-described third embodiment, and the dummy memory cell can be stabilized. The obtained capacitance value can be obtained, and stable operation can be realized.

[Fifth Embodiment] A fifth embodiment of the present invention is for performing the initialization operation of each ferroelectric capacitor only in a test mode operation other than the normal operation. FIG.
Is a diagram showing the configuration, in which TST1 is a test mode control signal and S1 is an initialization control signal. The dummy memory cell data initialization control signals DCRST0 and DCRST1 are AND signals of the test mode control signal TST1 and the initialization control signal S1. That is, the initialization of the dummy memory cells can be performed only when the test mode control signal TST1 is at the logic voltage “H”.

A feature of the present embodiment is that, for example, the initialization of a semiconductor memory device using a ferroelectric capacitor is performed in a test mode operation state after the manufacture of the semiconductor memory device, and the initialization is not performed in a normal operation. As a result, the number of times or the time when a voltage as high as the power supply voltage is applied to the main body memory cell capacitor for initialization is reduced,
The life of the ferroelectric capacitor can be extended.

[Embodiment 6] In Embodiment 6 of the present invention, in a configuration in which a plurality of ferroelectric capacitors are connected in series as shown in Embodiments 1 to 4, the size of each ferroelectric capacitor is reduced. It is about the same size. The purpose is to make the size comparable,
It is an object of the present invention to make the characteristic fluctuation of each ferroelectric capacitor substantially equal to the variation in manufacturing and to increase a design operation margin. The same shape is preferable not only in the size of the capacitor but also in the structure.

FIG. 10 shows the relationship between the area of the ferroelectric memory cell capacitor and the polarizability. In FIG. 10, reference numeral 100 denotes the characteristic curve.

As is clear from this, there is a region where the polarizability, which indicates the characteristics of the ferroelectric capacitor, decreases as the capacitor area decreases. The effect of this embodiment is particularly great when a ferroelectric memory is manufactured in a region having a small capacitor area.

Seventh Embodiment A seventh embodiment of the present invention uses a plurality of ferroelectric capacitors connected in series and a ferroelectric capacitor connected in parallel. In this configuration, the capacitor is used, for example, as a dummy memory cell. This is because the dummy memory cell capacitor needs to output intermediate data between "L" data and "H" data of the main body memory cell capacitor, and therefore must have a capacitance different from that of the main body memory cell capacitor. This is because there are cases.

FIG. 11 is a diagram showing the structure of a capacitor according to the seventh embodiment of the present invention, and FIG. 12 is a diagram showing the relationship between the capacitor area and the polarizability.

In FIG. 11, C111 to C113 are ferroelectric capacitors, N111 to N113 are nodes, and ferroelectric capacitors C111 and C112 are nodes N.
113 are connected in series, and the ferroelectric capacitors C111,
The other electrodes of C112 are a node N111 and a node N112, respectively. Further, a ferroelectric capacitor C113 is connected between the nodes N111 and N112 in parallel with these. Here, the ferroelectric capacitor C11
1 to C113 have substantially the same size.

In FIG. 12, reference numeral 121 denotes a characteristic curve of each of the ferroelectric capacitors C111 to C113, and 122 denotes a characteristic curve of the ferroelectric capacitors C111 to C112 connected in series. Has become. Reference numeral 123 denotes a characteristic curve of the entire ferroelectric capacitor C111 to C113, and one ferroelectric capacitor characteristic curve 1
It is almost 1.5 times of 21. As described above, by using a plurality of ferroelectric capacitors of the same size to form a capacitor having a desired capacitance value, a design operation margin for manufacturing variations is increased.
In particular, as shown in FIG. 12, when there is a region where the polarizability indicating the characteristics of the ferroelectric capacitor decreases as the capacitor area decreases, the characteristic curves 121 to 123 decrease at the same ratio. An operation margin can be secured.

Embodiment 8 Embodiment 8 of the present invention relates to the structure of a plurality of ferroelectric capacitors connected in series. The connection electrodes of the ferroelectric capacitors connected in series have different electrode wiring layers. It is of composition.

FIG. 13 is a diagram showing the configuration of the ferroelectric capacitor in this embodiment. In FIG. 13, AL denotes an aluminum wiring layer, BE denotes a lower electrode layer, TE denotes an upper electrode layer, FE denotes a ferroelectric layer, and a ferroelectric capacitor C13.
1, C132.

This ferroelectric capacitor is manufactured as follows. For example, a lower electrode layer BE, a ferroelectric layer FE, and an upper electrode layer TE are formed on an insulating film on a semiconductor substrate, and a ferroelectric capacitor C13 is formed from these.
The other parts are removed except for the parts necessary for forming the two C1 and C132. Next, the unnecessary portion of the upper electrode layer TE is removed so as to leave a smaller area than the portion left before. Next, an insulating interlayer film is formed, and thereafter, a contact hole is opened to the lower electrode layer BE and the upper electrode layer TE, and an aluminum wiring layer AL is formed.

According to this embodiment, the ferroelectric capacitor can be formed by two electrode layers, one ferroelectric layer, and a means for connecting each electrode, and can be manufactured with a small number of electrode layers.

Embodiment 9 Embodiment 9 of the present invention also relates to a structure of a plurality of ferroelectric capacitors connected in series, and the connection electrodes of the ferroelectric capacitors connected in series have the same electrode wiring layer. It is of a configuration.

FIG. 14 is a diagram showing a configuration of a ferroelectric capacitor according to the ninth embodiment of the present invention. In FIG.
AL is an aluminum wiring layer, BE is a lower electrode layer, TE is an upper electrode layer, and FE is a ferroelectric layer, forming ferroelectric capacitors C141 and C142.

This ferroelectric capacitor is manufactured as follows. For example, a lower electrode layer BE, a ferroelectric layer FE, and an upper electrode layer TE are formed on an insulating film on a semiconductor substrate, and the ferroelectric capacitors C141 and C141 are formed therefrom.
The other parts are removed while leaving the parts necessary to construct the structure 142 together. Next, the unnecessary portion of the upper electrode layer TE is removed so as to leave a portion having a smaller area than the portion where the unnecessary portion is left. Next, an insulating interlayer film is formed, a contact is made in the upper electrode layer TE, and an aluminum wiring layer AL is formed.

According to this embodiment, two electrode layers of the ferroelectric capacitor and one ferroelectric layer can be formed, the number of electrode layers is small, and the lower electrode layer of the two ferroelectric capacitors is small. BE is connected by the lower electrode layer BE itself.
It is not always necessary to connect the aluminum wiring layer AL to the lower electrode layer BE, and the layout area can be reduced.

[Embodiment 10] Embodiment 10 of the present invention also relates to the structure of a plurality of ferroelectric capacitors connected in series. The ferroelectric capacitors connected in series have a structure of three electrode wiring layers. Things.

FIG. 15 is a diagram showing the structure of the ferroelectric capacitor according to the tenth embodiment. In FIG. 15, AL is an aluminum wiring layer, BE is a lower electrode layer, ME is a middle electrode layer, TE is an upper electrode layer, FE1 and FE2 are ferroelectric layers, and ferroelectric capacitors C151 and C152 are formed. I have.

This ferroelectric capacitor is manufactured as follows. For example, a lower electrode layer BE, a ferroelectric layer FE1, a middle electrode layer ME, a ferroelectric layer FE2, and an upper electrode layer TE are formed on an insulating film on a semiconductor substrate, and the ferroelectric capacitors C151 and C152 are formed therefrom. The other parts are removed while leaving the parts necessary to constitute the above. Next, the middle electrode layer ME, the ferroelectric layer FE2, and the upper electrode layer TE are selectively removed so as to have a smaller area than the portion left before, thereby leaving a portion necessary for the ferroelectric capacitor C152. Next, an insulating interlayer film is formed, contact holes are formed in the upper electrode layer TE and the lower electrode layer BE, and an aluminum wiring layer AL is formed.

According to this structure, two capacitors can be formed hierarchically by three electrode layers and two ferroelectric layers of the ferroelectric capacitor, so that the layout area can be reduced. In addition, since the connection nodes connected in series do not necessarily need to be connected to the aluminum wiring layer AL, the layout area can be reduced.

[Eleventh Embodiment] An eleventh embodiment of the present invention has a configuration in which a plurality of serially connected ferroelectric capacitors are connected in parallel. The direction can be applied. The capacitor having this configuration is used, for example, in a dummy memory cell. This is because the dummy memory cell capacitor needs to output intermediate data between "L" data and "H" data of the main body memory cell capacitor, and therefore, it is necessary to use a capacitor having a capacitance value different from that of the main body memory cell capacitor. Because there is.

FIG. 16 is a diagram showing the structure of the capacitor in this embodiment, and FIG. 17 is an operation timing diagram.

The circuit configuration of FIG. 16 will be described. D
WL0 is a dummy word line, BL is a bit line, DCP0,
DCP1 is a dummy cell plate electrode, DCRST0 is a control signal for dummy memory cell data initialization, VRST0 is a dummy memory cell data initialization voltage signal, DC0A to DC0D.
C0D is a dummy memory cell capacitor, QnD0, Qn
R0 is an N-channel MOS transistor;
N1603 is a node. A dummy memory cell capacitor DC is connected between nodes N1601 and N1602.
0A is connected between the node N1602 and the dummy cell plate electrode DCP0.
C0B is connected, a dummy memory cell capacitor DC0C is connected between the nodes N1601 and N1603, and the node N1603 and the dummy cell plate electrode DCP are connected.
1 is connected to the dummy memory cell capacitor DC0D. The node N1601 and the bit line BL are connected to an N-channel type MO whose gate is a dummy word line DWL0.
Connected through an S transistor QnD0 to a node N1
601 and dummy memory cell data initialization voltage signal VRS
T0 is connected via an N-channel MOS transistor QnR0 whose gate is a control signal DCRST0.

The operation of the circuit of the dummy memory cell capacitor will be described with reference to the operation timing chart of FIG.

The operation of this circuit is characterized in that two sets of two ferroelectric capacitors connected in series and having a capacitance value of １ ／ are prepared, and two sets are connected in parallel. Data "H" for each capacitor
And “L” are initialized.

First, in the initialization period of the period P3, DCRS
T0 is set to the logic voltage “H” and the dummy cell plate electrode D
CP0, the dummy cell plate electrode DCP1, and the dummy memory cell data initialization voltage signal VRST0 are all set to the logic voltage "L", and the voltage difference between both electrodes is set to zero.
Next, the dummy cell plate electrode DCP0 is set to the logic voltage “H”, and the dummy memory cell capacitors DC0A,
DC0B is initialized. Next, the dummy memory cell data initialization voltage signal VRST0 is set to the logic voltage “H” to initialize the dummy memory cell capacitors DC0C and DC0D. Next, the dummy memory cell data initialization voltage signal V
After RST0 is set to the logic voltage "L", the dummy cell plate electrode DCP is set to the logic voltage "L", and the voltage difference between the respective electrodes is set to 0, the DCRST0 is set to the logic voltage "L" to complete the initialization operation. The period P4 is a normal operation period in which only the dummy cell plate electrode DCP0 and the dummy cell plate electrode DCP1 are operated.

According to this embodiment, as a dummy memory cell, two ferroelectric capacitors are connected in series and the capacitance value is set to 1
/ 2 are prepared and two sets of capacitors are connected in parallel. Since the data "H" and "L" are initialized in each of the two sets of capacitors, the data "H" of the main body memory cell is initialized. And "L" are stably supplied even in the case of manufacturing variations. Therefore, a design operation margin can be secured.

Embodiment 12 FIG. 18 shows Embodiment 1 of the present invention.
2 is a diagram illustrating a circuit configuration of FIG. The operation timing is almost the same as that of the second embodiment shown in FIG. The ferroelectric memory cell is composed of one bit of data by one transistor and one ferroelectric capacitor, and the dummy memory cell is shared by a plurality of bit lines.

In FIG. 18, WL0 to WL255 are word lines, DWL0 and DWL1 are dummy word lines, and BL and
/ BL is a bit line, CP is a cell plate electrode, DCP is a dummy cell plate electrode, BP is a bit line precharge control signal, DCRST is a control signal for initializing dummy memory cell data, SAE is a sense amplifier control signal, and VSS is a ground voltage. , SA are sense amplifiers, C0 to C255 are main body memory cell capacitors, DC0 is a dummy memory cell capacitor, Qn0 to Qn255, QnD0, QnD1, Q
nBP0 and QnBP1 are N-channel MOS transistors. Hereinafter, Qn0 to Qn255 are referred to as main memory cell transistors, and QnD0 and QnD1 are referred to as dummy memory cell transistors.

First, the circuit diagram of FIG. 18 will be described. The bit lines BL and / BL are connected to the sense amplifier SA. The sense amplifier SA has a sense amplifier control signal S
Controlled by AE. Dummy memory cell capacitor DC0
Has a gate electrode connected to a dummy word line DWL0.
And the second electrode is connected to the dummy cell plate electrode DCP via the dummy memory cell transistor QnD0 connected to the bit line / BL. A first electrode of the dummy memory cell capacitor DC0 is connected to the bit line BL via a dummy memory cell transistor QnD1 having a gate electrode connected to the dummy word line DWL1, and a second electrode is connected to the dummy cell plate electrode DCP. It is connected. On the other hand, the main body memory cell capacitor C0
Has a gate electrode connected to a bit line BL via a main body memory cell transistor Qn0 connected to a word line WL0, and a second electrode connected to a cell plate electrode CP.
It is connected to the. The first electrode of the main body memory cell capacitor C1 is connected to the bit line / via a main body memory cell transistor Qn1 whose gate electrode is connected to the word line WL1.
The second electrode is connected to the cell plate electrode CP.

The operation timing is substantially the same as in the second embodiment. According to the present embodiment, the layout area of the dummy memory cell capacitor can be reduced by sharing the dummy memory cell capacitor with a plurality of bit lines.
Here, the dummy memory cell capacitor is shared by the bit line pairs, but may be shared by more bit lines.

[0070]

According to the present invention, the voltage value applied to the main memory cell capacitor is relaxed, and a long-life and highly reliable ferroelectric memory device can be obtained. In addition, the ferroelectric capacitor can be formed in a direction with a margin for the characteristic fluctuation,
A ferroelectric memory device that can operate stably can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a circuit configuration of a ferroelectric memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing operation timing of the ferroelectric memory device according to the first embodiment of the present invention;

FIG. 3 is a diagram illustrating a circuit configuration of a ferroelectric memory device according to a second embodiment of the present invention;

FIG. 4 is a diagram showing operation timing of the ferroelectric memory device according to the second embodiment of the present invention;

FIG. 5 is a diagram showing a circuit configuration of a ferroelectric memory device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing operation timings of the ferroelectric memory device according to the third embodiment of the present invention.

FIG. 7 is a diagram showing a circuit configuration of a ferroelectric memory device according to a fourth embodiment of the present invention.

FIG. 8 is a diagram showing operation timings of the ferroelectric memory device according to the fourth embodiment of the present invention.

FIG. 9 is a diagram showing a circuit configuration of a ferroelectric memory device according to a fifth embodiment of the present invention.

FIG. 10 is a diagram showing a relationship between a ferroelectric memory cell capacitor area and a polarizability in Example 6 of the present invention.

FIG. 11 is a diagram showing a circuit configuration of a ferroelectric memory device according to a seventh embodiment of the present invention.

FIG. 12 is a diagram showing a relationship between a ferroelectric memory cell capacitor area and a polarizability in Example 7 of the present invention.

FIG. 13 is a diagram showing a configuration of a ferroelectric capacitor according to an eighth embodiment of the present invention.

FIG. 14 is a diagram showing a configuration of a ferroelectric capacitor according to a ninth embodiment of the present invention.

FIG. 15 is a diagram showing a configuration of a ferroelectric capacitor according to a tenth embodiment of the present invention.

FIG. 16 is a diagram showing a circuit configuration of a ferroelectric memory device according to Embodiment 11 of the present invention.

FIG. 17 is a diagram showing operation timings of the ferroelectric memory device according to the eleventh embodiment of the present invention.

FIG. 18 is a diagram showing a circuit configuration of a ferroelectric memory device according to Embodiment 12 of the present invention.

[Explanation of symbols]

WL0 to WL255 Word line DWL0, DWL1 Dummy word line BL, / BL Bit line and its signal CP Cell plate electrode and its signal DCP, DCP0, DCP1 Dummy cell plate electrode and its signal BP Bit line precharge control signal DCRST0, DCRST1 Dummy memory Cell Data Initialization Control Signals VRST0, VRST1 Dummy Memory Cell Data Initialization Voltage Signal SAE Sense Amplifier Control Signal S1, TST1 Control Signal VSS Ground Voltage VCC Power Supply Voltage SA Sense Amplifiers C111-C113, C131, C132, C141,
C142, C151, C152 Ferroelectric capacitors C0 to C255, C0B to C255B Main memory cell capacitors DC0A to DC0D, DC1A, DC1B Dummy memory cell capacitors Qn0 to Qn255, Qn0B to Qn255B, QnD
0, QnD1, QnR0, QnR1, QnBP0-Qn
BP2 N-channel MOS transistor N501, N502, N701, N702, N111-
N113, N1601 to N1603 Node AL Aluminum wiring layer BE Lower electrode layer ME Middle electrode layer TE Upper electrode layer FE, FE1, FE2 Ferroelectric layer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-76562 (JP, A) JP-A-63-201998 (JP, A) JP-A-5-303881 (JP, A) JP-A 64-64 66897 (JP, A) JP-A-6-177342 (JP, A) JP-A-6-244133 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/22 H01L 27 / 105

Claims (12)

(57) [Claims] A first electrode and a second electrode;
A first ferroelectric capacitor having a first ferroelectric layer sandwiched between second electrodes, third and fourth electrodes,
Having a second ferroelectric layer sandwiched between third and fourth electrodes
And a second ferroelectric capacitor that, the first Tsuyo誘
The electric conductor layer and the second ferroelectric layer are made of the same layer, and the second electrode and the third electrode are connected to each other, and the first ferroelectric layer is connected to the first ferroelectric layer.
Wherein the fourth electrode is connected to a bit line via a transistor having a gate connected to a word line, and the fourth electrode is connected to a cell plate line. 2. The first and second electrodes and said first and second electrodes.
A first ferroelectric capacitor having a first ferroelectric layer sandwiched between second electrodes, third and fourth electrodes,
Having a second ferroelectric layer sandwiched between third and fourth electrodes
That the second strength and a dielectric capacitor, is connected to the front Stories second electrode and the third electrode, connected to the first electrode bit line via a transistor whose gate is connected to word line The fourth electrode is connected to a cell plate line, and means for controlling a voltage applied between the first electrode and the second electrode;
A means for controlling a voltage applied between the first and second electrodes. 3. The first and second electrodes and said first and second electrodes.
A first ferroelectric capacitor having a first ferroelectric layer sandwiched between second electrodes, third and fourth electrodes,
Having a second ferroelectric layer sandwiched between third and fourth electrodes
That the second strength and a dielectric capacitor, is connected to the front Stories second electrode and the third electrode, connected to the first electrode bit line via a transistor whose gate is connected to word line The fourth electrode is connected to a cell plate line, and has means for controlling voltages of the second electrode and the fourth electrode. 4. The first and second electrodes and said first and second electrodes.
A first ferroelectric capacitor having a first ferroelectric layer sandwiched between second electrodes, third and fourth electrodes,
Having a second ferroelectric layer sandwiched between third and fourth electrodes
And a second ferroelectric capacitor that, the first Tsuyo誘
The electric conductor layer and the second ferroelectric layer are made of the same layer, and the second electrode and the third electrode are connected to each other, and the first ferroelectric layer is connected to the first ferroelectric layer.
Are connected to a bit line via a transistor having a gate connected to a word line, the fourth electrode is connected to a cell plate line, and the first electrode and the fourth electrode have the same voltage. Means for changing the voltage of the first electrode from the state of (a), and means for changing the voltage of the fourth electrode from the state where the first electrode and the fourth electrode have the same voltage. A ferroelectric memory device. 5. The ferroelectric memory device according to claim 2, further comprising a test mode control circuit, wherein both means operate only when said test mode control circuit operates. . 6. A main memory cell connected via a first memory cell transistor to a pair of bit lines and to a first bit line of the pair of bit lines so as to form a main memory cell. A ferroelectric capacitor, and a dummy memory cell ferroelectric capacitor connected to a second bit line of the pair of bit lines via a second memory cell transistor so as to form a dummy memory cell. Prepared,
A ferroelectric memory device, wherein the dummy memory cell capacitor is constituted by the ferroelectric capacitor according to claim 1. 7. The ferroelectric memory device according to claim 1, wherein the first ferroelectric capacitor and the second ferroelectric capacitor have substantially the same size. Memory device. 8. The first and second electrodes and said first and second electrodes.
A first ferroelectric capacitor having a first ferroelectric layer sandwiched between second electrodes, third and fourth electrodes,
Having a second ferroelectric layer sandwiched between third and fourth electrodes
A second ferroelectric capacitor that, fifth and sixth electrode
And a third ferroelectric material sandwiched between the fifth and sixth electrodes
And a third ferroelectric capacitor having a layer, the previous SL second electrode and the third electrode is connected, the first electrode and the fifth electrode is connected to the fourth And the sixth electrode are connected, the first electrode is connected to a bit line via a transistor having a gate connected to a word line, and the fourth electrode is connected to a cell plate line. A ferroelectric memory device characterized by the above-mentioned. 9. The ferroelectric memory device according to claim 8, the ferroelectric memory you wherein the size of the first ferroelectric capacitor and the second ferroelectric capacitor is comparable apparatus. 10. The ferroelectric memory device according to claim 1, wherein the second electrode and the fourth electrode are formed of a first wiring layer, and the first electrode and the third electrode are formed of a second wiring. A ferroelectric memory device formed of a layer, wherein the second electrode and the third electrode are connected by a third wiring layer. 11. The ferroelectric memory device according to claim 1, wherein the second electrode and the third electrode are formed and connected by a first wiring layer, and the first electrode and the fourth electrode are connected to each other. A ferroelectric memory device formed of a second wiring layer. 12. The first and second electrodes and said first and second electrodes.
A first ferroelectric layer sandwiched between the first and second electrodes
Ferroelectric capacitor , third and fourth electrodes, and
A second ferroelectric layer sandwiched between third and fourth electrodes;
A second ferroelectric capacitor, and fifth and sixth capacitors.
Third ferroelectric sandwiched between a pole and the fifth and sixth electrodes
A third ferroelectric capacitor having a body layer ;
An eighth electrode and a fourth electrode sandwiched between the seventh and eighth electrodes.
A fourth ferroelectric capacitor having a ferroelectric layer, is connected to the front Stories second electrode and the third electrode, and the sixth electrode and the seventh electrode connected , The first
And the fifth electrode are connected, the first electrode is connected to a bit line via a transistor whose gate is connected to a word line, and the fourth electrode is connected to a first cell plate line. The eighth electrode is connected to a second cell plate line, and a voltage direction applied to a series connection of the first and second ferroelectric capacitors and the third and fourth ferroelectric capacitors are connected. A ferroelectric memory device comprising means for making a voltage direction applied to a series connection of body capacitors opposite to a voltage direction.