JP3249295B2 - Bridge circuit and inverter device - Google Patents

Bridge circuit and inverter device

Info

Publication number
JP3249295B2
JP3249295B2 JP13525394A JP13525394A JP3249295B2 JP 3249295 B2 JP3249295 B2 JP 3249295B2 JP 13525394 A JP13525394 A JP 13525394A JP 13525394 A JP13525394 A JP 13525394A JP 3249295 B2 JP3249295 B2 JP 3249295B2
Authority
JP
Japan
Prior art keywords
voltage
series
diode
arm
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP13525394A
Other languages
Japanese (ja)
Other versions
JPH089656A (en
Inventor
修 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP13525394A priority Critical patent/JP3249295B2/en
Publication of JPH089656A publication Critical patent/JPH089656A/en
Application granted granted Critical
Publication of JP3249295B2 publication Critical patent/JP3249295B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Inverter Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、3レベル出力のブリッ
ジ回路及びインバ―タ装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-level output bridge circuit and an inverter device.

【0002】[0002]

【従来の技術】パルス幅変調(以下PWM)により直流
電力を交流電力に変換する際に、高調波成分を抑制する
インバ―タとして多レベル出力のインバ―タ装置が用い
られる。この種の従来のインバ―タ装置の主回路に用い
られる従来のブリッジ回路を図4に示す。
2. Description of the Related Art When converting DC power into AC power by pulse width modulation (hereinafter referred to as PWM), an inverter having a multi-level output is used as an inverter for suppressing harmonic components. FIG. 4 shows a conventional bridge circuit used for the main circuit of this type of conventional inverter device.

【0003】図4は1相分の構成を示したものであり、
1相当たり3レベルの出力電圧を発生することができ
る。同図において、E1 ,E2 は直流電圧源、S11〜S
14はスイッチ素子、D11〜D16はダイオ―ド、OUTは
出力端子である。また、同図において、Cs11〜Cs14
はスナバ用コンデンサ、Ds11〜Ds14はスナバ用ダイ
オ―ド、Rs11〜Rs14はスナバ用抵抗である。
FIG. 4 shows the structure of one phase.
Three levels of output voltage can be generated per phase. In the figure, E1 and E2 are DC voltage sources, S11 to S11.
14 is a switch element, D11 to D16 are diodes, and OUT is an output terminal. Also, in the same figure, Cs11 to Cs14
Is a snubber capacitor, Ds11 to Ds14 are snubber diodes, and Rs11 to Rs14 are snubber resistors.

【0004】このブリッジ回路の出力端子OUTの出力
電圧は、スイッチ素子S11とS12がオンし、スイッチ素
子S13とS14がオフ状態のとき電圧V1 となり、スイッ
チ素子S12とS13がオンし、スイッチ素子S11とS14が
オフ状態のとき電圧V2 となり、スイッチ素子S13とS
14がオンと、スイッチ素子S11とS12がオフ状態のとき
電圧V3 となり、3レベルの出力が得られる。これらの
スイッチ素子をPWM制御することにより図5に示すよ
うにPWM制御された交流出力電圧が得られる。また、
このときスナバ用コンデンサCs11〜Cs14は、各スイ
ッチ素子S11〜S14がオフ状態のときスナバ用ダイオ―
ドDs11〜Ds14を通してE1 またはE2 に充電され、
図5のVcs11〜Vcs14に示すように、いずれか2つ
のスナバコンデンサによって直流電圧源の電圧に充電さ
れる。そして、各スイッチ素子S11〜S14がオン状態に
なったときスナバ用抵抗Rs11〜Rs14を通して放電さ
れ、1つのスナバコンデンサの充電電圧が零になると、
その分が別のスナバコンデンサで負担される。
The output voltage at the output terminal OUT of this bridge circuit is the voltage V1 when the switching elements S11 and S12 are on and the switching elements S13 and S14 are off, the switching elements S12 and S13 are on and the switching element S11 When S14 and S14 are off, the voltage becomes V2, and the switching elements S13 and S14
When the switch 14 is on and the switch elements S11 and S12 are off, the voltage becomes V3 and a three-level output is obtained. By performing PWM control on these switch elements, an AC output voltage subjected to PWM control can be obtained as shown in FIG. Also,
At this time, the snubber capacitors Cs11 to Cs14 are connected to the snubber diode when the switch elements S11 to S14 are in the off state.
Is charged to E1 or E2 through the nodes Ds11 to Ds14,
As shown by Vcs11 to Vcs14 in FIG. 5, any two snubber capacitors are charged to the voltage of the DC voltage source. When each of the switch elements S11 to S14 is turned on, it is discharged through the snubber resistors Rs11 to Rs14, and when the charging voltage of one snubber capacitor becomes zero,
That amount is borne by another snubber capacitor.

【0005】[0005]

【発明が解決しようとする課題】上記従来構成のブリッ
ジ回路では、スイッチ素子がオンする度にスナバコンデ
ンサの充電電荷がスナバ抵抗で熱として消費されPWM
制御の変調周波数を高くした場合、スナバコンデンサの
充放電の回数が増加するため電力損失が増加するという
問題点がある。
In the above-described bridge circuit of the prior art, each time the switch element is turned on, the charge stored in the snubber capacitor is consumed as heat by the snubber resistor and the PWM is applied.
When the control modulation frequency is increased, there is a problem that the power loss increases because the number of times of charging and discharging of the snubber capacitor increases.

【0006】本発明は、上記問題点を解決するためにな
されたもので、PWM制御の変調周波数を高くしても、
電力損失があまり増加しないブリッジ回路およびインバ
―タ装置を提供することを目的としている。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and even if the modulation frequency of PWM control is increased,
An object of the present invention is to provide a bridge circuit and an inverter device in which power loss does not increase so much.

【0007】[0007]

【課題を解決するための手段】請求項1の発明として、
第1のダイオ―ドを逆並列接続したスイッチ素子を2個
直列接続して成る正側ア―ムと負側ア―ムを直流電圧源
の正負間に直列接続し、この正側ア―ムと負側ア―ムの
接続点を交流出力端子とし、前記正側ア―ムと負側ア―
ムの2個直列接続されたスイッチ素子の中間点と前記直
流電圧源の中間電位点との間にそれぞれ接続された電圧
クランプ用の第2のダイオ―ドを備え、コンデンサと第
3のダイオ―ドの直列回路で成るスナバ回路を前記スイ
ッチ素子にそれぞれ並列接続し、2個直列接続されたス
イッチ素子に接続される前記スナバ回路の第3のダイオ
―ドをそれぞれ直列接続し、直流電圧源側のスイッチ素
子に接続された前記スナバ回路のコンデンサと第3のダ
イオ―ドの接続点と前記中間電位との間にそれぞれ接続
される第1の抵抗と、交流出力端子側のスイッチ素子に
接続された前記スナバ回路のコンデンサと第3のダイオ
―ドの接続点と直流電圧源の正負との間にそれぞれ接続
される第2の抵抗と第4のダイオ―ドの直列回路を設け
たブリッジ回路とする。請求項2の発明として、上記の
ブリッジ回路を少なくとも2回路以上備え、単相あるい
は多相の交流電力を出力するインバ―タ装置とする。
Means for Solving the Problems As a first aspect of the present invention,
A positive arm and a negative arm are connected in series between two switch elements in which a first diode is connected in anti-parallel, and the positive arm is connected between the positive and negative DC voltage sources. The connection point between the negative arm and the negative arm is an AC output terminal, and the positive arm and the negative arm
A second diode for voltage clamping connected between an intermediate point of two series-connected switch elements of the system and an intermediate potential point of the DC voltage source, and a capacitor and a third diode. And a third diode of the snubber circuit connected in series to each of the two switch elements connected in series, and a snubber circuit composed of a series circuit of A first resistor connected between a connection point of the capacitor of the snubber circuit connected to the third switching element and the third diode and the intermediate potential, and a switching element connected to the AC output terminal side. A bridge circuit having a series circuit of a second resistor and a fourth diode respectively connected between the connection point of the capacitor of the snubber circuit and the third diode and the positive and negative of the DC voltage source; That. According to a second aspect of the present invention, there is provided an inverter device that includes at least two or more of the above-described bridge circuits and outputs single-phase or multi-phase AC power.

【0008】[0008]

【作用】請求項1の発明は、直流電圧源側のスイッチ素
子に接続されたスナバ回路のコンデンサが常に所定電圧
に充電され、該スイッチ素子がオフしたときのサ―ジ電
圧を吸収することによって増加する充電電荷は前記第1
の抵抗を介して前記中間電位点に放電され所定電圧に維
持される。交流出力端子側のスイッチ素子に接続された
スナバ回路のコンデンサは、対向するア―ムの2個直列
接続されたスイッチ素子が共にオンしたとき所定の電圧
に充電され、該スイッチ素子がオフしたときのサ―ジ電
圧を吸収することによって増加する充電電荷は前記第2
の抵抗と第4のダイオ―ドを介して直流電圧源に放電さ
れ、自ア―ムの2個直列接続されたスイッチ素子が共に
オンしたとき第2の抵抗と第4のダイオ―ドを介して直
流電圧源に放電され充電電圧は零となる。請求項2の発
明は、各ブリッジ回路の交流出力端子間に所定周波数の
単相あるいは多相の交流電圧を出力する。
According to the first aspect of the present invention, the capacitor of the snubber circuit connected to the switch element on the DC voltage source side is always charged to a predetermined voltage, and the surge voltage when the switch element is turned off is absorbed. The increasing charge charge is the first
And is maintained at a predetermined voltage through the above-mentioned resistor. The capacitor of the snubber circuit connected to the switch element on the side of the AC output terminal is charged to a predetermined voltage when the two switch elements of the opposing arm connected in series are turned on, and when the switch element is turned off. The charge that increases by absorbing the surge voltage of
Is discharged to the DC voltage source via the second resistor and the fourth diode, and when the two serially connected switch elements of the arm are turned on, the second resistor and the fourth diode are used. Then, the battery is discharged to the DC voltage source and the charging voltage becomes zero. According to a second aspect of the present invention, a single-phase or multi-phase AC voltage having a predetermined frequency is output between AC output terminals of each bridge circuit.

【0009】[0009]

【実施例】本発明の請求項1に対応するブリッジ回路の
実施例を図1に示す。図1は、1相分のブリッジ回路の
構成を示したものであり、3レベルの電圧を出力するも
のである。
FIG. 1 shows an embodiment of a bridge circuit according to claim 1 of the present invention. FIG. 1 shows the configuration of a bridge circuit for one phase, which outputs three levels of voltage.

【0010】図1において、直流電圧源は直列接続され
た2つの直流電圧源E1 ,E2 で成り、第1のダイオ―
ドD11〜D14がそれぞれ逆並列接続されたスイッチ素子
S11〜S14を2個直列接続して成る正側ア―ム(S11,
S12,D11,D12)と負側ア―ム(S13,S14,D13,
D14)を備え、正側ア―ムと負側ア―ムを直流電圧源の
正負間に直列接続し、正側ア―ムと負側ア―ムの接続点
を交流出力端子OUTとする。また正側ア―ムと負側ア
―ムの2個直列接続されたスイッチ素子の中間点と直流
電圧源の中間電位V2 の点との間に電圧クランプ用の第
2のダイオ―ドD15,D16を接続する。
In FIG. 1, a DC voltage source comprises two DC voltage sources E1 and E2 connected in series, and a first diode
A positive-side arm (S11, S11, D14) is formed by connecting two switch elements S11-S14 connected in series in anti-parallel with each other.
S12, D11, D12) and the negative arm (S13, S14, D13,
D14), the positive arm and the negative arm are connected in series between the positive and negative DC voltage sources, and the connection point between the positive arm and the negative arm is an AC output terminal OUT. A second diode D15 for voltage clamping is provided between an intermediate point of two serially connected switch elements of a positive arm and a negative arm and an intermediate potential V2 of the DC voltage source. Connect D16.

【0011】また、コンデンサCs11〜Cs14と第3の
ダイオ―ドDs11〜Ds14をそれぞれ直列接続して成る
スナバ回路を各スイッチ素子S11〜S14にそれぞれ並列
接続し、2個直列接続されたスイッチ素子S11,S12及
びS13,S14に接続されるスナバ回路の第3のダイオ―
ドDs11,Ds12及びDs13,Ds14をそれぞれ直列接
続する。また、直流電圧源側のスイッチ素子S11,S14
に接続されたスナバ回路のコンデンサと第3のダイオ―
ドの接続点と中間電位V2 との間にそれぞれ第1の抵抗
Rs11,Rs14を接続し、交流出力端子OUT側のスイ
ッチ素子S12,S13に接続されたスナバ回路のコンデン
サと第3のダイオ―ドの接続点と直流電圧源の正負との
間に第2の抵抗Rs12,Rs13と第4のダイオ―ドDs
15,Ds16の直列回路をそれぞれ接続する。
A snubber circuit formed by connecting capacitors Cs11 to Cs14 and a third diode Ds11 to Ds14 in series is connected in parallel to each of the switch elements S11 to S14, and two switch elements S11 are connected in series. , S12 and the third diode of the snubber circuit connected to S13, S14
Ds11 and Ds12 and Ds13 and Ds14 are connected in series. Also, the switching elements S11, S14 on the DC voltage source side
Of the snubber circuit connected to the 3rd diode
The first resistors Rs11 and Rs14 are respectively connected between the connection point of the node and the intermediate potential V2, and the capacitor of the snubber circuit connected to the switch elements S12 and S13 on the side of the AC output terminal OUT and the third diode are connected. And the fourth resistor Ds12, Rs13 between the connection point of the DC voltage source and the fourth diode Ds.
15 and Ds16 are connected in series.

【0012】上記構成において、交流出力端子OUTに
は、図2に示すようにスイッチ素子S11とS12がオン
し、スイッチ素子S13とS14がオフ状態のとき電圧V1
が出力され、スイッチ素子S12とS13がオンし、スイッ
チ素子S11とS14がオフ状態のとき電圧V2 が出力さ
れ、スイッチ素子S13とS14がオンし、スイッチ素子S
11とS12がオフ状態のとき電圧V3 が出力され、3レベ
ルの出力が得られる。これらのスイッチ素子を高い変調
周波数でPWM制御することにより正弦波の交流出力電
圧が得られる。
In the above configuration, when the switch elements S11 and S12 are turned on and the switch elements S13 and S14 are turned off as shown in FIG.
Is output, the switching elements S12 and S13 are turned on, and when the switching elements S11 and S14 are in the off state, the voltage V2 is output, and the switching elements S13 and S14 are turned on and the switching element S
When V11 and S12 are off, the voltage V3 is output, and a three-level output is obtained. By performing PWM control on these switch elements at a high modulation frequency, a sine wave AC output voltage can be obtained.

【0013】また、スイッチ素子S11とS12がオンし、
S13とS14がオフ状態のとき、コンデンサCs13とCs
14には直流電圧源の電圧E1 +E2 が直列に印加され、
スイッチ素子S13とS14がオンし、S11とS12がオフ状
態のとき、コンデンサCs11とCs12には直流電圧源の
電圧E1 +E2 が直列に印加される。また、スイッチ素
子S12とS13がオンし、S11とS14がオフ状態のとき、
コンデンサCs11とCs14には直流電圧源の電圧E1 +
E2 が直列に印加される。
Further, the switching elements S11 and S12 are turned on,
When S13 and S14 are off, capacitors Cs13 and Cs
14, the voltage E1 + E2 of the DC voltage source is applied in series,
When the switch elements S13 and S14 are turned on and S11 and S12 are off, the voltage E1 + E2 of the DC voltage source is applied to the capacitors Cs11 and Cs12 in series. When the switch elements S12 and S13 are turned on and S11 and S14 are turned off,
The capacitors Cs11 and Cs14 have a voltage E1 +
E2 is applied in series.

【0014】交流出力端子OUTにV1 とV2 の電圧を
交互に繰り返して出力するとき、コンデンサCs11,C
s13,Cs14は直流電圧源の電圧で定まる所定の電圧に
充電され、この状態を図2の正モ―ドの期間に示す。ま
た、交流出力端子OUTにV2 とV3 の電圧を交互に繰
り返して出力するとき、コンデンサCs11,Cs12,C
s14は直流電圧源の電圧で定まる所定の電圧に充電さ
れ、この状態を図2の負モ―ドの期間に示す。この図2
に示すようにコンデンサCs11とCs14は常に所定の電
圧に充電される。
When the voltages V1 and V2 are alternately and repeatedly output to the AC output terminal OUT, the capacitors Cs11 and Cs11
S13 and Cs14 are charged to a predetermined voltage determined by the voltage of the DC voltage source, and this state is shown in the positive mode period in FIG. Also, when the voltages V2 and V3 are alternately and repeatedly output to the AC output terminal OUT, the capacitors Cs11, Cs12, Cs
S14 is charged to a predetermined voltage determined by the voltage of the DC voltage source, and this state is shown in the negative mode period of FIG. This figure 2
As shown in (1), the capacitors Cs11 and Cs14 are always charged to a predetermined voltage.

【0015】スイッチ素子S11とS12がオンし、S13と
S14がオフしたとき、コンデンサCs11の充電電圧が電
圧E1 より高ければ抵抗Rs11を介して直流電圧源E1
に放電されE1 の電圧に維持される。従って、スイッチ
素子S11がオフしたとき、アノ―ド、カソ―ド間に生じ
るサ―ジ電圧を吸収することによって増加するコンデン
サCs11の充電電荷の一部は直流電圧源に回生される。
When the switching elements S11 and S12 are turned on and S13 and S14 are turned off, if the charging voltage of the capacitor Cs11 is higher than the voltage E1, a DC voltage source E1 is connected via a resistor Rs11.
And is maintained at the voltage of E1. Therefore, when the switch element S11 is turned off, a part of the charged electric charge of the capacitor Cs11 which is increased by absorbing the surge voltage generated between the anode and the cathode is regenerated to the DC voltage source.

【0016】また、スイッチ素子S13とS14がオンし、
S11とS12がオフしたとき、コンデンサCs14は前述と
同様にしてE2 の電圧に維持される。スイッチ素子S12
とS13がオンし、S11とS14がオフしたとき、コンデン
サCs12の充電電圧がE1 より高ければ、抵抗Rs12と
ダイオ―ドDs15の直列回路を介して直流電圧源へ放電
電流が流れ、コンデンサCs12の充電電圧はE1 以下に
維持される。コンデンサCs13の充電電圧も同様にして
E2 以下に維持される。
The switching elements S13 and S14 are turned on,
When S11 and S12 are turned off, the capacitor Cs14 is maintained at the voltage of E2 in the same manner as described above. Switch element S12
When S13 and S13 are turned on and S11 and S14 are turned off, if the charging voltage of the capacitor Cs12 is higher than E1, a discharging current flows to the DC voltage source through the series circuit of the resistor Rs12 and the diode Ds15, The charging voltage is kept below E1. Similarly, the charging voltage of the capacitor Cs13 is maintained at E2 or lower.

【0017】また、スイッチ素子S11とS12がオンし、
S13とS14がオフしたとき、コンデンサCs12に充電電
荷があれば抵抗Rs12とダイオ―ドDs15を介して直流
電圧源E1 に放電され一部の充電電荷が直流電圧源に回
生され、コンデンサCs12のの充電電圧はほぼ零とな
る。
Further, the switching elements S11 and S12 are turned on,
When S13 and S14 are turned off, if there is a charge in the capacitor Cs12, the charge is discharged to the DC voltage source E1 via the resistor Rs12 and the diode Ds15, and a part of the charge is regenerated to the DC voltage source. The charging voltage becomes almost zero.

【0018】またスイッチ素子S13とS14がオンし、S
11とS12がオフしたとき、コンデンサCs13の充電電圧
は前述と同様にしてほぼ零となる。以上に述べた作用に
より、交流出力端子OUTにV1 とV2 の電圧を繰り返
して出力するとき、図2の正モ―ド期間に示すように、
コンデンサCs11,Cs13,Cs14の電圧Vcs11,V
cs13,Vcs14はほぼE1 ,E2 の電圧に維持され、
コンデンサCs12の電圧Vcs12は零となる。また、V
2 とV3 の電圧を繰り返して出力するとき、図2の負モ
―ド期間に示すように、Vcs11,Vcs12,Vcs14
はほぼE1 ,E2 に維持されVcs13は零となる。
The switch elements S13 and S14 are turned on, and S
When 11 and S12 are turned off, the charging voltage of the capacitor Cs13 becomes substantially zero as described above. When the voltages V1 and V2 are repeatedly output to the AC output terminal OUT by the operation described above, as shown in the positive mode period of FIG.
Voltages Vcs11, Vs of capacitors Cs11, Cs13, Cs14
cs13 and Vcs14 are substantially maintained at the voltages of E1 and E2,
The voltage Vcs12 of the capacitor Cs12 becomes zero. Also, V
When the voltages 2 and V3 are repeatedly output, as shown in the negative mode period of FIG. 2, Vcs11, Vcs12, and Vcs14 are output.
Is maintained substantially at E1 and E2, and Vcs13 becomes zero.

【0019】本実施例によれば、各スイッチ素子がオン
する度に、スナバコンデンサの充電電荷が全て電力損失
として消費されることがなくなり、高い変調周波数でP
WM制御を行っても電力損失を少なくすることができ
る。
According to the present embodiment, every time each switch element is turned on, the charge stored in the snubber capacitor is not consumed as power loss, and P
Even if WM control is performed, power loss can be reduced.

【0020】本発明の請求項2に対応するインバ―タ装
置の実施例を図3に示す。図3において、3〜4は図1
に示したブリッジ回路であり、直流電圧源1,2の電圧
V1 ,V2 ,V3 が端子V1 ,V2 ,V3 に加えられ、
端子OUTからそれぞれ3レベルの電圧V1 ,V2 ,V
3 が出力される。6は各ブリッジ回路3〜4をPWM制
御する信号Su,Sv,Swを出力するインバ―タ制御
部である。
FIG. 3 shows an embodiment of an inverter device according to a second aspect of the present invention. In FIG. 3, reference numerals 3 and 4 represent FIG.
Wherein the voltages V1, V2, V3 of the DC voltage sources 1, 2 are applied to the terminals V1, V2, V3,
Three levels of voltages V1, V2, V
3 is output. Reference numeral 6 denotes an inverter control unit for outputting signals Su, Sv, Sw for controlling the bridge circuits 3 to 4 by PWM.

【0021】上記構成において、インバ―タ制御部6は
各ブリッジ回路3〜4のスイッチ素子S11〜S14をオン
オフさせるためのPWM信号Su,Sv,Swを出力す
るとき、各ブリッジ回路3〜4の交流出力端子OUTか
ら出力される電圧が 120°の位相差を持った正弦波電圧
となるように高い変調周波数でPWM信号を出力する。
これにより、品質の良い3相交流電圧を出力することが
できる。なお、ブリッジ回路を2個にして単相交流電圧
を出力することも可能であり、種々変形して実施するこ
とができる。
In the above configuration, when the inverter control section 6 outputs the PWM signals Su, Sv, Sw for turning on and off the switch elements S11 to S14 of each of the bridge circuits 3 to 4, it outputs the PWM signals Su, Sv, Sw. A PWM signal is output at a high modulation frequency so that the voltage output from the AC output terminal OUT becomes a sine wave voltage having a phase difference of 120 °.
Thereby, a high-quality three-phase AC voltage can be output. Note that it is also possible to output a single-phase AC voltage by using two bridge circuits, and various modifications can be made.

【0022】[0022]

【発明の効果】請求項1の発明によれば、直流電圧をP
WM制御により交流電圧に変換する際に、変調周波数を
増加させてPWM制御を行っても電力損失が少なく、変
換効率の向上したブリッジ回路を提供することができ
る。
According to the first aspect of the present invention, the DC voltage is P
When converting to an AC voltage by WM control, even if PWM control is performed by increasing the modulation frequency, a bridge circuit with reduced power loss and improved conversion efficiency can be provided.

【0023】請求項2の発明によれば、高い変調周波数
で上記ブリッジ回路のPWM制御を行い高品質の単相あ
るいは多相の交流電圧を出力し、しかも変換効率の向上
したインバ―タ装置を提供することができる。
According to the second aspect of the present invention, there is provided an inverter device which performs PWM control of the bridge circuit at a high modulation frequency, outputs a high-quality single-phase or multi-phase AC voltage, and has an improved conversion efficiency. Can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の請求項1に対応するブリッジ回路の実
施例の構成図
FIG. 1 is a configuration diagram of an embodiment of a bridge circuit according to claim 1 of the present invention.

【図2】上記実施例の作用を説明するためのタイムチャ
―ト
FIG. 2 is a time chart for explaining the operation of the embodiment.

【図3】本発明の請求項2に対応するインバ―タ装置の
実施例の構成図
FIG. 3 is a configuration diagram of an embodiment of an inverter device according to claim 2 of the present invention.

【図4】従来のブリッジ回路の構成図FIG. 4 is a configuration diagram of a conventional bridge circuit.

【図5】上記従来のブリッジ回路の作用を説明するため
のタイムチャ―ト
FIG. 5 is a time chart for explaining the operation of the conventional bridge circuit.

【符号の説明】 E1 ,E2 …直流電圧源 S11〜S14…スイッチ素子 D11〜D14…(第1の)ダイオ―ド D15,D16…(第2の)ダイオ―ド Ds11〜Ds14…(第3の)ダイオ―ド Ds15,Ds16…(第4の)ダイオ―ド Cs11〜Cs14…コンデンサ Rs11,Rs14…(第1の)抵抗 Rs12,Rs13…(第2の)抵抗 1,2…直流電圧源 3〜5…本発明のブリッジ回路 6…インバ―タ制御部[Description of Signs] E1, E2 DC voltage sources S11 to S14 Switching elements D11 to D14 (first) diodes D15 and D16 (second) diodes Ds11 to Ds14 (third) ) Diodes Ds15, Ds16 ... (fourth) diodes Cs11 to Cs14 ... capacitors Rs11, Rs14 ... (first) resistors Rs12, Rs13 ... (second) resistors 1,2 ... DC voltage sources 3 to 5. Bridge circuit of the present invention 6. Inverter control unit

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 第1のダイオ―ドを逆並列接続したスイ
ッチ素子を2個直列接続して成る正側ア―ムと負側ア―
ムを直流電圧源の正負間に直列接続し、この正側ア―ム
と負側ア―ムの接続点を交流出力端子とし、前記正側ア
―ムと負側ア―ムの2個直列接続されたスイッチ素子の
中間点と前記直流電圧源の中間電位点との間にそれぞれ
接続された電圧クランプ用の第2のダイオ―ドを備え、
コンデンサと第3のダイオ―ドの直列回路で成るスナバ
回路を前記スイッチ素子にそれぞれ並列接続し、2個直
列接続されたスイッチ素子に接続される前記スナバ回路
の第3のダイオ―ドをそれぞれ直列接続し、直流電圧源
側のスイッチ素子に接続された前記スナバ回路のコンデ
ンサと第3のダイオ―ドの接続点と前記中間電位との間
にそれぞれ接続される第1の抵抗と、交流出力端子側の
スイッチ素子に接続された前記スナバ回路のコンデンサ
と第3のダイオ―ドの接続点と直流電圧源の正負との間
にそれぞれ接続される第2の抵抗と第4のダイオ―ドの
直列回路を設けたことを特徴とするブリッジ回路。
1. A positive-side arm and a negative-side arm comprising two series-connected switch elements in which a first diode is connected in anti-parallel.
The positive arm and the negative arm are connected in series, and the connection point between the positive arm and the negative arm is used as an AC output terminal, and two of the positive arm and the negative arm are connected in series. A second diode for voltage clamp connected between an intermediate point of the connected switch element and an intermediate potential point of the DC voltage source;
A snubber circuit composed of a series circuit of a capacitor and a third diode is connected in parallel to the switch element, respectively, and the third diodes of the snubber circuit connected to two switch elements connected in series are connected in series. A first resistor connected between a connection point of the capacitor of the snubber circuit connected to the switch element on the DC voltage source side and a third diode and the intermediate potential, and an AC output terminal. A series connection of a second resistor and a fourth diode respectively connected between the connection point of the capacitor of the snubber circuit connected to the switch element on the side and the third diode and the positive and negative of the DC voltage source. A bridge circuit comprising a circuit.
【請求項2】 請求項1に記載のブリッジ回路を少なく
とも2回路以上備え、単相あるいは多相の交流電力を出
力することを特徴とするインバ―タ装置。
2. An inverter device comprising at least two or more bridge circuits according to claim 1, and outputting single-phase or multi-phase AC power.
JP13525394A 1994-06-17 1994-06-17 Bridge circuit and inverter device Expired - Lifetime JP3249295B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13525394A JP3249295B2 (en) 1994-06-17 1994-06-17 Bridge circuit and inverter device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13525394A JP3249295B2 (en) 1994-06-17 1994-06-17 Bridge circuit and inverter device

Publications (2)

Publication Number Publication Date
JPH089656A JPH089656A (en) 1996-01-12
JP3249295B2 true JP3249295B2 (en) 2002-01-21

Family

ID=15147397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13525394A Expired - Lifetime JP3249295B2 (en) 1994-06-17 1994-06-17 Bridge circuit and inverter device

Country Status (1)

Country Link
JP (1) JP3249295B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3262495B2 (en) * 1996-06-03 2002-03-04 株式会社東芝 Multi-level inverter
US5982646A (en) * 1998-06-30 1999-11-09 General Electric Company Voltage clamp snubbers for three level converter
WO2006090694A1 (en) 2005-02-22 2006-08-31 Citizen Holdings Co., Ltd. Pointer indication type timepiece
CN104040868A (en) * 2012-01-12 2014-09-10 皇家飞利浦有限公司 Inverter with less snubber capacitors
CN107040157B (en) * 2017-06-21 2023-08-08 佛山科学技术学院 Multi-level converter topology with coupling inductor
CN112542947B (en) * 2019-09-20 2023-05-09 南京南瑞继保电气有限公司 Conversion circuit, front-end circuit, sub-module, direct current converter and control method
JP7293095B2 (en) * 2019-11-26 2023-06-19 東芝インフラシステムズ株式会社 power converter

Also Published As

Publication number Publication date
JPH089656A (en) 1996-01-12

Similar Documents

Publication Publication Date Title
JP3262495B2 (en) Multi-level inverter
Hota et al. An optimized three-phase multilevel inverter topology with separate level and phase sequence generation part
US8508957B2 (en) Power conversion device for converting DC power to AC power
US11205919B2 (en) Uninterruptible power supply system
WO2013105156A1 (en) Multilevel power conversion circuit
JP5515386B2 (en) Snubber circuit for three-level power converter
JPS6160667B2 (en)
Zhang et al. A hybrid modulation method for single-phase quasi-Z source inverter
JP3249295B2 (en) Bridge circuit and inverter device
Raj et al. A modified charge balancing scheme for cascaded H-bridge multilevel inverter
US12040618B2 (en) Power conversion system including a second circuit being configured to control a current or power such that the current or the power is synchronized with power ripples caused by the AC power supply or the AC load
JP2004080880A (en) Snubber circuit
GB2337643A (en) Power converter
JPH09331684A (en) Non-insulated type uninterruptible power-supply unit
Iwaya et al. Novel multilevel PWM wave control method using series connected full bridge inverters
CN110277926B (en) DC-AC converter and control method thereof
JPH04334977A (en) Power converter
JP2001314086A (en) Ac-dc converter
JPH10285953A (en) Power converter
CN114785175B (en) AC/DC multi-port three-level converter
Ajaykumar et al. Fault tolerant control of Z-source neutral point clamped inverter
JP3276126B2 (en) Bridge circuit and inverter device
CN114785173B (en) AC/DC multi-port three-level converter with boosting capability and modulation method thereof
JP3150521B2 (en) Bridge circuit and inverter device
Kedika et al. A Nine-Level Inverter for Open Ended Winding Induction Motor Drive with Fault-Tolerance

Legal Events

Date Code Title Description
S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071109

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081109

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081109

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091109

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091109

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101109

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111109

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121109

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121109

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131109

Year of fee payment: 12

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term