JP3247037B2 - Rake receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rake receiving apparatus (hereinafter referred to as a "rake receiving apparatus").

[0002]

2. Description of the Related Art Generally, in a mobile communication system, data transmitted from a transmitting device is reflected by a building or the like or diffracted by a building or the like, and transmitted to a receiving device via a plurality of propagation paths. arrive. Therefore, if the receiving device demodulates the received data as it is, the signal-to-noise ratio (hereinafter, referred to as “SNR”) of the demodulated data decreases.

In order to cope with this problem, a mobile communication system employing a spread spectrum communication system as a communication system generally uses a rake system as a reception system.

Here, the rake method is to despread received data while changing the phase of a spreading code, thereby separating a plurality of delayed waves included in the received data, and dividing the separated delayed waves into phases. This is a receiving method that enhances the SNR of demodulated data by combining and aligning.

[0005] As a rake receiving apparatus using a rake method as a receiving method, conventionally, a receiving apparatus described in the following document is known.

References: Takashi Asahara, Toshiharu Kojima, Makoto Miyake, Tadashi Fujino "Weighted Average RAKE Method with Forgetting Factor and Its Simplification" IEICE Technical Report SST 92-70 (1993-3).

[0007]

In the rake receiving apparatus, as described above, while sequentially changing the phase of the spread code, a plurality of delayed waves included in the received data are separated to detect a delayed wave to be demodulated. Time may be longer.

However, if the time spent for detecting the delayed wave to be demodulated becomes longer, the current phase of the delayed wave to be demodulated becomes unclear, and it becomes impossible to specify the phase of the delayed wave to be demodulated. Problems arise.

[0009]

In order to solve the above-mentioned problems, the present invention sets the code length of a spread code to N (N is an integer of 2 or more) times the correlation length, and sets each chip of the spread code , And generates data indicating a chip number as a reference when detecting the phases of a plurality of delay waves included in the received data, while changing the phase of the same spread code as the spread code for spread modulation. By despreading the received data using the spreading code, the phases of a plurality of delayed waves included in the received data are detected using the chip number, and the difference between the data indicating the detected phase and the reference chip number data is detected. , The relative phase between the plurality of delay waves and the reference chip number data is obtained, and the absolute phase of the delay wave is obtained by adding the data indicating the relative phase and the reference chip number data to obtain the absolute phase. By despreading the received data by a spreading code having a phase, in which so as to demodulate the delayed wave included in the received data.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[Configuration and Operation of First Embodiment] [Configuration of Rake Receiver] First, the configuration of the rake receiver will be described.

FIG. 1 is a block diagram showing a configuration of a rake receiving apparatus according to a first embodiment of the present invention.

The rake receiver shown in the figure has a reception data input terminal 11 and chip clock input terminals 12 (1) and 12 (1).
(2), 12 (3) and symbol clock input terminal 13
, The reference phase generator 14, the phase detector 15, the demodulators 16 (1) and 16 (2), and the phase controllers 17 (1) and 1 (1).
7 (2), a synthesizing unit 18 and a demodulated data output terminal 19.

Here, to the reception data input terminal 11, for example, reception data R whose frequency band has been converted from a radio frequency band to a base frequency band is supplied. The received data R is data that has been spread-modulated using a spreading code.

The code length L of the spreading code is N of the correlation length T.
(N is an integer of 2 or more) times. As a result, the transmission data is spread-modulated by N symbols by one spreading code.

Each chip of the spread code is assigned a number. Also, numbers are given to N symbols modulated by one spreading code. This symbol number is represented by an integer part of a quotient obtained by dividing the chip number by the correlation length T.

In the following description, a case where the correlation length T is 64 and the spreading code length L is 81290, as shown in FIG. 2, will be described as a representative.

In this case, the transmission data is spread modulated by 1280 symbols by one spreading code. The chip numbers are represented by 0 to 81919 as shown in FIG. Further, the symbol numbers are represented by 0 to 1279.

Chip clock input terminals 12 (1) to 12 (1) to 12
(3) is supplied with a chip clock TC having the same frequency as the chip repetition frequency and used as one of the reference clocks in the rake receiver.

The symbol clock input terminal 13 is supplied with a symbol clock SC having the same frequency as the symbol repetition frequency and used as one of the reference clocks in the rake receiver.

The reference phase generator 14 has a function of generating data RT indicating a chip number which is a reference when detecting the phases of a plurality of delay waves included in the received data R. This generation is performed in synchronization with the chip clock TC supplied to the chip clock input terminal 12 (3).

Further, the reference phase generator 14 has a function of generating data RS indicating a symbol number serving as a reference when aligning phases of demodulated data of a plurality of delay waves included in the received data R. This generation is performed in synchronization with the symbol clock SC supplied to the symbol clock input terminal 13.

The phase detector 15 despreads the received data R over the entire space using the same spreading code as the spreading code for spreading modulation, while changing the phase of the spreading code by, for example, one chip at a time. This has a function of detecting the phases of a plurality of delay waves included in the reception data R using the chip number. This detection is performed, for example, repeatedly at a predetermined cycle.

The phase detector 15 detects two delayed waves D having large power of the despread output among the detected phases.
1 and D2 indicating phase and reference chip number data R
By calculating the difference between the two delayed waves D1,
It has a function of detecting the relative phase between D2 and the reference chip number data RT.

The demodulation section 16 (1) receives data RP1 indicating the relative phase of the delayed wave D1 detected by the phase detection section 15.
And the reference chip number data RT by adding
It has a function of generating data indicating the absolute phase of the delay wave D1.

The demodulation unit 16 (1) generates a spread code having the obtained absolute phase, and despreads the received data R with the spread code, thereby obtaining a delayed wave D1 included in the received data R. Has the function of demodulating the

Further, the demodulation section 16 (1) divides the chip number of the demodulation spreading code by the correlation length T and extracts the integer part thereof to generate data DMS1 indicating the number of the symbol being demodulated. Has functions.

Although a detailed description is omitted, the demodulation unit 1
6 (2) also has a function similar to that of the demodulation unit 16 (1).

The phase controller 17 (1) has a function of controlling the phase of the demodulated data DM1 of the delay wave D1 based on the reference symbol number data RS and the demodulated symbol number data DMS1. This control is performed by the symbol clock terminal 13
Is performed in synchronization with the symbol clock SC supplied to.

Although detailed description is omitted, the phase control unit 17 (2) also has the same function as the phase control unit 17 (1).

The synthesizing section 18 has a phase control section 17 (1), 1
7 (2), the demodulated data DM1M and DM whose phases have been controlled.
2 and a function of generating demodulated data DM of the received data R.

The demodulated data output terminal 19 is supplied with demodulated data DM of the received data R.

[Operation of Rake Receiving Apparatus] The operation of the above configuration will be described.

The data R received by an antenna (not shown) is supplied to a reception data input terminal 11 after the frequency band is converted from a radio frequency band to a base frequency band by digital demodulation. The reception data R supplied to the reception data input terminal 11 is supplied to the phase detection unit 15 and the demodulation unit 1.
6 (1) and 16 (2).

In parallel with this, the reference phase generator 14
The reference chip clock data RT is generated in synchronization with the chip clock TC. This reference chip number data RT
Is a phase detector 15 and demodulators 16 (1) and 16 (2)
Supplied to

The reference phase generator 15 synchronizes the reference symbol number data R with the symbol clock SC.
Generate S. The reference symbol number data RS is supplied to the phase controllers 17 (1) and 17 (2).

The phase detector 15 despreads the received data R with the spreading code while sequentially changing the phase of the spreading code by one chip. Thereby, the phases of the plurality of delay waves included in the reception data R are detected. in this case,
The phases of the plurality of delayed waves are represented by chip numbers when the power of the despread output increases.

When the phase detector 15 detects the phases of the plurality of delayed waves, the phase detector 15 outputs data indicating the phases of the two delayed waves D1 and D2 having large despread output power and the reference chip number data RT. Find the difference between Thus, the relative phase between the delay waves D1 and D2 and the reference chip number data RT is detected. The data RP1 and RP2 indicating the detected relative phase are respectively supplied to the demodulation units 16 (1) and 16
It is supplied to (2).

The demodulation section 16 (1) receives the relative phase data RP
1 is added to the reference chip number data RT. Thereby, data indicating the absolute phase of the delay wave D1 is obtained. When the absolute phase is obtained, the demodulation unit 16 (1) generates a spread code having this phase, and despreads the received data R with the spread code. As a result, demodulated data DM1 of the delayed wave D1 is obtained.

In parallel with the demodulation processing, the demodulation unit 16
In (1), a process of dividing a chip number given to a demodulation spreading code by a correlation length T and extracting an integer part of the quotient is executed. As a result, data DMS1 indicating the number of the symbol being demodulated is obtained.

The demodulated data DM1 and the demodulated symbol number data DMS1 of the delay wave D1 are supplied to the phase control unit 17 (1). The phase of demodulated data DM1 supplied to phase control section 17 (1) is controlled based on reference symbol number data RS and demodulated symbol number data DMS1.

Although a detailed description is omitted, the demodulation unit 1
6 (2) performs the same processing as the demodulation unit 16 (1). Thereby, the delayed wave D included in the reception data R
2 demodulated data DM2 and demodulated symbol number data DMS
2 is generated.

Also, in the phase control unit 17 (2),
The same processing as that performed by the phase control unit 17 (1) is performed. Thus, the phase of the demodulated data DM2 of the delayed wave D2 is controlled based on the reference symbol number data RT and the demodulated symbol number data DMS2.

As a result, the phases of the demodulated data DM1 and DM2 of the delayed waves D1 and D2 are aligned. As a result, demodulated data DM1 and DM2 having the same symbol number are output from phase control sections 17 (1) and 17 (2).

The demodulated data DM1 and DM2 are supplied to the synthesizing unit 18 and synthesized. As a result, the demodulated data D
M1 and DM2 are combined so as to combine the same symbol numbers. As a result, demodulated data DM having a high SNR is obtained at the demodulated data output terminal 19.

[Configuration of Reference Phase Generation Unit 14] Next, the configuration of the reference phase generation unit 14 will be described in detail.

FIG. 4 is a block diagram showing the configuration of the reference phase control unit 14.

The illustrated reference phase generator 14 has a reference chip counter 21 and a reference symbol counter 22.

The reference chip counter 21 is composed of an 81920 decimal counter and has a function of generating the reference chip number data RT by counting the chip clock TC.

The reference symbol counter 22 is composed of a 1280-base counter and has a function of generating the reference symbol number data RS by counting the symbol clock SC.

[Operation of Reference Phase Generation Unit 14] The operation of the above configuration will be described.

The chip clock TC supplied to the chip clock input terminal 12 (3)
Is supplied as a counting clock. This allows
The count value of the counter 21 is repeatedly updated from 0 to 81919 in synchronization with the chip clock TC. As a result, reference chip number data RT having a predetermined phase and indicating a chip number assigned to each chip of the spread code is obtained.

The symbol clock SC supplied to the symbol clock input terminal 13 is supplied to the reference symbol counter 22
Is supplied as a counting clock. This allows
The count value of the counter 22 is repeatedly updated from 0 to 1279 in synchronization with the chip clock TC. As a result, reference symbol number data R having a predetermined phase and indicating a chip number assigned to each symbol of received data R
S is obtained.

[Configuration of Demodulator 16 (n)] Next, the configuration of the demodulator 16 (n) (n = 1, 2) will be described.

FIG. 5 is a block diagram showing a configuration of the demodulation unit 16 (n).

As shown, the demodulation unit 16 (n) includes an addition unit 31, a seed generation unit 32, and a spread code generation unit 33.
, A delayed wave demodulator 34 and a demodulated symbol number calculator 35
Having.

The adder 31 receives the reference chip number data RT
And the relative phase data RPn to generate data APn indicating the absolute phase of the delayed wave Dn.

The seed generator 32 is constituted by, for example, a central processing unit, and each time the relative phase indicated by the relative phase data RPn is changed, the absolute phase data A
It has a function of generating a seed SE for generating a spreading code having an absolute phase indicated by Pn.

The seed generator 32 outputs demodulation chip number data DM indicating the chip number of the spreading code for demodulation.
It has a function of generating Tn.

The spreading code generator 33 has a function of generating a spreading code having a phase specified by the seed SE using a shift register and an exclusive OR circuit.
This generation is performed in synchronization with the chip clock TC.

The delay wave demodulation unit 34 includes a spreading code generation unit 33
Has a function of demodulating the delayed wave Dn included in the received data R by despreading the received data R with the spreading code generated in step (1).

The demodulation symbol number calculation unit 35 divides the demodulation chip number indicated by the demodulation chip number data DMT1 by the correlation length T and extracts the integer part of the quotient, thereby obtaining the demodulation symbol number indicating the number of the symbol being demodulated. It has a function of generating data DMSn.

[Operation of Demodulator 16 (n)] The operation of the above configuration will be described.

The relative phase data RPn output from the phase detector 15 is supplied to the adder 31 and is added to the reference chip number data RT. Thereby, data APn indicating the absolute phase of the delayed wave Dn is obtained. That is, data indicating the current phase of the delayed wave Dn is obtained.

The absolute phase data APn is supplied to the seed generator 32. The seed generator 32 takes in the absolute phase data APn every time the relative phase data RPn is changed, and generates a seed SE for generating a spread code having an absolute phase indicated by the absolute phase data APn. . The spreading code control unit 32
Is demodulated chip number data DMT indicating a chip number of a spreading code for demodulation based on the absolute phase data APn.
Generate n.

The generated seed SE is supplied to the spreading code generator 33. Also, demodulation chip number data DMT
n is supplied to the demodulation symbol number calculation unit 35.

Each time the seed SE is changed, the spreading code generator 33 loads this seed SE into an internal shift register. As a result, a spread code having a phase specified by the seed SE is generated.

This spread code is supplied to the delay wave demodulator 34 and used as a spread code for demodulation. As a result, the received data R is despread by the spreading code. As a result, the delayed wave Dn included in the received data R is demodulated.

The demodulated chip number data DMTn supplied to the demodulated symbol number calculating section 35 is divided by the correlation length T to extract the integer part of the quotient. Thus, demodulated symbol number data D indicating the number of the symbol being demodulated
MSn is obtained.

[Configuration of Phase Control Unit 17 (n)] Next, the configuration of the phase control unit 17 (n) will be described.

FIG. 6 is a block diagram showing a configuration of the phase control unit 17 (n).

The illustrated phase control unit 17 (n) includes a data storage unit 41, a data writing unit 42, and a data reading unit 4
3

The data storage section 41 has 1280 registers. Each register is given a number from 0 to 1279.

The data writing section 42 has a function of writing the demodulated data DMn of the delayed wave Dn to the register having the same number as the symbol number indicated by the demodulated symbol number data DMSn.

The data reading section 43 has a function of reading demodulated data DMn from a register having the same number as the symbol number indicated by the reference symbol number data RS.

[Operation of Phase Control Unit 17 (n)] The operation of the above configuration will be described.

The delayed wave D output from the demodulator 16 (n)
The demodulated data DMn of n
The data is written to the data storage unit 41 in symbol units. In this case, the demodulated data DMn is the demodulated symbol number data D
The data is written to the register having the same number as the symbol number indicated by MSn. For example, demodulated symbol number data D
If the symbol number indicated by MSn is 2, the demodulated data DMn is written to the register assigned with number 2.

The demodulated data DMn written in the demodulated data storage section 41 is read by the demodulated data reading section 43 in symbol units. In this case, the demodulated data DMn
Is read from a register provided with the same number as the reference symbol number indicated by the reference symbol number data RS. For example, if the symbol number indicated by the reference symbol number data RS is 1, the demodulated data DMn
Are read from the register numbered 1.

In this case, the reference symbol number data RS
Is shared by the two phase controllers 17 (1) and 17 (2). Thereby, the phase control units 17 (1) and 17 (2)
From the demodulated data DM1 and DM2 having the same symbol number.
Is obtained.

[Effects of the First Embodiment] According to this embodiment described in detail above, the following effects can be obtained.

(1) First, according to this embodiment, the code length of the spread code is set to N times the correlation length, a number is assigned to each chip of the spread code, and the phase of the delay wave Dn is detected. By generating data RT indicating a chip number serving as a reference when performing the above, and changing the phase of the same spreading code as the spreading code for spreading modulation, the received data R is despread with this spreading code, thereby producing a delayed wave Dn. Of the delay wave Dn and the reference chip number data RT by calculating the difference between the data indicating the detected phase and the reference chip number data RT. Data RPn indicating the phase and reference chip number data RT
Is added to obtain the absolute phase of the delayed wave Dn. Therefore, even if the time spent for detecting the delayed wave Dn becomes longer, the current phase of the delayed wave Dn can be accurately detected. it can.

As a result, even when the time spent for detecting the delayed wave Dn becomes longer, it can be accurately demodulated.

(2) Further, according to this embodiment,
R indicating a symbol number serving as a reference when aligning the phases of demodulated data DM1 and DM2 of two delayed waves D1 and D2
When S is generated and the delayed waves D1 and D2 are demodulated, the chip number of the demodulated spreading code is divided by the correlation length T to detect the number of the symbol being demodulated, and the demodulated symbol number and the reference symbol number are used. Since the phases of the delayed waves D1 and D2 are controlled on the basis of this, even in a propagation environment where the time difference between the two delayed waves D1 and D2 is one symbol time or more, the phases of the demodulated data DM1 and DM2 can be aligned. it can.

Thus, the two demodulated data DM1, D
When combining M2, it is possible to combine symbols having the same number and to combine symbols having a large reception power separated by one symbol time or more, thereby increasing the SNR of the demodulated data DM. .

That is, the conventional rake receiving apparatus uses a code having the same code length as the correlation length as the spread code. However, in such a configuration, when the time difference between the delayed waves is equal to or longer than one symbol time, different symbols are combined,
There is a problem that a symbol having a large reception power separated by a symbol time or more cannot be synthesized.

On the other hand, in this embodiment, the code length of the spread code is set to N times the correlation length, and the phase of the delay wave is controlled based on the demodulated symbol number and the reference symbol number. The time difference between the delayed waves is 1
Even in a propagation environment having a symbol time or more, it is possible to solve a problem that different symbols cannot be combined or a symbol having a large reception power separated by one symbol time or more cannot be combined.

(3) According to this embodiment, when controlling the phase of the demodulated data DMn of the delay wave Dn, the data storage unit 41 having a plurality of registers corresponding to each symbol number is provided. When the demodulation data DMn is written to the storage unit 41, the demodulation data is written to the register having the same number as the demodulation symbol number. When the demodulation data DMn is read from the demodulation data storage unit 41, the demodulation data is read from the register having the same number as the reference symbol number. , So that the phase control unit 17 (n) which is easy to design
Can be provided.

(4) According to this embodiment, when generating a demodulation spread code, a spread code having this phase is generated based on the absolute phase detection output of the delayed wave Dn. Since a seed is generated and a spread code for demodulation is generated based on the seed, the spread code for demodulation is generated using a normal spread code generation circuit including a shift register and an exclusive OR circuit. Can be generated.

[Second Embodiment] [Overview] This embodiment is characterized by the configuration of the demodulation unit 16 (n). Specifically, the present invention has a feature in a configuration for generating a demodulation spread code.

That is, in the first embodiment, a case has been described in which a spread code for demodulation is generated using a circuit having a shift register and an exclusive OR circuit.

On the other hand, in this embodiment, a spread code for demodulation is generated using a memory for storing waveform data of the spread code.

[Structure] FIG. 7 is a block diagram showing the structure of the demodulation unit 16 (n) according to the second embodiment. In FIG. 7, for the sake of simplicity, the parts that perform substantially the same functions as those in FIG. 5 are given the same reference numerals, and detailed descriptions thereof are omitted.

7 differs from FIG. 5 mainly in that a spreading code storage unit 51 is provided in place of the spreading code generation unit 33 and that an address generation unit 5 is provided in place of the seed generation unit 32.
2 is provided.

Here, the spreading code storage section 51 has 81920 addresses corresponding to each chip number of the spreading code, and stores the waveform data of the corresponding chip in each address. The spread code storage unit 51 is configured by, for example, a read-only memory (ROM). However, a magnetic or optical memory may be used instead of such an electrical memory.

The address generation unit 52 is provided with the spread code storage unit 5
1 has a function of generating an address for reading out waveform data. The address generation unit 52 has an 81920 decimal counter for counting the chip clock TC,
Each time the value of the relative phase data RPn changes, the counter is loaded with the absolute phase data APn, and the counter counts the chip clock TC to generate a read address of the waveform data.

[Operation] The operation of the above configuration will be described.

When the value of the relative phase data RPn changes,
The absolute phase data A is stored in the internal counter of the address generator 52.
Pn is loaded. This allows this counter to:
The chip clock TC is counted from the absolute phase indicated by the absolute phase data APn. as a result,
A count value indicating the absolute phase of the delay wave Dn is obtained.

This count value is supplied to the spread code storage unit 51 as a read address. As a result, the spread code waveform data is read from the address corresponding to the absolute phase of the delay wave Dn. As a result, a spreading code having the same phase as the absolute phase of the delayed wave Dn is obtained.

[Effects] In this embodiment described in detail above, the same effects as the effects (1) to (3) of the first embodiment can be obtained, and further, the following effects can be obtained. Can be obtained.

That is, according to this embodiment, the spread code storage unit 51 having an address corresponding to each chip number of the spread code and storing the waveform data of the chip corresponding to each address is provided. Since the storage unit 51 accesses the storage unit 51 based on the absolute phase data APn, the demodulation spread code is generated. Therefore, the configuration for generating the demodulation spread code is simplified as compared with the previous embodiment. Can be

[Third Embodiment] [Overview of Third Embodiment] This embodiment is characterized by the configuration of the phase control unit 17 (n) and the configuration of the reference phase generation unit 14. is there.

That is, in the first embodiment, the demodulated data storage unit 41 having a plurality of registers corresponding to each symbol number is provided, and the data storage unit 41 stores the delay wave Dn
When the data DMn is written, the data DMn is written to the register having the same number as the demodulation symbol number, and when the demodulation data DMn is read, the phase of the demodulation data DMn is controlled by reading from the register having the same number as the reference symbol number. explained.

On the other hand, in the present embodiment, the difference between the demodulated symbol number and the reference symbol number is obtained, and the demodulated data DMn is delayed by a time corresponding to the difference.
The phase of the demodulated data DMn is controlled.

In the first embodiment, the case where the reference symbol number is updated and the case where the reference symbol number is updated one by one from 0 has been described.

On the other hand, in this embodiment, the average value of the demodulated symbol numbers of the delayed waves D1 and D2 at the start of demodulation is obtained, and the average value is updated one by one.

[Configuration and Operation of Third Embodiment] [Configuration of Reference Phase Generation Unit 14] FIG. 8 is a block diagram showing a configuration of the reference phase generation unit 14 in this embodiment. In FIG. 8, for the sake of simplicity, the parts that perform substantially the same functions as those in FIG. 4 are given the same reference numerals, and detailed descriptions thereof are omitted.

In FIG. 8, the main difference from FIG. 4 is that an average calculator 61 is added to the configuration of FIG.

This average value calculation section 61 is
At the start of demodulation in (1) and 16 (2), the demodulation unit 16
It has a function of calculating an average value of demodulated symbol number data DMS1 and DMS2 output from (1) and 16 (2).

[Operation of Reference Phase Generating Unit 14] The operation of the above configuration will be described.

The demodulated symbol number data DMS1 and DMS2 output from the demodulators 16 (1) and 16 (2) are supplied to the average calculator 61. This average value calculation unit 61
When demodulation sections 16 (1) and 16 (2) start demodulation, demodulated symbol number data DM1, DM
An average value of two data is obtained. Data indicating the average value is set in the reference symbol counter 22. Thus, the value of the reference symbol number data RS is sequentially updated one by one from the above average value at the start of demodulation.

[Configuration of Phase Control Unit 16 (n)] FIG.
FIG. 3 is a block diagram illustrating a configuration of a phase control unit 16 (n) according to the embodiment.

The illustrated phase control section 16 (n) has a shift register 71, a subtraction section 72, and a data input section 73.

The shift register 71 has a function of sequentially shifting input data in synchronization with the symbol clock SC. The shift register 71 has, for example, seven registers, and data can be input to any of the seven registers. Each register is given a number. This number is 3 in the data shift direction in order.
2, 1, 0, -1, -2, -3 are set.

The subtracting section 72 calculates the demodulated symbol number data D
It has a function of obtaining data I indicating the difference between MSn and reference symbol number data RS.

The data input section 73 has a function of writing the demodulated data DMn to a register having the same number as the value of the difference data I.

[Operation of Phase Control Unit 17 (n)] The operation of the above configuration will be described.

The demodulated symbol number data DMSn output from the demodulation unit 16 (n) is supplied to the subtraction unit 72, where the reference symbol number data RS is subtracted. This allows
Data I indicating the difference between the demodulated symbol number and the reference symbol number is obtained.

The difference data I is supplied to the data input section 73. The data input unit 73 is connected to the demodulation unit 16 (n)
Is input to a register having the same number as the difference indicated by the difference data I.

The data input to the register is sequentially shifted in synchronization with the symbol clock SC. As a result, the phases of the demodulated data DM1 and DM2 output from the demodulators 16 (1) and 16 (2) are aligned.

This will be described below with reference to a specific example.

For example, when a symbol having the same number as the reference symbol number is demodulated, that is, when the phase of the demodulated symbol is the same as the phase of the reference symbol, the difference data I is 0.
Becomes As a result, the demodulated data DMn is written to the 0th register. As a result, the demodulated data DMn becomes 3
Delayed by clock.

When a symbol having a number smaller than the reference symbol number by one is demodulated, that is, when the phase of the demodulated symbol is one symbol behind the phase of the reference symbol, the difference data becomes -1. Thus, the demodulated data DMn is input to the -1st register. As a result, the demodulated data DMn is delayed by two clocks.

Further, when a symbol having a number greater than the reference symbol number by one is demodulated, that is, when the phase of the demodulated symbol is one symbol ahead of the phase of the reference symbol, the difference data I becomes 1. Thus, the demodulated data DMn is input to the first register. As a result, the demodulated data DMn is delayed by four clocks.

As described above, the demodulation units 16 (1), 16
The phases of the demodulated data DM1 and DM2 output from (2) are aligned.

In FIG. 9, shift register 71
Is set to 7 because it is assumed that the difference between the demodulated symbol number and the reference symbol number falls within the range of ± 3. Therefore, if this difference does not fall within the range of ± 3, the number of registers may be increased.

[Effects of Third Embodiment] According to this embodiment described in detail above, (1) and (2) of the first embodiment will be described.
The same effects as (3) and (4) can be obtained, and further, the following effects can be obtained.

(1) First, according to this embodiment, a difference between demodulated symbol number data DMSn and reference symbol number data RS is obtained, and demodulated data DMn is delayed by shift register 71 by a time corresponding to the difference. Thus, the phases of the demodulated data DM1 and DM2 are made uniform, so that the number of registers of the shift register 71 can be reduced as compared with the first embodiment. In the example of FIG. 9,
The number of registers can be reduced from 1279 to 7.

(2) According to this embodiment, when generating reference symbol number data RS, the average value of demodulated symbol number data DMS1 and DMS2 at the start of demodulation is generated as an initial value. , 0 as the initial value, the number of registers of the shift register 71 can be reduced.

[Fourth Embodiment] [Overview] In this embodiment, as in the third embodiment, the difference between the demodulated symbol number data DMSn and the reference symbol number data RS is determined, and this difference is calculated. In the configuration for delaying the demodulated data DMn based on this, the method is characterized in how to find the difference between the demodulated symbol number data DMSn and the reference symbol number RS.

That is, in the third embodiment, the demodulated symbol number data DMSn and the reference symbol number data R
The case where the difference from S is calculated and both are calculated as described above has been described.

On the other hand, in this embodiment, the demodulated symbol number data DMSn and the reference symbol number data RS
Is calculated after data compression.

[Structure] FIG. 10 is a block diagram showing the structure of the phase control unit 17 (n) of this embodiment. In FIG. 10, for the sake of simplicity of description, parts that perform substantially the same functions as the components of FIG. 9 are given the same reference numerals, and detailed description thereof will be omitted.

FIG. 10 differs from FIG. 9 in that demodulation symbol number compression section 81, reference symbol number compression section 82, and difference calculation section 83 are provided instead of subtraction section 72.

Here, the demodulation symbol number compression section 81
It has a function to compress the demodulated symbol number data DMSn. This data compression is performed by, for example, the upper M (M is 2
This is performed by converting data of the above (integer) bits into 1-bit data by a logical sum operation.

The reference symbol number compression section 82 has a function of compressing the reference symbol number data RS. This data compression is also performed by converting upper M-bit data into 1-bit data by a logical OR operation.

When the symbol numbers are represented by 0 to 1279, the symbol number data DMSn, RS
Expressed in bits. In this embodiment, for example, the upper 7 bits of the 11-bit symbol number data RS and DMSn are converted into 1-bit data by a logical OR operation. Thus, the 11-bit symbol number data DMSn, RS is converted into 5-bit symbol number data DMSn, RS.

The difference calculator 83 calculates two symbol number data DMSn, RS before data compression based on two symbol number data DMSn, RS before data compression and two symbol number data DMSn, RS after data compression. RS
Has a function of obtaining difference data I of

In this case, the code IS and the size IM of the difference data I are, for example, in the following three cases (a) to (a).
(C) is set separately.

In the following description, the demodulated symbol number data DMn of 11 bits is represented by A [10] to A [0]. Here, A [10] represents the most significant bit data, and A [0] represents the least significant bit data. Also, data A [10] to A [4] of the upper 7 bits of this data
Is expressed as AOR.

Similarly, the 11-bit reference symbol number data RS is represented by S [10] to S [0]. Where S
[10] represents the data of the most significant bit, and S [0] represents the data of the least significant bit. Also, 1-bit data obtained by performing a logical sum operation on the upper 7-bit data S [10] to S [4] of the data S is represented as SOR.

In the following description, it is assumed that the difference between demodulated symbol number data A [10] to A [0] and reference symbol number data S [10] to S [0] falls within a range of ± 3. ing.

(A) Demodulated symbol number data A [10]
A [10] to A [3] of the upper 8 bits (= M + 1 = 7 + 1) of the reference symbol number data S
Upper 8-bit data S [10] of [10] to S [0]
In this case, 11-bit demodulated symbol number data A [10] to A [0] before data compression and 11-bit reference symbol number data S [10] to S [0] are used. Difference data I
Are represented by the sign and magnitude of the difference data between the 5-bit demodulated symbol number data AOR to A [0] after data compression and the 5-bit reference symbol number data SOR to S [0]. You.

For example, 11-bit demodulated symbol number data “000000000101” (10
5) and 11-bit reference symbol number data "00"
The sign and the size of the difference data I from “000000011” (decimal 3) are the difference data “00101” between the 5-bit demodulated symbol number data “00101” after data compression and the 5-bit reference symbol number data “00011”. 0001
The code “0” (positive) and the size “0010” (10
It is represented by 2) in hexadecimal.

Whether or not the case (a) is satisfied is determined by determining whether or not the following conditional expression is satisfied.

[0145]

(Equation 1) Here, XNOR indicates an operation symbol of exclusive NOR, and AND indicates an operation symbol of AND. In this case, if the conditional expression (1) is satisfied, it is determined that the case of (a) is satisfied.

(B) Demodulated symbol number data A [10]
To A [0] are reference symbol number data S [10] to S
[0] and demodulated symbol number data A
Upper 8-bit data A [10] of [10] to A [0]
To A [3] and reference symbol number data S [10] to S
When upper 8 bits of data S [10] to S [3] of [0] are not equal In this case, 11-bit demodulated symbol number data A [10] to A [0] before data compression and 11-bit Difference data I from reference symbol number data S [10] to S [0]
Is set to “0” (positive). Also, the size I
M is set to the size of the difference data between the 5-bit demodulated symbol number data AOR to A [0] after data compression and the 5-bit reference symbol number data SOR to S [0].

For example, the 11-bit demodulated symbol number data “000000001001” (10
25) and 11-bit reference symbol number data "0
The sign of the difference data I from "0000010110" (22 in decimal) is set to "0" (positive). Size IM
Is set to the size “0011” (3 in decimal) of the difference data “00011” between the 5-bit demodulated symbol number data “11001” after data compression and the 5-bit reference symbol number data “10110”. .

The 11-bit demodulated symbol number data “0000000010001” (17 in decimal) before data compression and the 11-bit reference symbol number data “00”
00000001110 ”(14 in decimal)
Is set to “0” (positive). The size IM is
5-bit demodulated symbol number data “1” after data compression
0001 ”and 5-bit reference symbol number data“ 01 ”
110 and the size “001” of the difference data “00011”
1 "(3 in decimal).

Further, 11-bit demodulated symbol number data "00000110001" (49 in decimal) before data compression and 11-bit reference symbol number data "00"
The sign of the difference data I from "00011110" (46 in decimal) is set to "0" (positive). The size IM is a 5-bit demodulated symbol number data “10” after data compression.
001 ”and 5-bit reference symbol number data“ 111 ”
The size “001” of the difference data “10011” from “10”
1 "(3 in decimal).

Whether or not the case (b) is satisfied is determined by determining whether or not the following conditional expression is satisfied.

[0151]

(Equation 2) In this case, if conditional expression (2) is satisfied, it is determined that the case of (b) is satisfied.

(C) Demodulated symbol number data A [10]
To A [0] are reference symbol number data S [10] to S
[0] and demodulated symbol number data A
Upper 8-bit data A [10] of [10] to A [0]
To A [3] and reference symbol number data S [10] to S
When upper 8 bits of data S [10] to S [3] of [0] are not equal In this case, 11-bit demodulated symbol number data A [10] to A [0] before data compression and 11-bit Difference data I from reference symbol number data S [10] to S [0]
Is set to "1" (negative). Size IM
Is set to the size of the difference data between the 5-bit demodulated symbol number data AOR to A [0] after data compression and the 5-bit reference symbol number data SOR to S [0].

For example, 11-bit demodulated symbol number data “00000010110” (10
25) and 11-bit reference symbol number data "0
The sign IS of the difference data I from "000001001" (decimal 22) is set to "1" (negative). Size I
M is set to the size “1101” (3 in decimal) of the difference data “11101” between the 5-bit demodulated symbol number data “10110” after data compression and the 5-bit reference symbol number data “11001”. You.

The 11-bit demodulated symbol number data “00000001110” (14 in decimal) before data compression and the 11-bit reference symbol number data “00”
000000011 ”(17 in decimal)
Is set to "1" (negative). Also, the size IM is the size “1101” of the difference data “11101” between the 5-bit demodulated symbol number data “01110” after data compression and the 5-bit reference symbol number data “10001” (3 decimals). ).

Further, 11-bit demodulated symbol number data “0000011110” (46 in decimal) before data compression and 11-bit reference symbol number data “00”
The sign of the difference data I of “00110001” (49 in decimal) is set to “1” (negative). Also, the size IM
Is set to the size “1101” (3 in decimal) of the difference data “01101” between the 5-bit demodulated symbol number data “11110” after data compression and the 5-bit reference symbol number data “10001”. .

Whether or not the case (c) holds is determined by determining whether or not the following conditional expression (3) holds.

[0157]

(Equation 3) In this case, if conditional expression (3) is satisfied, it is determined that the case of (c) is satisfied.

[Operation of Phase Control Unit 17 (n)] The operation of the above configuration will be described.

The 11-bit demodulated symbol number data A [10] to A [0] output from demodulation section 16 (n) are
The demodulated symbol number is supplied to the compression unit 81 and the difference calculation unit 83. The 11-bit demodulated symbol number data A [10] to A [0] supplied to the demodulated symbol number compression section 81 are:
It is converted into 5-bit demodulated symbol number data AOR to A [0]. This 5-bit demodulated symbol number data A
OR to A [0] are supplied to the difference calculation unit 83.

Similarly, 11-bit reference symbol number data S [10] -S output from reference phase generation section 14
[0] is the reference symbol number compression unit 82 and the difference calculation unit 83
Supplied to 11-bit reference symbol number data S [10] to S supplied to reference symbol number compression section 82
[0] is the 5-bit reference symbol number data SOR ~
Converted to S [0]. The 5-bit reference symbol number data SOR to S [0] are supplied to the difference calculation unit 83.

The difference calculation unit 83 calculates the above three equations (1)
Using (3), it is determined whether (a) to (c) hold.

As a result of this determination, if (a) is satisfied, the difference calculation unit 83 calculates the 5-bit demodulated symbol number data AOR to A [0] and the 5-bit reference symbol number data SOR to S [0]. Is obtained, and this difference data is set as difference data I.

If (b) holds, the difference calculation unit 83 sets the code IS of the difference data I to “0” (positive) and sets the size IM to 5 bits of demodulated symbol number data A.
OR ~ A [0] and 5-bit reference symbol number data S
It is set to the size of the difference data from OR to S [0].

Further, when (c) holds, the difference calculation unit 83 sets the code IS of the difference data I to “1” (negative) and sets the size IM to 5 bits of demodulated symbol number data A.
OR ~ A [0] and 5-bit reference symbol number data S
It is set to the size of the difference data from OR to S [0].

[Effects] According to this embodiment described in detail above, the same effects as in the third embodiment can be obtained, and further, the following effects can be obtained.

(1) First, according to this embodiment, 1
1-bit demodulated symbol number data A [10] to A
[0] and 11-bit reference symbol number data S [1
0] to S [0] are obtained after compressing them to 5 bits. Therefore, according to the third embodiment, the scale of the circuit for obtaining the difference data I is reduced. Can be reduced.

(2) According to the present embodiment, 1
1-bit demodulated symbol number data A [10] to A
[0] and 11-bit reference symbol number data S [1
0] to S [0], the relationship is obtained by dividing the above three cases (a), (b), and (c). You can ask.

[Other Embodiments] The four embodiments of the present invention have been described above in detail.
The present invention is not limited to the embodiment described above.

(1) For example, in the above embodiment, the case where the phase of the delayed wave Dn is controlled based on the demodulated symbol number and the reference chip number has been described.

However, the present invention is based on
The control may be performed by a phase control configuration as described in Japanese Patent Application No. 7-141719 filed on Jun. 8, 1995.

(2) In the third embodiment, the case where the reference symbol number data RS is generated, the case where the average value of the demodulated symbol numbers of the delayed waves D1 and D2 at the start of demodulation is generated as an initial value. explained. This means that when there are three or more delayed waves to be combined, the average value of the demodulated symbol numbers of the three or more delayed waves is used.

However, according to the present invention, the delay wave to be synthesized is 3
If there are three or more, the average value of the largest number and the smallest number among the three or more demodulated symbol numbers may be used as the initial value.

According to such a configuration, when there are many delayed waves to be combined, the configuration for calculating the initial value can be simplified.

(3) A value other than the average of the demodulated symbol numbers may be used as the initial value. For example, 0 may be used. In this case, the numbers of the seven registers of the shift register 71 shown in FIGS. 9 and 10 are changed to "3, 2, 1, 0, -1, -2, -3".
May be changed to “6, 5, 4, 3, 2, 1, 0”.

(4) In addition, it goes without saying that the present invention can be variously modified without departing from the scope of the invention.

[0176]

As described in detail above, according to the present invention,
The code length of the spread code is set to N times the correlation length, a number is assigned to each chip of the spread code, and data indicating a chip number serving as a reference when detecting the phases of a plurality of delayed waves is generated. While changing the phase of the same spreading code as the spreading code for spreading modulation, the received data is despread by this spreading code, and the phase of the delayed wave is detected using the chip number, and the data indicating the detected phase is detected. The relative phase between the delayed wave and the reference chip number data is obtained by calculating the difference between the delay wave and the reference chip number data, and the absolute phase of the delayed wave is obtained by adding the data indicating the relative phase and the reference chip number data. Is obtained, the current phase of the delayed wave can be accurately detected even when the time spent for detecting the delayed wave becomes longer. As a result, when demodulating a delayed wave, even if the time spent for detecting the delayed wave becomes longer, it can be accurately demodulated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a rake receiving device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of an example of a spreading code used in the first embodiment.

FIG. 3 is a diagram illustrating an example of a chip number assignment method according to the first embodiment;

FIG. 4 is a block diagram illustrating a configuration of a reference phase generator according to the first embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a demodulation unit according to the first embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a phase control unit according to the first embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a demodulation unit according to a second embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a reference phase generator according to a third embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a phase control unit according to a third embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a phase control unit according to a fourth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Reception data input terminal 12 (1) -12 (3) ... Chip clock input terminal 13 ... Symbol clock input terminal 14 ... Reference phase generation part 15 ... Phase detection part 16 (1), 16 (2) ... Demodulation part 17 (1), 17 (2) phase control section 18 synthesis section 19 demodulated data output terminal 21 reference chip counter 22 reference symbol counter 31 addition section 32 seed generation section 33 spreading code generation section 34 delay Wave demodulation unit 35 demodulation symbol number calculation unit 41 data storage unit 42 data writing unit 43 data reading unit 51 spreading code storage unit 52 address generation unit 61 average value calculation unit 71 shift register 72 subtraction unit 73 data input unit 81 demodulation symbol number compression unit 82 reference symbol number compression unit 83 difference calculation unit

Continuation of the front page (56) References JP-A-8-335891 (JP, A) JP-A-8-186521 (JP, A) JP-A-9-107310 (JP, A) JP-A-7-240734 (JP) , A) JP-A-9-247044 (JP, A) Takashi Inoue et al., High Fading Wideband DS / CDMA System Using Cyclic Spreading and Oversymbol RAKE Reception, IEICE Technical Report RCS 96-75, Japan , P. 63-68 (58) Field surveyed (Int.Cl. ⁷ , DB name) H04J 13/00-13/06 H04B 1/96-1/713

Claims (12)

(57) [Claims] 1. An apparatus for receiving data spread and modulated by a spreading code having a code length N (N is an integer of 2 or more) times a correlation length and a number assigned to each chip, Reference chip number generating means for generating data indicating a chip number serving as a reference when detecting the phases of a plurality of delay waves included in received data, and changing the phase of the same spreading code as the spreading code for spreading modulation. While the received data is despread by the spreading code, phase detection means for detecting the phases of a plurality of delayed waves included in the received data using the chip number, and Difference calculating means for calculating a difference between data indicating the phases of the plurality of delayed waves and the reference chip number data generated by the reference chip number generating means; Adding means for adding data indicating the reference chip number and the reference chip number data generated by the reference chip number generating means, and a spreading code identical to the spreading code for spreading modulation, which is indicated by an added output of the adding means. By despreading the received data with a spreading code having a phase,
Demodulating means for demodulating a plurality of delayed waves included in the received data; and controlling the phase of the demodulated data of the plurality of delayed waves outputted from the demodulating means to thereby obtain the phase of the demodulated data of the plurality of delayed waves. A rake receiving device comprising: phase control means for adjusting the phase; and synthesizing means for synthesizing demodulated data of the plurality of delayed waves, the phases of which are controlled by the phase control means. 2. The method according to claim 1, wherein the phase control unit divides a number assigned to each chip of a plurality of spreading codes used for demodulation by the demodulation unit by the correlation length,
Demodulation symbol number generation means for generating data indicating the number of a symbol being demodulated for each delay wave; and generating data serving as a reference when indicating the symbol number and aligning the phases of the demodulation data of the plurality of delay waves. A reference symbol number generating unit that controls a phase of the demodulated data of the plurality of delayed waves based on the demodulated symbol number data and the reference symbol number data, thereby obtaining a phase of the demodulated data of the plurality of delayed waves. 2. The rake receiving apparatus according to claim 1, further comprising control means for adjusting the number of the rakes. 3. The control means is provided for each delay wave, a plurality of data storage means having a plurality of storage units corresponding to each symbol number, and a plurality of data storage means provided for each delay wave, A plurality of data writing means for writing the demodulated data in a storage unit corresponding to the symbol number indicated by the corresponding demodulated symbol number data in the corresponding data storage means; and a plurality of data writing means provided for each delay wave and writing the data in the corresponding data storage means 3. A rake receiving apparatus according to claim 2, further comprising data reading means for reading out the demodulated data from a storage unit corresponding to a reference symbol number indicated by the reference symbol number data. 4. The control means is provided for each delay wave, a plurality of difference calculation means for calculating a difference between corresponding demodulated symbol number data and the reference symbol number data, and provided for each delay wave. 3. The rake receiving apparatus according to claim 2, further comprising a plurality of delay units for delaying demodulated data of the corresponding delayed wave by a time corresponding to the difference obtained by the corresponding difference calculating unit. 5. The demodulation symbol number compression means for compressing the corresponding demodulation symbol number data by a predetermined method, the reference symbol number for compressing the reference symbol number data by a predetermined method. Compression means, based on the demodulated symbol number data and the reference symbol number data before data compression and the demodulated symbol number data and the reference symbol data after data compression, 5. The rake receiving apparatus according to claim 4, further comprising a calculating means for calculating a difference. 6. The demodulation symbol number compression means converts data of upper M bits (M is an integer of 2 or more) into 1-bit data by a logical sum operation, thereby compressing the demodulation symbol number data. The reference symbol number compression means is configured to compress the reference symbol number data by converting high-order M-bit data into 1-bit data by a logical sum operation. The rake receiving device according to claim 5, wherein 7. When the demodulated symbol number data before data compression and the data of the upper (M + 1) bits of the reference symbol number data are equal to each other, the arithmetic means determines the sign and magnitude of the difference by using the demodulated symbol after data compression. When the sign and the magnitude of the difference between the number data and the reference symbol number data are set, and the data of the upper (M + 1) bits are not equal and the demodulated symbol number data before data compression is larger than the reference symbol number data, the difference is set. Is set to a positive value, and the size is set to the magnitude of the difference between the demodulated symbol number data after data compression and the reference symbol number data. The upper (M + 1) -bit data is not equal, and demodulation before data compression is performed. If the symbol number data is smaller than the reference symbol number data, the sign of the difference is set to negative, and the magnitude is set to the demodulated symbol after data compression. 6. The rake receiving apparatus according to claim 5, wherein the rake receiving apparatus is configured to set the difference between the vol number data and the reference symbol number data. 8. A data shifter having a plurality of shift stages, capable of inputting data from any of the shift stages, and shifting input data in synchronization with a symbol clock having the same frequency as a symbol frequency. Means, and the demodulated data of the corresponding delayed wave is shifted to a shift stage separated from the predetermined shift stage by the number of stages corresponding to the difference obtained by the corresponding difference calculating unit from among the plurality of shift stages of the data shift unit. 5. The rake receiving device according to claim 4, further comprising data input means for inputting. 9. The reference symbol number generating means includes: an average value calculating means for obtaining an average value of demodulated symbol number data of the plurality of delayed waves at the start of demodulation; and an average value obtained by the average value calculating means. 9. The rake receiving apparatus according to claim 8, further comprising: a number generating means for generating said reference symbol number data as an initial value. 10. The reference symbol number generation means, the demodulation symbol number data of the plurality of delay waves at the start of demodulation, average value calculation means for calculating an average value of the largest data and the smallest data, 9. The rake receiving apparatus according to claim 8, further comprising: a number generation unit configured to generate the reference symbol number data using an average value obtained by the average value calculation unit as an initial value. 11. A seed generating means provided for each delay, and for generating a seed for designating a phase of a spreading code for demodulating the delayed wave based on a detected phase of the corresponding delayed wave. And a plurality of spreading code generation means provided for each delay wave and using a shift register and an exclusive OR circuit to generate a spreading code having a phase specified by a seed generated by the corresponding seed generation means. And a delay wave demodulation means provided for each delay wave and demodulating the corresponding delay wave by despreading the received data with the spreading code generated by the corresponding spreading code generation means. The rake receiving device according to claim 1, wherein 12. The demodulation means is provided for each delay wave, a plurality of spread code storage means for storing waveform data of each chip of the spread code, and provided for each delay wave, Data reading means for reading out the waveform data from the spreading code storage means based on the detected phase of the received signal; and despreading of the received data by the spreading code read from the corresponding spreading code storage means provided for each delay wave. 2. The rake receiving apparatus according to claim 1, further comprising: a delay wave demodulation unit for demodulating a corresponding delay wave.