JP3244098B2 - Motor speed control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an office automation (OA) such as a printer or a PPC (plain paper copier).
The present invention relates to a motor speed control device used in equipment.

[0002]

2. Description of the Related Art In recent years, OA equipment such as printers and PPCs have been demanded to have higher performance such as higher speed, higher printing quality, and lower noise. Therefore, high performance such as high speed, high controllability, low vibration and low noise is required for the motors mounted on these devices.

[0003] Among these high performances, if an attempt is made to attain a high controllability, for example, the RE which means the reference speed of the motor is obtained from the oscillation signal of the crystal oscillator having an extremely stable frequency.
A method is known in which an F signal is obtained, the REF signal is compared with an FG signal indicating the speed of the motor, and the motor speed is controlled by changing the motor torque so that the frequencies match each other. I have.

[0004] As a method of obtaining the FG signal,
There is known a method in which an FG pattern is provided on a motor, and the FG pattern is obtained by an AC signal induced by a linkage magnetic flux from an FG magnet provided on a rotor of the motor. This is a method in which a high-precision FG signal can be obtained by providing a large number of magnetic poles of a magnet provided on a rotor, and is often used in a flat brushless motor in which a rotor and a motor coil face each other on a plane. .

However, in the above method, it is sometimes difficult to provide an FG pattern when the motor shape is different. Therefore, it is necessary to obtain an FG signal from a Hall element, which is a position detector of the rotor of the motor, and use it for speed control of the motor.

As described above, it is necessary for the motor speed control device to select an FG signal most suitable for the motor from a plurality of FG signals and use it for speed control. As such a speed control device, there is a speed control device having a configuration as shown in FIG.

In FIG. 3, reference numeral 1 denotes a motor provided at an output terminal of the motor driving means 2; 3 denotes a speed control means whose output terminal is connected to an input terminal of the motor driving means 2; The oscillator 44 provided at the terminal is a frequency dividing means whose input terminal is connected to the output terminal of the oscillation circuit 5 and the output terminal is connected to the first input terminal of the speed control means 3. The first, second, third and fourth input terminals are FG1, FG2, FG3 and SELECT input terminals 10, 1 respectively.
Selection means 1, 12, and 13 having an output terminal connected to a second input terminal of the speed control means 3.

The operation of the conventional motor speed control device configured as described above will be described.

By providing the oscillator 6 in the oscillation circuit 5, the oscillation circuit 5 performs a high-frequency (1 to 10 MHz) oscillation operation. The oscillation frequency is a constant value specific to the oscillator. The high frequency signal generated by the oscillation circuit 5 is input to the frequency dividing means 44. The frequency dividing means 44 divides the input high-frequency signal according to a preset dividing ratio and outputs a low-frequency (several hundred to several KHz) REF signal, and a first input terminal of the speed control means 3. To enter.

Next, the selecting means 7 selects three types of F, FG1, FG2 and FG3 in accordance with the input signal of the SELECT input terminal 13.
One of the G signals is selected and the second
Of the selected FG signal.

The speed control means 3 sends a torque command signal V to the motor drive means 2 so that the frequency of the FG signal having a frequency proportional to the rotation speed of the motor 1 matches the frequency of the REF signal which is the speed reference of the motor 1. enter the _T, the motor drive unit 2 supplies power to the motor 1 so that the torque based on the magnitude of the torque command signal V _T is generated in the motor 1.

Therefore, by appropriately selecting the natural frequency of the oscillator 6, the motor 1 can be controlled at a desired constant speed with high accuracy.

[0013]

However, in the above-mentioned conventional configuration, when the selection of the FG signal is changed without changing the desired speed of the motor 1, the speed control means 3 is naturally used.
The frequency of the FG signal supplied to the
The REF signal serving as the reference speed of the motor 1 must also be changed.
Has to be replaced.

A typical crystal oscillator is a crystal oscillator, which has a feature that an extremely stable oscillation frequency can be obtained, but has a disadvantage that the oscillator itself is expensive.
Due to the above-mentioned inconvenience, it is necessary to prepare many types of expensive oscillators.

The present invention solves the above-mentioned conventional problem. Even when the selection of the FG signal is changed without changing the desired speed of the motor, the speed of the motor does not need to be replaced by an expensive oscillator. It is an object to provide a control device.

[0016]

In order to achieve the above object, a motor speed control device according to the present invention comprises a frequency dividing means having a first dividing means.
And a second frequency dividing circuit, so that a plurality of frequency dividing ratios of the second frequency dividing circuit can be selected in advance, and the frequency dividing ratio is set to a plurality of frequencies having a frequency proportional to the speed of the motor. The frequency ratio of the FG signals is made equal to each other, and the frequency dividing ratio of the second frequency dividing circuit is set to a value equal to the frequency ratio of the FG signal selected based on an external command signal.

[0017]

According to the above construction, the frequency dividing ratio of the frequency dividing means is made equal to the frequency ratio of the plurality of FG signals, and the frequency dividing ratio is selected.
By setting a value equal to the ratio of the G signal,
The frequency of the REF signal, which indicates the reference speed of the motor, will be changed according to the same value as the selected frequency ratio of the FG signal without changing the oscillator. Also, the motor can be controlled at a desired constant speed before the FG signal is changed.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. Members corresponding to the members described in the configuration of the conventional example of FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. Reference numeral 4 denotes frequency dividing means, which is composed of a first frequency dividing circuit 9 and a second frequency dividing circuit 8. ing.
An input terminal of the first frequency dividing circuit 9 is connected to an output terminal of the oscillation circuit 5 to form an input terminal of the frequency dividing means 4, and an output terminal of the first frequency dividing circuit 9 is connected to the second frequency dividing circuit 8. Is connected to the first input terminal of An output terminal of the second frequency dividing circuit 8 is connected to a first input terminal of the speed control means 3 and forms an output terminal of the frequency dividing means 4. The dividing ratio of the second dividing circuit 8 is 1,
It is configured such that three values of 1 / N and 1 / M can be set.

Reference numeral 7 denotes a selection means. The first, second, and third input terminals have a frequency ratio of 1: 1 / N: 1 / M.
The input terminals 10, 11, and 12 of the FG1, FG2, and FG3 signals (N and M are integers) are provided, and the fourth input terminal is the input terminal 13 of the SELECT signal. An output terminal of the selection means 7 is connected to a second input terminal of the speed control means 3. The SELECT signal input terminal 13 is also connected to the second input terminal of the second frequency divider 8.

The operation of the first embodiment configured as described above will be described.

The selecting means 7 has a frequency ratio of 1: 1 / N: 1 / M according to the input signal of the SELECT signal input terminal 13.
One of the three types of FG signals, FG1, FG2, and FG3, is selected, and the selected FG signal is input to the second input terminal of the speed control means 3. At the same time, the SELECT signal is input to the second input terminal of the second frequency divider 8 so that the same frequency division ratio as the frequency ratio of the selected FG signal is set in the second frequency divider 8. You. That is, FG
When 1 is selected, the division ratio 1 is selected, when FG2 is selected, the division ratio 1 / N is selected, and when FG3 is selected, the division ratio 1 / M is selected. .

The high frequency signal generated by the oscillation circuit 5 is input to a first frequency dividing circuit 9 of the frequency dividing means 4. The first frequency dividing circuit 9 divides the inputted high frequency signal according to a preset dividing ratio and outputs a signal of a low frequency (several hundreds to several KHz). Output to the first input terminal. The input signal from the second frequency dividing circuit 8 is further divided by a frequency dividing ratio according to the SELECT signal to generate a REF signal, which is input to a first input terminal of the speed control means 3.

The speed control means 3 sends a torque command signal V _T to the motor drive means 2 so that the frequency of the FG signal having a frequency proportional to the rotation speed of the motor 1 matches the REF signal at which the reference speed of the motor 1 matches. type, the motor drive unit 2 supplies power to the motor 1 so that the torque based on the magnitude of the torque command signal V _T is generated in the motor 1.

Therefore, by properly selecting the natural frequency of the oscillator 6, the motor 1 can be controlled at a desired speed with high accuracy.
By applying the signal, even if the FG signal to be selected is changed, the frequency division ratio of the second frequency dividing circuit 8 is simultaneously set to the same value as the frequency ratio of the FG signal before and after the change.
The frequency of the REF signal, which indicates the reference speed of the motor 1 supplied to the speed control means 3, is also changed in accordance with the selected frequency ratio of the FG signal. It is possible to control with high speed and high accuracy.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention. Reference numeral 101 denotes three-phase motor coils 101a and 101.
A brushless motor having b and 101c, which is provided at an output terminal of the motor driving means 2.

Reference numerals 17, 18, and 19 denote Hall elements as first, second, and third position sensors.
It is connected to 16 first, second and third input terminals. The first, second, and third output terminals of the hall amplifier 16 are connected to the first, second, and third input terminals of the commutation control unit 15, respectively. The first to sixth output terminals of the commutation control means 15 are connected to the first to sixth input terminals of the output unit 14. The output unit 14 includes source-side output transistors Q1, Q
3, Q5 and sink-side output transistors Q2, Q4
Q6, each transistor Q1 and Q
2, Q3 and Q4, Q5 and Q6 are connected in series, and the connection point forms an output terminal of the output unit 14. The output unit 1
4, the commutation control means 15 and the Hall amplifier section 16 constitute the motor driving means 2, and the output terminal of the output section 14 forms the output terminal of the motor driving means 2.

Reference numeral 3 denotes a speed control means, whose output terminal is connected to the fourth input terminal of the commutation control means 15.

Reference numeral 20 denotes a hole FG generating means, which comprises a waveform shaping section 21 and a 3-hole FG generating circuit 22.
The waveform shaping section 21 has first, second, and third input terminals commonly connected to the first, second, and third input terminals of the hall amplifier section 16, respectively. Are connected to the first, second, and third input terminals of the 3-hole FG generation circuit 22, respectively. The first output terminal of the waveform shaping section 21 and the output terminal of the 3-hole FG signal generation circuit 22 form first and second output terminals of the hole FG generation means 20, respectively.

Reference numeral 26 denotes a pattern FG generating means, which comprises an FG amplifier (AMP.) 27 and an FG comparator (COMP.) 28. An FG pattern 31 has one end grounded and the other end connected to one side of the capacitor 32. The other end of the capacitor 32 is commonly connected to one of the switch 29 (SW1) and the switch 30 (SW2) and the input terminal of the discriminating means 25, and the FG.AMP. Connected to 27 input terminals. FG AMP. 27 output terminals are FG / C
OMP. Connected to 28 input terminals. FG COMP. Two
The output terminal 8 forms the output terminal of the pattern FG generating means 26.

Reference numeral 7 denotes a selection means, which comprises a first selection circuit 23 and a second selection circuit 24. The first and second input terminals of the first selection circuit 23 are connected to the first and second output terminals of the Hall FG generating means 20, and form an FG3 signal input terminal and an FG2 signal input terminal. An output terminal of the first selection circuit 23 is connected to a first input terminal of the second selection circuit 24. A second input terminal of the second selection circuit 24 is connected to an output terminal of the pattern
One signal input terminal. An output terminal of the second selection circuit 24 forms an FG signal output terminal of the selection means 7 and is connected to a second input terminal of the speed control means 3. The first and second output terminals of the determination circuit 25 are connected to the third input terminals of the first and second selection circuits 23 and 24, respectively.

Reference numeral 6 denotes an oscillator, which is provided at an input terminal of the oscillation circuit 5. Reference numeral 4 denotes a frequency dividing means, which includes a first frequency dividing circuit 9 and a second frequency dividing circuit 8. An input terminal of the first frequency divider 9 is connected to an output terminal of the oscillation circuit 5 to form an input terminal of the frequency divider 4, and an output terminal of the first frequency divider 9 is connected to a first input terminal of the second frequency divider 8. Connected. An output terminal of the second frequency dividing circuit 8 forms an output terminal of the REF signal, and is connected to a first input terminal of the speed control means 3.
The second and third input terminals of the second frequency dividing circuit 8 are
25 first and second output terminals.

The operation of the second embodiment configured as described above will be described.

The waveform shaping section 21 converts a sinusoidal signal generated in the first, second, and third Hall elements 17, 18, and 19 into a rectangular wave. The obtained signal is input to the first input terminal of the first selection circuit 23 as an FG3 signal, and at the same time, is input to the first input terminal of the 3-hole FG generation circuit 22. The signals generated at the second and third output terminals of the waveform shaping section 21 are obtained from the second and third Hall elements 18 and 19, and the three-hole F
It is input to the second and third input terminals of the G generation circuit 22. 3
The output terminal of the hall FG generating circuit 22 has a three-hole FG obtained by synthesizing signals obtained from the three hall elements 17, 18, and 19.
A signal is output and input to the second input terminal of the first selection circuit 23 as an FG2 signal.

Next, the switch (SW1) 29 and the switch (S
W2) 30 is open, and the brushless motor 101 generated in the FG pattern 31 by the rotation of the rotor
An AC signal having a frequency proportional to the rotation speed is input to the pattern FG generating means 26 via the capacitor 32. FG · A which is a component of the pattern FG generating means 26
MP. The AC signal is amplified by 27, and FG / C
OMP. The waveform of the AC signal is shaped into a square wave by 28 and F
Generate the G1 signal. The FG1 signal is input to the second input terminal of the second selection circuit 24 of the selection means 7.

The FG1, FG2, and FG3 signals are signals whose frequency ratios are preset to, for example, 1: 1/3: 1/6 under the condition that the rotation speed of the brushless motor 101 is constant.

On the other hand, the determining means 25 detects that the input terminal of the pattern FG generating means 26 is open, and
The FG1 signal acts so as to be transmitted to the speed control means 3. At the same time, it acts on the second frequency dividing circuit 8 to set the frequency dividing ratio to one of three values of 1, 1/3 and 1/6.

The high frequency signal generated by the oscillation circuit 5 is input to the first frequency dividing circuit 9 of the frequency dividing means 4. The first frequency dividing circuit 9 divides the inputted high frequency signal according to a preset dividing ratio and outputs a signal of a low frequency (several hundreds to several KHz). Input to the first input terminal. The input signal is the dividing ratio of the second dividing circuit 8 set previously,
The frequency is further divided to generate a REF signal.
To the first input terminal.

The speed control means 3 includes a brushless motor 101
The fourth input terminal of the commutation control means 15 of the component of the motor driving means 2 so that the frequency of the FG1 signal having a frequency proportional to the rotation speed of the brushless motor 101 matches the frequency of the REF signal serving as the reference speed of the brushless motor 101. enter the torque command signal V _T, the motor drive unit 2 supplies power to the brushless motor 101 so that the torque based on the magnitude of the torque command signal V _T generated brushless motor 101.

Thus, by appropriately selecting the natural frequency of the oscillator 6, the brushless motor 101 can be controlled at a desired constant value with high accuracy.

Next, when the switch (SW1) 29 is closed and the switch (SW2) 30 is opened, the discriminating means 25 acts on the second frequency dividing circuit 8 to set the frequency dividing ratio to 1/3. .
At the same time, the first selecting circuit 23 selects the FG2 signal from the input FG3 and FG2 signals, outputs the FG2 signal to its output terminal, and outputs the FG2 signal to the first selecting circuit 24 of the second selecting circuit 24. Input terminal. In the second selection circuit 24, the FG signal input to the first input terminal is selected by the operation of the determination means 25 and output to the output terminal. As a result, the FG2 signal is output from the selection means 7 to the speed control means 3. Will be entered. Then, similarly to the case where the FG1 signal is selected by the speed control means 3, the brushless motor 101 is controlled with high accuracy at a desired constant value of speed.

Next, when the switch (SW2) 30 is closed and the switch (SW1) 29 is opened, the discriminating means 25 operates on the second frequency dividing circuit 8 to set the frequency dividing ratio to 1/6. .
At the same time, the first selecting circuit 23 selects the FG3 signal from the input FG3 and FG2 signals, and outputs the FG3 signal to its output terminal. Input terminal. In the second selection circuit 24, the FG signal input to the first input terminal is selected by the operation of the determination means 25 and output to the output terminal. As a result, the FG3 signal is output from the selection means 7 to the speed control means 3. Will be entered. Then, similarly to the case where the FG1 and FG2 signals are selected by the speed control means 3, the brushless motor 101 is controlled with high accuracy at a desired constant value of speed.

As described above, even when an arbitrary FG signal is selected from three FG signals having different frequencies from each other, the selected FG signal is selected.
Since the frequency division ratio equal to the frequency ratio of the G signal is set,
Since the REF signal equal to the change in the frequency of the selected FG signal is supplied to the speed control means 3, the speed of the brushless motor 101 can be changed without changing the natural frequency of the oscillator 6 even if the FG signal is changed. Control can be performed at the same desired speed as before the change of the FG signal.

In addition, since the discriminating means 25 detects the input level of the input terminal of the pattern FG generating means 26, there is an advantage that it is not necessary to provide a new input terminal for selecting the FG signal.

[0045]

As described above, according to the motor speed control apparatus of the present invention, as described in each claim, a motor capable of arbitrarily selecting one from a plurality of FG signals indicating the speed of the motor. In the speed control device according to
And a second frequency divider circuit, and a plurality of FG signals whose frequency division ratios can be selected so that a plurality of frequency division ratios of the second frequency divider circuit can be set in advance. REF signal equal to the frequency of the selected FG signal is supplied to the speed control means by setting the frequency division ratio equal to the frequency ratio of the FG signal selected based on an external command signal. Therefore, even if the FG signal is changed, the motor speed can be controlled at the same desired speed as before the change of the FG signal without changing the natural frequency of the expensive oscillator.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a motor speed control device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a motor speed control device in a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Motor, 2 ... Motor drive means, 3 ... Speed control means, 4, 44 ... Frequency dividing means, 5 ... Oscillation circuit, 6 ... Oscillator, 7 ... Selection means, 8 ... Second frequency dividing circuit, 9 ... First
, FG1 signal input terminal, 11 FG2
Signal input terminal, 12: FG3 signal input terminal, 13: SEL
ECT signal input terminal, 14: output unit, 15: commutation control means, 16: hall amplifier unit, 17: first Hall element,
18 ... second Hall element, 19 ... third Hall element,
20: Hall FG generating means, 21: Waveform shaping section, 22: 3
Hall FG generating circuit, 23: first selecting circuit, 24: second selecting circuit, 25: determining means, 26: pattern FG generating means, 27: FG / AMP. , 28… FG ・ COM
P. , 29 ... switch (SW1), 30 ... switch (SW1)
2), 31 ... FG pattern, 32 ... Capacitor, 101 ...
Brushless motor.

Continuation of the front page (72) Inventor Koichiro Ogino 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Tsutomu Shimazaki 2-5-2-5 Keihanhondori, Moriguchi-shi, Osaka (56) References JP-A-5-22980 (JP, A) JP-A-4-58779 (JP, A) JP-A-2-95190 (JP, A) (58) Fields investigated ( Int.Cl. ⁷ , DB name) H02P 6/16 H02P 5/00

Claims (4)

(57) [Claims] 1. A motor, motor driving means for supplying electric power to the motor to generate torque, and applying a torque command signal to the motor driving means to change the magnitude of the torque generated in the motor. Speed control means for controlling the speed of the motor, and a motor reference speed signal of a constant frequency obtained by frequency dividing by a frequency dividing means from a high frequency signal generated by an oscillation circuit provided with an oscillator, is selected in advance. A motor speed signal selected from a plurality of signals having a frequency proportional to the speed of the motor that can be compared by the speed control means, and the torque control signal is generated by the speed control means based on the comparison result. In the motor speed control device configured to generate the first frequency division frequency, the frequency division means divides the frequency of the input high-frequency signal according to a preset frequency division ratio. And a second frequency dividing circuit for receiving an output signal of the first frequency dividing circuit.
A plurality of frequency dividing ratios of the frequency dividing circuit can be selected in advance, and the frequency dividing ratio is set to be the same as the ratio between the frequencies of the plurality of selectable motor speed signals. A motor speed control device wherein a circumferential ratio can be set to a value equal to a ratio of a frequency of a motor speed signal selected based on an external command signal. 2. A method according to claim 1, wherein three signals having a frequency proportional to the speed of the motor and having a frequency ratio of 1: 1 / N: 1 / M (N and M are integers) are selected based on an external selection signal. Motor speed signal is selected, and at the same time, the frequency division ratio is set to 1,
3. A value of a frequency division ratio equal to a frequency ratio of a selected motor speed signal can be set in the second frequency divider circuit which can set three types of 1 / N and 1 / M. 2. The motor speed control device according to claim 1. 3. A brushless motor having a three-phase motor coil, and the motor coil is energized based on a position signal of a rotor of the brushless motor from three Hall elements provided in the brushless motor, and torque is applied to the motor coil. A motor driving means for generating the motor; and a speed control means for controlling the speed of the brushless motor by changing the magnitude of the torque generated in the brushless motor by giving a torque command signal to the motor driving means. A constant frequency motor speed signal obtained by frequency division by frequency dividing means from a high frequency signal generated by the provided oscillation circuit, and two types of Hall signals obtained from one or three of the Hall elements, or a brushless Motor speed signal selected from one of the pattern signals obtained from the speed pattern provided on the motor And the speed control means,
In the motor speed control device configured to generate the torque command signal by the speed control unit based on the comparison result, the frequency dividing unit divides the frequency according to a preset dividing ratio of the input high frequency signal. And a second frequency dividing circuit for receiving an output signal of the first frequency dividing circuit, and a plurality of frequency dividing ratios of the second frequency dividing circuit can be selected in advance. The frequency dividing ratio is made equal to the ratio of the frequencies of a plurality of motor speed signals having a frequency proportional to the speed of the brushless motor, and the frequency dividing ratio of the second frequency dividing circuit is set to an external command signal. A motor speed control device characterized in that it can be set to a value equal to the ratio of the frequency of the motor speed signal selected based on the motor speed signal. 4. A selection signal can be input from a speed pattern connection terminal, and has a frequency proportional to the speed of the brushless motor whose frequency ratio is 1: 1/3: 1/6 based on the input selection signal. An arbitrary motor speed signal is selected from the three signals of the hall signal and the pattern signal,
At the same time, the frequency division ratio of the motor speed signal in which the frequency division ratio of the second frequency division circuit is selected in the second frequency division circuit in which three types of frequency division ratios of 1, 1/3 and 1/6 can be selected in advance. 4. The motor speed control device according to claim 3, wherein the value can be set to a value equal to: