JP3242099B2 - Video camera unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to video camera units, and in particular to small and bright video camera units.

[0002]

[Prior art]

In recent years, ultra-small 1 / 3-inch solid-state imaging devices have been developed, and door scope TV cameras and the like using such devices have been tried. The wide-angle lens used for this purpose is required to have certain optical properties related to spherical aberration, astigmatism, distortion, chromatic aberration, sine condition, and the like. JP-A-48-64927). A solid-state imaging chip (IC chip) comprising a combination of a photodiode and a switch MOSFET is disclosed in, for example,
It is publicly known from Japanese Patent Publication No. 152382. In a television camera for surveillance or home use using the solid-state imaging chip, the optical lens is provided with an automatic aperture mechanism.

[0003]

[Problems to be solved by the invention]

The wide-angle lens has a large number of lenses and is not suitable for miniaturization. Further, the lens with the automatic iris mechanism requires relatively complicated mechanical parts, which causes the lens part of the television camera to be large and expensive. In addition, since the automatic drawing mechanism is composed of relatively complicated mechanical parts, there is a problem in reliability due to wear of the mechanical mechanism. Furthermore, the conventional video camera unit does not consider the storage of the lens and the solid-state imaging device, and is not suitable for miniaturization as a video camera unit. One object of the present invention is to provide a very small video camera unit.

[0004]

[Means for Solving the Problems]

Among the inventions disclosed in the present application, an outline of a typical one is a lens, a rectangular solid imaging device, a holder for housing the lens and the device, a substrate on which the device is provided, and a holder for the device. A first storage section for storing the lens provided therein; and a second storage section for storing the device provided in the holder, wherein the first storage section is provided outside the lens. A first inner wall having an inner diameter substantially equal to a diameter, wherein the second storage portion has a second inner wall formed to have substantially the same shape as a rectangular parallelepiped outer periphery of the device so as to store the device; And the holder is provided on the substrate. Further, according to the embodiment of the present invention, there is provided a video camera unit including a plurality of plastic lenses in which some lenses are formed as aspherical surfaces, and an imaging circuit capable of electrically varying sensitivity.

Since all lenses are made of plastic, these lenses can be easily molded by appropriate molding means such as injection molding.
Therefore, aspherical lenses that cannot be polished with glass lenses that require polishing can be easily manufactured. Even if the number of lenses is small, the problem of spherical aberration, astigmatism, and distortion can be reduced even if the number of lenses is small. Aberration, chromatic aberration, and sine conditions can be corrected, the number of lenses can be reduced, and miniaturization, weight reduction, and cost reduction can be achieved.

In addition, since the solid-state imaging circuit is electrically variable in sensitivity, it is possible to eliminate the need for a mechanical diaphragm mechanism as in the related art. Can be achieved. Especially for micro surveillance cameras, both technologies have become important technologies. Furthermore, the provision of the first cylindrical storage section for storing the lens and the second storage section for storing the device enables miniaturization.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION

FIGS. 1 to 4 and Table 1 show a wide-angle lens according to the present invention and a micro TV camera unit using the same. FIG. 1 is a cross-sectional view of the camera unit, and FIG. 2 is a plan view when the camera unit is viewed from below (the imaging device side).

In FIG. 1 and FIG. 2, reference numeral 1 denotes a cylindrical lens holder having an imaging device storage section 11 formed at a base, L ₁ , L ₂ ,
L ₃ and L ₄ are combination plastic lenses housed in the lens housing 12 of the lens holder, and 6 is a solid-state imaging device housed in the image sensor housing 11 corresponding to the lens.

The lens holder 1 is made of a material having a thermal expansion coefficient close to that of the plastic lenses L _{1 to} L ₄ , for example, a synthetic resin. The imaging device storage section 11 is formed in a rectangular parallelepiped shape so that the imaging device 6 can be easily fitted. Is inward flange 13 provided between the imaging device housing portion 11 and the lens housing portion 12, so it is aligned with the lens L ₁ ~L ₄ and the solid-state image device 6 by the inward flange 13 I have. A ring-shaped lid 14 is attached to the tip of the holder 1 so that the lens does not come off.

The plastic lenses L _{1 to} L ₄ are specifically designed with the constants shown in Appendix 1 and have the characteristics shown in FIG. The first lens L ₁ and the second lens L ₂ are concave lenses,
Third lens L ₃ and the fourth lens L ₃ forms the convex lens, the third front and rear both sides # 5 of lens L _3, # 6 and the fourth non-spherical front # 7 of lens L ₄ I have to. These lenses L _{1 to} L ₄ are provided with ribs 21, 31, 41, 51 which are fitted on the lens housing portion 12 at a peripheral edge thereof and keep a predetermined distance from each other. The solid-state imaging device 6 includes a substrate 62, a solid-state imaging semiconductor chip 64 mounted on the substrate 62, and external connection leads 61 attached to two sides of the base 62. The size of the chip 64 is set to, for example, 1/3 inch diagonal.

Next, the configuration of the lenses L _{1 to} L ₄ will be described with reference to FIGS. 3 and 4, Tables 1 and 2. Figure 3 is with a lens L ₁ ~L ₄ only view showing taken out, the lens surface numbers # 1 to # 8 from the left in the order shown in Figure 1. Table 1 shows an example of each lens surface # 1 to # 8 and each lens L ₁ ~L ₄ lens surface curvature radius γ corresponding to the lens surface distance d, the refractive index n and the design constants of the dispersion rate ν Where the radius γ and the distance d are expressed as a ratio to the EFL when the combined focal length EFL of the four lenses is set to 1.

In order to obtain predetermined characteristics with as few lenses as possible, it is preferable to adopt the following concept. The first lens L ₁ is a convex surface (# 1) meniscus positive lens toward the subject side, a second lens L ₂ is two-sided (# 3, # 4) concave negative lens, the third lens L ₃ duplex (# 5 , # 6) convex aspheric positive lens, a fourth lens L ₄ may be a convex surface of aspherical (# 7) to the positive meniscus lens toward the subject side.

Further, each constant of each lens and each lens surface is preferably selected so as to satisfy the following conditions. _{(1) f 1> 50f (} 2) 0.4f <d 2 <0.6f (3) 1.0f <r 3 where, f is the composite focal length of the lens L ₁ ~L _4, f ₁ is independently of the lens L ₁ focal length, d ₂ is the lens surface # distance between 2 and # 3, r ₃ is the radius of curvature of the lens surface # 3.

The reason for setting each condition is as follows. With respect to the condition (1), if f ₁ <50f, the negative distortion becomes large, and the field curvature is overcorrected. Also, coma aberration occurs. (2) coma inward fall below the lower limit value of d ₂ in the condition occurred, it becomes as if the upper limit is coma extrovert occur. Under the condition (3), when the value of r ₃ is smaller than the combined focal length f, the negative distortion increases as the value of r ₃ decreases toward the lower limit. For better aberration correction, in addition to the above conditions, adjustment can be easily made by making both surfaces of the third lens and surfaces of the fourth lens on the subject side aspherical as shown in Examples.

Each aberration in the present embodiment is as shown in FIG. 4. In FIG. 4, D, G, C, F, and E lines are D-line, G-line, C-line, and F-line, respectively.
-Line, E- line, spherical aberration curve, and chromatic aberration. M and S represent a meridional section and a sagittal section. As can be seen from these aberration curves, spherical aberration is well corrected, and the flare when opened is extremely small. Also, as seen from the Seidel coefficient (Table 3), the coma aberration is well corrected and the imaging performance is good. From its original purpose, distortion is
Great for correction. In addition, the lens surfaces # 5 to # 7 are formed as aspherical surfaces, and the radius of curvature r in Table 1 is annotated with * 1 to * 3. In the note.

FIG. 5 is a sectional view showing another embodiment of the solid-state imaging unit according to the present invention, and FIG. 6 is a plan view of the solid-state imaging unit viewed from below (lenses L _{1 to} L ₄ , lid 114, holder). 1 is omitted), and FIG. 5 is a cross-sectional view taken along the line VV in FIG. 114 is a lid assembled after accommodating the lens L ₁ ~L ₄ to the lens holder 1. Top end of lens holder 1
The height of 111 is formed higher than the edge portion of the lens L1, and a vertical portion 112 and a horizontal bottom portion 113 formed by notches are formed inside thereof. The height of the horizontal bottom portion 113 is set so that the height is substantially the same as the height of the edge portion of the lens L1. Thus, the upper end portions 111 to 113 of the lens holder 1 are
By forming the step portion, the lid 114 is easily fitted, and the bonding area between the lid 114 and the step portions 111 to 113 is increased, so that the bonding strength is increased. Further, since the bottom of the lid 114 contacts both the edge of the lens L1 and the portion 113 of the lens holder 1 via an adhesive or the like, a stable structure can be obtained.

A notch 110 is provided below the lid 114, and is used as an adhesive injection port. A projection 116 and a notch 115 are provided in a lower inner portion of the lens holder 1. Notch 115 is lens L4
It serves as a drain port for the air expelled when L1 to L1 are sequentially stacked, and prevents the lenses L4 to L1 from being lifted up by air. The protrusion 116 is effective for determining the distance between the lower lens L4 and the solid-state imaging chip 64. Further, the projection 116 also serves as a light shield for preventing the irregularly reflected light from entering the chip 64 and causing a flare phenomenon. S ₁ to S ₃ also provided the same purpose, a light shielding plate of gloss without black, it is formed in a donut shape.

The outer shape of the lens holder 1 is provided with a flat protrusion 117 at a lower portion, and the protrusion 117 can be used as a stop when the imaging unit is inserted into a hole provided in the camera body. . The inner inclined surface 150 of the lid 114 is formed in a step-like shape, and serves to diffuse unnecessary light hitting the portion to the outside. The solid-state imaging device 6 is fitted along the lower inner wall 125 of the holder 1. The guide at this time is a semicircular portion 126 protruding from the bottom surface of the holder 1, and the plastic substrate 62 of the device 6 is also formed with a semicircular concave portion according to its shape. In the plan view of FIG. 6, the bottom surface 118 of the holder 1 is hatched for convenience.

The alignment of the device 6 on the plane (X and Y directions) is performed by the inner walls 125 and 126 of the holder 1 in this way, but in the vertical direction (Z direction), the device 6 is positioned slightly deeper from the bottom surface of the holder 1. (FIG. 5) The distance of focusing between the lenses L1 to L4 and the surface of the imaging chip 64 can be determined by the steps 123 and 124. The step portions 123 and 124 are provided at two upper and lower portions in the plan view of FIG. 6, and a step is formed at the boundary lines 123 and 124. Since the steps 123 and 124 are in contact with the portion of the package 62 where the leads 61 do not exist,
The thickness and the bending of the lead 61 do not affect the accuracy of the distance between the lens and the imaging chip.

FIG. 7 is a sectional view showing another embodiment of the video camera unit according to the present invention. One of the feature points of the present embodiment different from the embodiment of FIGS. 1 and 5 is that the viewing angle is not a wide angle but a normal angle, and the number of lenses is reduced by one to a total of three. This is a point that reduction has been made possible. Lens L ₁₁ is double-sided (# 11, # 12) both convex positive lens,
Lens L ₁₂ is a concave surface facing # 13 on the subject, positive meniscus lens faces # 14 of the image pickup device side and aspherical, lens L
Reference numeral ₁₃ denotes a meniscus positive lens having an aspherical surface # 15 on the subject side. Table 4 shows the constants of the respective lens surfaces, Table 5 shows the constants of the aspherical lens surfaces, and Table 6 and FIG. 8 show various characteristics such as the Seidel aberration coefficient of each lens surface. The method of attachment is the same as that of the embodiment of FIG.

The optimum design constants of each lens and the men's surface are as follows. (4) f ₂ > 0 (5) r ₆ > 0 (6) 0.25 <d ₄ <0.35 (7) f ₃ > f ₂ > f ₁ > 0 (8) r ₄ > 0 According to such a configuration, As is clear from the aberration curves in FIG. 8, the correction of high-order spherical aberration and coma is good,
Flare when opened is extremely small. Further, as is clear from the Seidel coefficient shown in Table 6, the coma aberration is well corrected and the imaging performance is good.

Another feature of the present embodiment is that the imaging device 64 is electrostatically shielded from the outside by including carbon in the holder 100. The holder 100 is formed by mixing an appropriate amount of glass with a polycarbonate resin, further mixing carbon at a ratio of 10 to 200% of the whole, and performing transfer molding. This holder is AC grounded together with the leads 61 of the solid-state imaging device 64 via the chassis 150 of the main body when the camera unit is mounted on the main body. Note that, as a material to be mixed into the holder 100, silver particles may be used in addition to carbon.

The above-mentioned TV camera unit can be formed in a small size with a total length and a maximum diameter of 15 mm each. Further, the optical system enables wide-angle, normal, and telephoto, each of which has, for example, a focal length f = 4.8 mm, f = 7.3 mm, f = 15.0 mm, and a brightness F
= 1: 1.6-2.0, angle of view 80 ° -90 ° (wide angle), 45 ° -50 ° (standard), 20 ° -25 ° (telephoto), etc.

Meanwhile, the solid-state imaging chip 64 has an electrically variable sensitivity, and thus has a function of electrically adjusting the aperture or the shutter speed. It is very convenient. Hereinafter, the internal circuit of the chip 64 will be described with reference to FIG. 9, and the block configuration of the entire imaging (camera) circuit will be described with reference to FIG.

FIG. 9 shows a TSL (Transversal) to which the present invention is applied.
1 is a main part circuit diagram of an embodiment of a solid-state imaging device of a (Signal Line) type. Each circuit element in the figure is formed on a single semiconductor substrate such as single crystal silicon, although not particularly limited by a known semiconductor integrated circuit manufacturing technique. The main blocks in the figure are drawn according to the actual geometric arrangement. The signal terminals at the upper and lower ends of the figure are signal terminals, which are electrically connected to the leads 61 of the device 6 shown in FIGS. The number of leads 61 in FIGS. 1 and 2 is 16 for convenience.
Although the number is represented by individual pieces, it is sufficient to use 24 pieces (commonly referred to as a 24-pin DIL package) in accordance with the circuit in the chip shown in FIG.

The pixel array PD is exemplarily shown for four rows and two columns. However, in order to prevent the drawing from becoming complicated, circuit symbols are added only to the pixel cells of two rows out of the four rows. One pixel cell is
It comprises a series circuit of a photodiode D1 and a switch MOSFET Q1 whose gate is coupled to a vertical scanning line VL1, and a switch MOSFET Q2 whose gate is coupled to a horizontal scanning line HL1. The above photodiode D1 and switch MOSFET Q
Output nodes such as other similar pixel cells (D2, Q3, Q4) arranged in the same row (horizontal direction) as the pixel cell composed of 1, Q2 are:
In the figure, it is coupled to a horizontal signal line HS1 extending in the horizontal direction. Pixel cells similar to the above are similarly combined in other rows.

The horizontal scanning line HL 1 exemplarily shown is extended in the vertical direction in the figure, and is commonly coupled to gates of the switch MOSFETs Q 2 and Q 6 of pixel cells arranged in the same column. Pixel cells arranged in other columns are also coupled to the corresponding horizontal scanning lines HL2 and the like as described above.

In this embodiment, in order to add a substantial electronic automatic aperture function to the solid-state imaging device, in other words,
In order to vary the substantial accumulation time for the photodiode, switch MOSFETs Q8, Q9 and Q
26 and Q28 are provided. The switch MOSFETs Q8 and Q9 arranged on the right end couple the horizontal signal lines HS1 and HS2 to output lines VS extending in the vertical direction, respectively. This output line
VS is coupled to a terminal S, and a read signal is transmitted to an input of a preamplifier provided outside via the terminal S. Also, the switch MOSFET Q2 arranged on the left end side
6, Q28 couples the horizontal signal lines HS1 and HS2 to a dummy (reset) output line DVS extending in the vertical direction, respectively. The output line DVS is coupled to the terminal RV, although not particularly limited. This allows the dummy output line DV if necessary
The signal of S can be transmitted from the external terminal RV.

In this embodiment, although not particularly limited, switch MOSFETs Q 27, Q 29, etc., which are turned on by a reset signal supplied from the terminal RP during a horizontal retrace period, are provided on the horizontal signal lines HS 1 to HS 4 of each row. Provided. These MO
Depending on the ON state of the SFETs Q27, Q29, etc., a constant bias voltage (not shown) is applied from the external terminal RV to the horizontal signal lines HS1 to HS4 via the dummy output line DVS. The reason why the reset MOSFETs Q27, Q29, etc. are provided as described above is as follows. A semiconductor region such as a drain of a switch MOSFET coupled to the horizontal signal lines HS1 to HS4 may also be photosensitive, and a false signal (smearing, blooming) formed by such a parasitic photodiode.
Are stored in a horizontal signal line that is set to a floating state when not selected. Accordingly, in this embodiment, all the horizontal signal lines HS1 to HS4
Is reset to the predetermined bias voltage.
Thus, for the selected horizontal signal line, the pixel signal is always extracted from the state where the false signal is reset, so that the false signal included in the output pixel signal can be significantly reduced. The false signal (smear, blooming) is described in detail in, for example, Japanese Patent Application Laid-Open No. 57-17276.

The horizontal scanning lines HL1 and HL2 are supplied with a horizontal scanning signal formed by a horizontal shift register HSR. A scanning circuit for performing the vertical selection operation (horizontal scanning operation) in the pixel array PD is configured by the following circuits.

In this embodiment, the horizontal signal line HS1 of the pixel array PD
In addition, a pair of scanning circuits are provided corresponding to the provision of a pair of switch MOSFETs Q8, Q9, etc. and switch MOSFETs Q26, Q28, etc. at both ends of HS4 and the like.

In this embodiment, in order to be applicable to industrial use,
In addition to the interlace mode, selective two-line simultaneous scanning and scanning in a non-interlace mode are enabled. The following scanning circuit is provided on the right side of the pixel array PD.
The vertical shift register VSR forms output signals SV1, SV2 and the like used for reading. These output signals SV1, SV2
The vertical scanning lines VL1 to VL4 and the switch MOSFET Q are connected via the interlace gate circuit ITG and the driving circuit VD.
8, Q9, etc. are supplied to the gate.

The interlace gate circuit ITG performs a vertical selection operation (horizontal scanning operation) in the interlace mode. Therefore, in the first (odd) field, the vertical scanning lines VL1 to VL4 are adjacent to the vertical scanning lines VL1 to VL4. Selected simultaneously with the combination of VL1, VL2 and VL3. That is, the output signal SV1 of the vertical shift register VSR is output to the vertical scanning line VLI that selects the horizontal signal line HS1 by the switch MOSFET Q18 controlled by the odd field signal FA. At the same time, the output signal SV2 of the vertical shift register VSR is changed to the horizontal signal lines HS2 and HS3 by the switch MOSFETs Q20 and Q22 controlled by the signal FA.
Are simultaneously output to the vertical scanning lines VL2 and VL3.
Hereinafter, a selection signal for a pair of horizontal signal lines formed by a combination of the same order is formed.

In the second (even) field, the vertical scanning lines VL 1
To VL4, adjacent vertical scanning lines VL1, VL2 and VL3
Simultaneously selected in combination with VL4. That is, the switch MOSFET Q19 controlled by the even field signal FB
And Q21, the output signal SV1 of the vertical shift register VSR
Are the vertical scanning lines VL1 and VL2 that select the horizontal signal lines HS1 and HS2.
Is output to Similarly, switch MOSFETs Q23 and Q25 controlled by signal FB cause vertical shift register VSR
Is output to the vertical scanning lines VL3 and VL4 so as to simultaneously select the horizontal signal lines HS3 and HS4. Hereinafter, a selection signal for a pair of horizontal signal lines formed by a combination of the same order is formed. The above-described interlace gate circuit ITG and the next drive circuit DV realize a plurality of types of horizontal scanning operations as described below.

An output signal from the interlace gate circuit ITG corresponding to the one vertical scanning line VL1 is connected to the switch MOSFET Q14 and
Supplied to the gate of Q15. These switch MOSFETs Q14
And Q15 have a common drain electrode coupled to terminal V3. The switch MOSFET Q14 supplies a signal supplied from a terminal V3 to the vertical scanning line VL1. The switch MOSFET Q15 supplies a signal supplied from the terminal V3 to the gate of the switch MOSFET Q8 that couples the horizontal signal line HS1 to the output line VS. Further, in order to prevent the high level of the output signal from decreasing by the threshold voltage of the switch MOSFETs Q14 and Q15, there is no particular limitation.
A capacitor C1 is provided between the gate of ETQ14 and the output side (source side) of MOSFET Q15. Thus, when the output signal from the interlace gate circuit ITG is set to the high level, the potential of the terminal V3 is set to the low level, and the capacitor C1 is precharged. Thereafter, when the potential of the terminal V3 is set to a high level, the gate voltage of the MOSFETs Q14 and Q15 can be boosted by the bootstrap function of the capacitor C1.

An output signal from the interlace gate circuit ITG corresponding to the vertical scanning line VL2 adjacent to the vertical scanning line VL1 is supplied to the gates of the switch MOSFETs Q16 and Q17. The common drain electrode of these switch MOSFETs Q16 and Q17 is coupled to terminal V4. The switch MOSFET Q16 is
The signal supplied from the terminal V4 is supplied to the vertical scanning line VL2. The switch MOSFET Q17 supplies the signal supplied from the terminal V4 to the gate of the switch MOSFET Q9 that couples the horizontal signal line HS2 to the output line VS. Also, to prevent the high level of the output signal from being reduced by the threshold voltage of the switch MOSFETs Q16 and Q17, there is no particular limitation, but between the gate of the MOSFET Q16 and the output side (source side) of the MOSFET Q17. Is provided with a capacitor C2. Thus, the gate voltage of the MOSFETs Q16 and Q17 can be boosted by the bootstrap effect of the capacitor C2 by changing the potential of the terminal V4 at the same timing as described above. The terminal V3 is an odd-numbered vertical scanning line (horizontal signal line)
, And the terminal V4 is provided commonly to the even-numbered vertical scanning lines (horizontal signal lines).

As can be understood from the above, the combination of the alternate supply of the timing signals to the terminals V3 and V4 and the simultaneous selection operation of two rows by the interlace gate circuit ITG allows the interlace mode to be set. The read operation becomes possible. For example, at odd field FA, terminal V4
Is set to a low level, and a timing signal synchronized with the operation of the vertical shift register VSR is supplied to the terminal V3, thereby connecting the vertical scanning line (horizontal signal line) to VL1 (HS
1), VL3 (HS3) can be selected in this order. Also,
In the case of the even field FB, the terminal V3 is set to the low level, and a timing signal synchronized with the operation of the vertical shift register VSR is supplied to the terminal V4, so that the vertical scanning lines (horizontal signal lines) are VL2 (HS2), VL4 (HS4) can be selected in that order.

On the other hand, when the terminals V3 and V4 are simultaneously set to the high level as described above, two-row simultaneous scanning can be performed according to the output signal from the interlace gate circuit ITG. In this case, as described above, the combination of the two rows output for each of the two screens by the two field signals FA and FB is shifted up and down by one row, thereby shifting the spatial center of gravity up and down, in other words , An equivalent interlace mode is realized.

Further, for example, by setting only the FB signal to a high level, the horizontal shift register HSR is set to 2 at one vertical scanning timing.
By rotating the terminals V3 and V4 to the high level in synchronization therewith, the selection operation in the non-interlace mode can be realized in the order of VL1, VL2, VL3, and VL4. In this case, the horizontal shift register
It is desirable that the clock supplied to the HSR and the vertical shift register VSR be doubled in frequency. That is, the terminal
By making the frequency of the clock signal supplied from the terminals H1 and H2 and the terminals V1 and V2 to the horizontal shift register HSR and the vertical shift register VSR twice as high as one second,
60 images can be read out by the non-interlace method. Note that the terminals HIN and VIN are terminals for supplying input signals shifted by the shift registers HSR and VSR, respectively, and the shift operation is started when the input signals are supplied. For this reason, when the above two-row simultaneous reading, interlaced scanning, non-interlaced scanning, etc. are performed by a combination of the input signals supplied to the interlaced gate circuit ITG and the input terminals V3 and V4, the output signal is not When supplying the input signal to the shift register VSR, consideration must be given to the timing so that the vertical relationship of the directions is not reversed.

Further, between each of the vertical scanning lines VL1 and the gate of the corresponding switch MOSFET Q8 and the ground potential point of the circuit,
Reset MOSFETs Q10 and Q11 are provided. These reset MOSFETs Q10 and Q11 are connected to other vertical scan lines and switches.
In response to the clock signal supplied from the terminal V2 in common with the reset MOSFET provided corresponding to the MOSFET, the gate potential of the selected vertical scanning line and the switch MOSFET is rapidly pulled to a low level.

In this embodiment, a vertical shift register VSRE for sensitivity control, an interlace gate circuit ITGE, and a drive circuit DVE are provided in order to add a sensitivity variable function as described above. These sensitivity control circuits are not particularly limited, but are arranged on the left side of the pixel array PD. The vertical shift register VSRE, the interlace gate circuit ITG, and the drive circuit DVE are provided with the read vertical shift register VSR, the interlace gate circuit ITG, and the drive circuit.
It is composed of a circuit similar to DV. Timing signals similar to the above are supplied from terminals VIE to V4E and VINE, and FAE and ABE, respectively. In this case, in order to perform a shift operation at a timing synchronized with the vertical shift register VSR for reading and the vertical shift register VSRE for variable sensitivity, there is no particular limitation, but the terminals VIE, VI and V2E are connected.
The same clock signal is supplied to V2. Therefore,
The terminals V1E and V1 and the terminals V2E and V2 may be shared by an internal circuit. Unique terminal V1E as above
The reason why V2E and V2E are provided is to make this solid-state imaging device applicable to a television camera having a manual aperture or a conventional mechanical aperture function. When the sensitivity variable operation is not performed as described above, the terminals V1E and V2E are set to a low level such as the ground potential of the circuit, etc., so as to reduce wasteful power consumption of the vertical shift register VSRE. .

Next, a sensitivity control operation in the solid-state imaging device of this embodiment will be described. For the sake of simplicity, the following description will be made taking the vertical scanning operation in the non-interlace mode as an example. For example, a vertical shift register VSRE for sensitivity control, an interlace gate circuit ITGE, and a drive circuit DVE form a vertical shift register VSR for reading, an interlace gate circuit I.
The reading operation of the fourth row (vertical scanning line VL4, horizontal signal line HS4) is performed in parallel with the reading of the first row (vertical scanning line VL1, horizontal signal line HS1) by the TG and the driving circuit DV. Thus, in synchronization with the selection operation of the horizontal scanning lines HL1, HL2, etc. formed by the horizontal shift register HSR, the optical signals accumulated in the photodiodes D1, D2, etc. in the first row are output to the output signal line VS. They are read out in chronological order. This read operation is performed by supplying a current corresponding to the optical signal from the terminal S via a load resistor, and a precharge (reset) operation is performed simultaneously with the read operation. A similar operation is performed in the photodiode in the fourth row. In this case, the reading operation of the fourth row is performed on the dummy output line DVS by the scanning circuit (VSRE, ITGE, DVE) for changing the sensitivity as described above. When only the sensitivity control operation is performed, the same bias voltage as that of the terminal S is applied to the terminal RV. As a result, the optical signal already accumulated in each pixel cell in the fourth row is swept out, in other words, the reset operation is performed.

Therefore, by the above vertical scanning operation, the vertical shift register VSR for reading and the interlace gate circuit ITG
The read operation of the fourth row (vertical scanning line VL4, horizontal signal line HS4) by the driving circuit DV is performed in the first row to the third row.
Since the operation is performed after the row reading operation, the accumulation time of the photodiodes of the pixel cells arranged in the fourth row is the reading time of the pixel cells of three rows.

Instead of the above, a vertical shift register VSR for sensitivity control
E, parallel to reading of the first row (vertical scanning line VL1, horizontal signal line HS1) by read vertical shift register VSR, interlace gate circuit ITG and drive circuit DV by interlace gate circuit ITGE and drive circuit DVE Then, the selection operation of the second row (vertical scanning line VL2, horizontal signal line HS2) is performed. Thus, in synchronization with the operation of selecting the horizontal scanning lines HL1, HL2, etc. formed by the horizontal shift register HSR, the optical signals accumulated in the photodiodes D1, D2, etc. in the first row are output to the output signal line VS. They are read out in chronological order. This read operation is performed by supplying a current corresponding to the optical signal from the terminal S via a load resistor, and a precharge (reset) operation is performed simultaneously with the read operation. A similar operation is performed in the photodiodes D3, D4, and the like in the second row. As a result, an operation of sweeping out the optical signals already accumulated in each pixel cell of the second row is performed in parallel with the above-described read operation of the first row. Accordingly, the read operation of the second row (the vertical scan line VL2 and the horizontal signal line HS2) by the read vertical shift register VSR, the interlace gate circuit ITG, and the drive circuit DV is performed by the vertical scan operation. , The accumulation time of the photodiodes of the pixel cells arranged in the second row is the read time of the pixel cells for one row. As a result, the substantial accumulation time of the photodiode can be reduced to 1/3, in other words, the sensitivity can be reduced to 1/3 as compared with the above case.

As described above, the preceding vertical scanning operation performed by the scanning circuit for sensitivity control resets the pixel cells in the row, so that the actual reading by the scanning circuit for reading is performed from the reset operation. The time until the accumulation is taken as the accumulation time for the photodiode. Therefore, in a pixel array composed of 525 rows, different address designations by the two vertical scanning circuits and a selection operation of pixel cells by a common horizontal scanning circuit allow a maximum (525) of reading time for one row as a unit (minimum). The storage time can be set over multiple steps up to, in other words, 525 steps of sensitivity. However, it is assumed that the change in the illuminance of the light receiving surface is negligible with respect to the scanning time forming one screen, and that substantially constant light is incident on the photodiode. Note that the maximum sensitivity (525) is obtained when the scanning circuit for sensitivity control is not operating.

In the sensitivity control operation as described above, the reading of the pixel signal and the reset operation by the preceding vertical scanning operation are performed in parallel. For this reason, the pixel signal for the reset operation may be mixed with the readout signal due to capacitive coupling via a substrate or the like. When such capacitive coupling occurs, noise such as a ghost in a television receiver is generated in a read pixel signal, and image quality is deteriorated.

Therefore, in this embodiment, the function of forcibly selecting all the horizontal scanning lines from the external terminal SP via the diode-connected MOSFETs QQ30, Q31, etc., for the horizontal scanning lines HL1, HL2, etc. Is added. That is, when the terminal SP is set to a high level, regardless of the operation of the horizontal shift register HSR, all of the diode-type MOSFETs Q30, Q31, etc. are turned on to supply a high level to all the horizontal scanning lines HL1, HL2, etc. Can be selected. Also, since the selection level is supplied through a unidirectional element such as the diode-type MOSFETs Q30 and Q31, the terminal
When the SP is set to the low level, the MOSFETs Q30, Q31 and the like maintain the off state. This prevents the operation of setting the horizontal scanning lines HL1, HL2, and the like according to the shift operation of the horizontal shift register HSR to the selection level in time series even if the forced simultaneous selection circuit as described above is provided. Never. In addition,
If the horizontal shift register HSR is constituted by a dynamic circuit, etc., and the shift operation is adversely affected by the forced selection level of the horizontal scanning lines HL1 and HL2 as described above, the selection level is set to the horizontal shift register. A switch circuit or the like that does not transmit to the inside of the HSR is added.

The simultaneous selection operation of the horizontal scanning lines HL1 and HL2 is performed in a horizontal blanking period as described later, and the preceding vertical scanning is started. Thus, the signals of all the pixels in the row to be reset can be forcibly reset in advance. Therefore, in reading out pixel signals in accordance with the operation of selecting a horizontal scanning line by the horizontal shift register HSR, substantially no pixel signal is output from the preceding row. As a result, the above-described noise does not appear in the read signal even if there is capacitive coupling via the substrate or the like.

FIG. 10 is a block diagram showing an embodiment of an imaging device having the automatic aperture function using the solid-state imaging device. The solid-state imaging device MID has a sensitivity variable function as shown in FIG. The read signal output from the solid-state imaging device MID is amplified by a preamplifier. The amplified signal Vout is supplied to a signal processing circuit (not shown) on the one hand, and becomes an image signal for television, for example. The amplified signal Vout is used for automatic aperture control on the other hand. That is, the amplified signal Vout
Is supplied to a low-pass filter LPF and converted into its average signal level. Although this signal is not particularly limited, it is supplied to a detection circuit DET, where it is converted into a DC signal. The sensitivity control circuit receives the output signal of the detection circuit DET, compares the output signal with a desired aperture amount, and forms a control signal corresponding to the optimal aperture amount. That is, the sensitivity control circuit receives the signals VIN and V1 from the drive circuit that supplies the above-described clock signal for controlling the scanning timing to the solid-state imaging device MID, and refers to the readout timing of the solid-state imaging device MID. To form a signal VINE substantially preceding it. That is, since the preceding timing signal VINE corresponding to the required aperture amount (sensitivity) is formed based on the timing signal VIN, the signal VINE is actually formed later than the timing signal VIN. . However, since the repetitive scanning is performed, the signal VINE
From the viewpoint, it is assumed that the signal VIN is delayed in the next screen scan. That is, when the timing signal VINE is generated one line later than the timing signal VIN, the timing signal VINE is regarded as a timing signal preceding the timing signal VIN by 524 rows in the next scanning screen.
The shift operation of each of the vertical shift registers VSR and VSRE is started by the timing signals VIN and VINE, so that the above-described sensitivity variable operation is performed.

The sensitivity control circuit compares a reference voltage corresponding to a desired aperture amount with an output voltage from the detection circuit DET by, for example, a voltage comparison circuit, and adjusts the aperture amount step by step according to the magnitude. Change. Alternatively, in order to increase the response, the 525-step aperture amount is made to correspond to the binarized signal, and the most significant bit is determined according to the output signal of the voltage comparison circuit. For example, about 1/2 aperture (sensitivity 25
With reference to 6), when the signal of the detection circuit DET is higher than the reference voltage, it is 1/4 (sensitivity 128).
(Sensitivity 384), and the halves of the respective apertures are determined. As a result, one optimal aperture amount can be obtained from ten 525 sensitivity steps by ten setting operations. Setting operation of the aperture amount, in other words, initial setting operation of vertical shift register VSRE for sensitivity control (VINE)
Is performed in the vertical flyback period, it is possible to set the optimal aperture amount in accordance with the read signal operation from ten screens.

Although not particularly limited, the sensitivity control circuit generates a signal SP for the forced reset operation during the horizontal flyback period. In response, the sensitivity control circuit generates a vertical selection signal for the preceding row when the horizontal retrace period starts.

In the imaging device of this embodiment, the sensitivity variable function is built in the solid-state imaging device MID, and the level of the readout output signal is determined to electrically control the sensitivity. Since the sensitivity control circuit can also be constituted by a semiconductor integrated circuit or the like, the device can be reduced in size and weight and can have high durability. Particularly, there is no surveillance camera in an environment where there is no operator and the brightness changes day and night. It is suitable.
In addition, the surveillance camera can be made very small, and its existence can be hidden.

FIG. 11 shows a timing chart of one embodiment of the read operation of the solid-state imaging device. For example, when the vertical scanning line VL1 is at the high level, the reading operation of the first row is performed by sequentially setting the horizontal scanning lines HL1 to HLm to the high level in time series. That is, the current corresponding to the optical signal accumulated in the photodiode of the pixel cell that is successively selected in this way flows, thereby performing a read operation from the pixel cell,
The reset (precharge) operation for the next read operation is performed simultaneously. The voltage signal formed by flowing the photocurrent through the load resistor is amplified and output by the preamplifier shown in FIG. Similarly, when the preceding vertical scanning line VLn is at a high level, the n-th row reset operation is performed in accordance with the time-series selection operation of the horizontal scanning lines HL1 to HLm.

When the read and reset operations for the pair of rows (1, n) are completed, a horizontal retrace period starts. During the horizontal retrace period, the vertical scanning lines VL1 and VLn are changed from a high level to a low level, and are switched to a non-selected state. Then, the terminal RP is set to the high level, and each reset signal shown in FIG.
Turn on the MOSFETs Q27, Q29, etc. As a result, the above-described false signal generated on the non-selected horizontal signal line HS2 and the like is reset. Further, the terminal SP is set to the high level, and all the horizontal scanning lines HL1 to HLm are forcibly set to the selection level. At this time, the vertical scanning line VLn + 1 corresponding to the next preceding row is also set to the high-level selection state for sensitivity control. Therefore, reading (resetting) of all pixels for one row corresponding to the vertical scanning line VLn + 1 for setting the sensitivity is performed.

As a result, when the horizontal retrace period ends and the next second row read operation starts, the horizontal scanning lines HL1 to HLm are sequentially set to the high level in a time-series manner, and the horizontal signal lines HS2 are connected to the horizontal signal lines HS2. Can obtain the above read signal. At this time, no signal is obtained on the preceding horizontal signal line HSn + 1 in the (n + 1) th row because it is immediately after the forced reset. Even if it is obtained, it is an extremely small signal and can be ignored. Therefore, both horizontal signal lines (HS1,
HSn + 1), even if there is capacitive coupling via a substrate or the like,
The sweep signal accompanying the reset operation does not leak to the read signal side. Therefore, a high-quality read signal can be obtained by the forced reset operation in the horizontal flyback period as described above.

The operation and effect obtained from the above embodiment are as follows. (1) A first scanning circuit for outputting signals of a plurality of pixel cells arranged two-dimensionally in time series, and a vertical scanning by an address independent of a selection address in the vertical scanning direction by the first scanning circuit. A second scanning circuit for performing a selection operation in the scanning direction is provided, and the sensitivity is made variable by operating the second scanning circuit in advance, and the pixel cells of the two-dimensionally arranged pixel cells are arranged. An external terminal is provided for forcibly selecting all the horizontal scanning lines for selecting the horizontal scanning direction in a simultaneous selection state, and all pixels in the preceding row are provided by a simultaneous selection signal from the second scanning circuit and the external terminal. The signal can be reset (swept out) within the horizontal retrace period. As a result, it is possible to prevent a substantial pixel signal from being generated on a horizontal signal line corresponding to a preceding vertical scanning line, so that an effect of preventing coupling noise with respect to a read pixel signal can be obtained.

(2) In addition to a first scanning circuit for outputting signals of a plurality of pixel cells arranged two-dimensionally in time series, a selection address in the vertical scanning direction by the first scanning circuit and A second operation of selecting in the vertical scanning direction by an independent address;
And the second scanning circuit performs vertical scanning preceding the vertical scanning by the first scanning circuit, so that the accumulation time of the photoelectric conversion element according to the time difference between the two vertical scanning operations Can be controlled.

(3) According to the above (1) and (2), it is possible to obtain a solid-state imaging device having a variable sensitivity function while maintaining high image quality.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the example circuit of FIG. 9, the interlace gate circuit and the drive circuit can adopt various embodiments according to the scanning method. Further, the vertical scanning lines in the preceding row may be in a selected state only during the horizontal retrace period. In this case, since only the horizontal signal corresponding to the row to be read is output as the read signal, it is possible to completely prevent the generation of noise due to the capacitive coupling as described above.

[0060]

【The invention's effect】

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. By having a cylindrical first storage unit for storing a lens and a second storage unit for storing a device, an ultra-small video camera unit capable of storing a lens and a solid-state imaging device can be provided. Become. Further, it is possible to reduce the size of the lens, eliminate the need for a mechanical aperture, and eliminate the need for a shutter mechanism. This makes it possible to significantly reduce the size of the entire camera.

[0061] Synthetic focal length EFL = 1.0 Brightness F No. = 2.0 Angle of view FA = 87 ° Back focus BF = 0.55 γ: radius of curvature of lens surface d: distance between lens surfaces n: refractive index for d-line of lens ν: Lens dispersion

[0062]

[0063] Seidel aberration coefficient SA: Spherical aberration coefficient CM: Coma aberration coefficient AS: Astigmatism coefficient DS: Distortion aberration coefficient PT: Petzval coefficient

[0064] Synthetic focal length EFL = 1.0 Brightness F No. = 2.0 Angle of view FA = 45 ° Back focus BF = 0.42 γ: radius of curvature of lens surface d: distance between lens surfaces n: refractive index of lens to d-line ν: Lens dispersion

[0065]

[0066] Seidel aberration coefficient SA: Spherical aberration coefficient CM: Coma aberration coefficient AS: Astigmatism coefficient DS: Distortion aberration coefficient PT: Petzval coefficient

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a video camera unit according to the present invention.

FIG. 2 is a plan view thereof.

FIG. 3 is a view for explaining a lens portion used in the camera unit shown in FIGS. 1 and 5;

FIG. 4 is a characteristic diagram of a lens portion.

FIG. 5 is a sectional view showing another embodiment of the present invention.

FIG. 6 is a plan view of another embodiment of the present invention.

FIG. 7 is a sectional view showing another embodiment of the present invention.

FIG. 8 is a diagram showing characteristics of a lens used in another embodiment of FIG. 7;

FIG. 9 is a main part circuit diagram showing one embodiment of an internal circuit of the solid-state imaging chip according to the present invention.

FIG. 10 is a block diagram showing one embodiment of an imaging device using the solid-state imaging chip.

FIG. 11 is a timing chart for explaining an example of the operation of the solid-state imaging chip.

[Explanation of symbols]

L _{1 to} L ₄ …… Plastic lens, 1… Holder, 6…
... Solid-state imaging device, 64 ... Solid-state imaging chip, 14 ... Lid, PD ... Pixel array, VSR ... Read-out vertical shift register, ITG ... Read-out interlace gate circuit, DV ... Read-out drive circuit, VSRE: vertical shift register for sensitivity setting, ITGE: interlace gate circuit for sensitivity setting, DVE: drive circuit for sensitivity setting, HSR: horizontal shift register, MID: solid-state imaging device, LPF: low-pass filter , DET …… Detection circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hirokazu Sokei 3300 Hayano Mobara-shi, Chiba Pref. Mochi Plant, Hitachi, Ltd. (72) Inventor Junichiro Nakajima 3000 Mita, Atsugi-shi, Kanagawa Echonai (72) ) Inventor, Masayuki Takahashi 3000, Mita, Atsugi-shi, Kanagawa Prefecture, Echo Co., Ltd. (72) Inventor Kunio Niwa 3000, Mita, Atsugi-shi, Kanagawa Prefecture, Echo Co., Ltd. (56) References JP-A-63-312780 (JP, A) JP-A-62-188871 (JP, U)

Claims (3)

(57) [Claims] 1. A lens, a solid-state imaging device having a rectangular parallelepiped shape having leads for external connection, a holder for accommodating the lens and the device, a substrate on which the device is provided, and the lens provided on the holder. And a second storage portion for storing the device provided in the holder, the first storage portion being configured to store the device.
Has a first inner wall having an inner diameter substantially the same as the outer diameter of the lens, and the second housing has a shape substantially the same as a rectangular parallelepiped outer periphery of the device so as to store the device. A video camera unit having a second inner wall formed, wherein the holder is provided on the substrate. 2. The video camera unit according to claim 1, wherein said lens is formed as an aspheric surface by a plastic lens. 3. The video camera unit according to claim 1, wherein said solid-state imaging device includes a solid-state imaging circuit capable of electrically varying sensitivity.