JP3238543B2 - Image processing method and image processing apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and an image storage device for performing image processing on a non-standard video signal (luminance signal) using a clock signal synchronized with a burst signal. That is, the present invention relates to an image processing apparatus that performs image processing on a non-standard luminance signal using a memory that operates with a clock signal that is burst locked, for example, an image processing apparatus that implements subtitle processing and noise removal. is there.

[0002] A non-standard video signal includes a subcarrier frequency of f _SC , a horizontal frequency of f _H , and a vertical frequency of f _V
Where f _SC ≠ (455/2) f _H , f _H ≠ (525/2) f
_A typical example of the _V signal is an output signal from a video tape recorder, a NES, or the like.

[0003]

2. Description of the Related Art In recent years, television receivers (hereinafter abbreviated as televisions) have been improved in image quality and deduction of televisions by performing image processing using a storage device such as a semiconductor memory. As shown in FIG. 6, the non-standard video signal includes a vertical synchronization signal a, a horizontal synchronization signal b, a burst signal c, an image signal d, and the like. In the case of a method (hereinafter referred to as a burst lock method) of performing image processing on this non-standard video signal using a clock signal synchronized with a burst signal, the relative position, signal width, and the like in the medium are not standardized. In particular, the interval of the horizontal synchronization signal b is not standardized,
The problem is that the intervals are not constant.

Hereinafter, a conventional image processing method and image processing apparatus will be described. FIG. 4 shows a block diagram of a storage device of an image processing apparatus for implementing an image processing method according to a conventional burst lock method and its peripheral circuits. In FIG. 4, reference numeral 1 denotes a clock generation circuit that generates a signal at regular intervals in synchronization with an input burst signal. Reference numeral 2 denotes a storage device to which an output signal of the clock generation circuit 1, a video signal, and a vertical synchronization signal are input. In such a configuration, when a vertical synchronizing signal is input, the storage device 2 enters a state in which a video signal (luminance signal) is input from the head address, and thereafter, every time a clock signal of the clock generation circuit 1 is input. The video signals are sequentially stored from the head address, and when the next vertical synchronizing signal is input to the storage device 2, the input is terminated and the video signal for one screen is obtained.

FIG. 7 shows a conventional first-in first-out memory (First-in-first-out memory) of an image processing method according to the conventional burst lock method.
In First Out memory; hereinafter, abbreviated as FIFO memory. 3) shows a time chart of each part of the storage device and its peripheral circuits in the image processing apparatus performed by using ()).
Here, FIG. 7A shows a video signal. In the figure, a video signal between a vertical synchronization signal and the next vertical synchronization signal is a video signal for one field. FIG. 7B shows a vertical synchronization pulse obtained from a vertical synchronization signal in a video signal.
A write reset and a read reset of the IFO memory are performed. FIG. 7C shows the write enable pulse and the read enable pulse, which are always “1”.

[0006] In this case, FIF of the structure as shown in FIG. 10
In the O memory 50, a vertical synchronization pulse is input to the write reset terminal 53 and the read reset terminal 54. The video signal is input to the input terminal 51, the write enable pulse is input to the write enable terminal 55, and the read enable pulse is input to the read enable terminal 56. Thus, every time a vertical synchronization pulse is input, the FIFO memory 50 sequentially stores the FIFO address from the head address of the FIFO memory 50 until the next vertical synchronization pulse is input.
The video signal stored in the FO memory 50 is read, and the video signal of the current field is read from the FIFO memory 50.
Write from the first address of 52 is an output terminal.

With the above operation, the reading and writing of the video signal are performed until the next vertical synchronizing signal is input, thereby obtaining a video signal for one screen. FIG. 5 is a block diagram of a storage device of an image processing device that stores a video signal on plane coordinates and a peripheral circuit thereof, which is an improvement of the above-described conventional example. In FIG. 5, reference numeral 11 denotes a clock generation circuit that generates a signal at regular intervals in synchronization with an input burst signal. Reference numeral 12 denotes an address generation circuit to which a signal of the clock generation circuit 11, a horizontal synchronizing signal, and a vertical synchronizing signal are input. Each time the signal of the clock generation circuit 11 is input, one dimension (hereinafter referred to as x-axis) is provided. ), A value obtained by increasing or decreasing a certain number (hereinafter, referred to as “1”) of the current address (hereinafter, referred to as “x”) is defined as “x”, and the address of the other dimension (hereinafter, referred to as “y-axis”). (Hereinafter, referred to as y) is a value that does not change, and an address (x, y)
Is output as a signal. When a horizontal synchronizing signal is input, the address of the x-axis is set to an initial value (hereinafter, the initial value of x is treated as 1), and a fixed number is increased or decreased in the address of the y-axis (hereinafter, referred to as “x”). 1). Further, when a vertical synchronization signal is input, the address of the y-axis is set to an initial value (hereinafter, the initial value of y is treated as 1).

Reference numeral 13 denotes a storage device to which an address of the address generation circuit 12, a video signal (luminance signal), and a vertical synchronizing signal are input, and stores the video signal at the address output from the address generation circuit 12. 14 is an address generation circuit 12
And an address line connecting the address input terminal of the storage device 13 and the number of lines corresponding to the capacity of the storage device 13 is required.

The vertical synchronizing signal input to the storage device 13 is for resetting an address. This is because the storage device 13 wants to store information for one field. In such a configuration, when a vertical synchronizing signal is input to the address generating circuit 12 and then the first horizontal synchronizing signal is input, the address of the address generating circuit 12 is set to the initial value address (1) on both the x-axis and the y-axis. , 1). The clock generation circuit 11 generates a clock signal at regular intervals in synchronization with the burst signal.

When the first clock signal of the clock generation circuit 11 is input to the storage device 13, the storage device 13
The video signal is stored at the address (1, 1). When the second clock signal of the clock generation circuit 11 is input to the storage device 13, the storage device 13 stores the video signal at the address (1, 2). The above operation is repeated until (1, 1) to (1, x) until the second horizontal synchronization signal is input.
The video signals for one horizontal period until ₁ ) are stored in the storage device 13. The value of x is, for example, x = in the NTSC system.
910 ± 30, and x = 1135 ± 30 in the PAL system. As described above, the value of x is not constant.

Next, the second address generation circuit 12
When the horizontal synchronization signal is input, the storage device 13 stores the address
(2, 1) stores a value of a video signal, and generates a clock signal.
Each time 11 clock signals are input to the storage device 13,
Dresses (2,2)-(2, x _Two) Up to the video signal value.
Remember The above operation is repeated until the next vertical synchronization signal
The video signal is stored until the
When the number is input, the input is terminated and the video signal for one screen
No.

Image processing is performed by performing predetermined signal processing on the video signal stored as described above as a video signal for one screen.

[0013]

However, in the conventional image processing method based on the burst lock method, the number of video signals to be stored in one horizontal period (hereinafter referred to as the number of pixels) is determined because the interval between horizontal synchronization signals is not constant. )), And accurate image processing could not be performed. More specifically, for example, when image processing is performed on a non-standard video signal using a FIFO memory, the number of samplings between horizontal synchronization signals, that is, the number of samplings for one frame is different. When a video signal as shown in the figure is processed, as shown in FIG. 7 (d), the position of the video signal of one field before stored in the FIFO memory does not match the position of the video signal of the current frame, and an accurate image is obtained. There was a problem that processing could not be performed.

In the above-mentioned conventional improvement, an address generating circuit is required, and furthermore, many lines and pins are required for transmitting an address, so that the circuit scale becomes large and it is difficult to reduce the size. Had problems. The present invention solves the above conventional problems,
It is an object of the present invention to provide an image processing method and an image processing apparatus which can reduce the circuit scale, facilitate downsizing, and perform accurate image processing in a method of performing image processing of a non-standard video signal by a burst lock method.

[0015]

[Means for Solving the Problems] In order to solve the above-mentioned problems
In addition, the image processing method of the present invention employs a predetermined number
Generates a clock signal for sampling
The raw circuit and the synchronization of the clock signal to the burst signal
To supply a burst signal to the clock generation circuit
Signal supply means and sampling data for non-standard video signals.
Storage means for storing data and a vertical synchronization signal in the storage means.
A vertical synchronizing signal supplying means, a clock generating circuit,
And a horizontal synchronizing signal
And a vertical synchronization signal in the storage means.
After inputting the horizontal sync signal,
Sampled with a clock signal synchronized with the
Video signal data from the horizontal synchronization signal as a starting point.
Input to the predetermined number storage means for each scanning period,
When input is input to the storage means, the input is terminated and one screen
Video signal from the vertical synchronization signal supply means.
Each time a signal is input to the storage means, the video signal for one screen is
Stored in the storage means, and 1 stored in the storage means
Output the video signal for one screen before the field,
Only the video signal stored in the storage means for the video signal of
To perform signal processing.

Further, the image processing apparatus according to the present invention provides a horizontal scanning
Generates a predetermined number of sampling clock signals for each period
Clock generation circuit and burst signal
A burst signal to the clock generation circuit to synchronize
A burst signal supply means for supplying the non-standard video signal;
First-in first-out memory that stores sampling data sequentially
To supply a vertical synchronization signal to the first-in first-out memory.
Synchronous signal supply means, clock generation circuit and first-in first-out
Supply horizontal sync signal to output memory
And a horizontal synchronization signal according to the input of the horizontal synchronization signal.
Synchronize with burst signal every horizontal scanning period starting from signal
Video signals sampled by the clock signal
Data is input to the first-in first-out memory and one vertical scan is performed.
The video signal for one screen is recorded in the first-in first-out memory every period.
And the vertical synchronization signal from the vertical synchronization signal supply means.
Each time a number is entered into the FIFO, the FIFO is
Image of one screen before one field stored in memory
Outputs a signal and pre-empts the input non-standard video signal.
Signal using only the video signal stored in the advance memory.
Processing is performed.

[0017]

According to the present invention, a video signal is stored in a storage device in response to a clock signal for a fixed number of clocks from a horizontal synchronization signal in a video signal for one screen, and only the stored video signal is used. Since the signal processing is performed by using a single address, an address generating circuit is not required, and only one line and pin are required for transmitting an address, so that the circuit scale can be significantly reduced.
In addition, accurate image processing can be performed, and no inconvenience such as a video signal appearing on the screen during the horizontal flyback period occurs.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a storage device of an image processing apparatus according to a first embodiment of the present invention and its peripheral circuits. In FIG. 1, reference numeral 21 denotes a clock signal which is output at regular intervals in synchronization with the input burst signal, and stops outputting the clock signal when the number of clocks reaches a predetermined value after the horizontal synchronization signal is input. It is a clock generation circuit.
Reference numeral 22 denotes a storage device to which a clock signal, a video signal, a vertical synchronization signal, and a horizontal synchronization signal of the clock generation circuit 21 are input. When the vertical synchronization signal is input, a video signal is input from a head address, Thereafter, every time the clock signal of the clock generation circuit 21 is input, the video signal is sequentially stored from the head address.

In such a configuration, when the horizontal synchronizing signal is input to the storage device 22 after the vertical synchronizing signal is input, and further the clock signal of the clock generation circuit 21 is input, the storage device 22 stores the video signal at the head address. Remember. Further, each time the clock signal of the clock generation circuit 21 is input to the storage device 22, the video signal is stored at the address next to the current address. This operation is repeated until the number of clocks of the clock generation circuit 21 reaches a certain value. When the number of clocks of the clock generation circuit 21 exceeds a certain value,
The clock generation circuit 21 does not output a clock signal,
The storage device 22 does not store video signals. Thereafter, when the second horizontal synchronizing signal is input to the clock generation circuit 21, the clock generation circuit 21 is initialized, and the storage device 22 again stores the video signal from the next address where the writing was previously stopped. . The above operation is performed until the next vertical synchronization signal is input to the storage device 22. When the next vertical synchronizing signal is input to the storage device 22, the input is terminated and a video signal for one screen is obtained.

Thus, image processing can be performed on all the horizontal synchronizing signals among the video signals for one screen by using only the image signals within a certain number of clocks from the horizontal synchronizing signal. Image processing can be performed with the same. The period during which the storage device 22 is not storing is set within the horizontal retrace period of the video signal shown in FIG. 6, and the video signal during this period does not include a signal appearing on an actual screen. It has no effect.

According to the image processing apparatus of this embodiment, the video signal is stored in the storage device 22 in response to the clock signal for a fixed number of clocks from the horizontal synchronizing signal in the video signal for one screen, and is stored. Since the signal processing is performed by using only the video signal, the address generation circuit is not required, the number of lines and pins for transmitting the address is one, the circuit scale can be significantly reduced, and the accurate image processing is performed. In addition, there is no inconvenience that the video signal in the horizontal blanking period appears on the screen. Also, by changing the fixed number of clocks, which is the set value of the clock generation circuit 21, it is possible to cope with various television systems.

FIG. 8 is a block diagram of a second embodiment of the present invention, and FIG. 9 is a time chart of each part of the storage device and its peripheral circuits in the second embodiment. The image processing device shown in FIG. 8 includes a FIFO memory 61 and a timing generation circuit 62. Next, the operation will be described with reference to FIGS. FIG. 9A shows a video signal. FIG. 9B shows a vertical synchronizing pulse obtained from a vertical synchronizing signal in the video signal, and performs a write reset and a read reset of the FIFO memory 61. FIG.
(C) is a write enable pulse and a read enable pulse output from the timing generation circuit 62, which are synchronized with the horizontal synchronizing signal, are "1" for a certain number of clocks from the horizontal synchronizing signal, and follow the certain number of clocks. It becomes "0" until the horizontal synchronization pulse of.

In a FIFO memory 50 as shown in FIG. 10, a vertical synchronizing pulse is inputted to a write reset terminal 53 and a read reset terminal 54. The video signal is input to the input terminal 51, the write enable pulse is input to the write enable terminal 55, and the read enable pulse is input to the read enable terminal 56. Thereby, F
Every time a vertical synchronization pulse is input, the FIFO memory 50 sequentially outputs the video signal of the previous field stored in the FIFO memory 50 from the start address of the FIFO memory 50, and outputs the video signal of the current field to the FIFO memory.
The data is stored from the start address of the FO memory 50. 52 is an output terminal.

At this time, if the write enable pulse and the read enable pulse are “1”, the video signal is written to the FIFO memory 50 and the FIFO memory 5
The signal within 0 is read. When the write enable pulse and the read enable pulse are “0”, F
Writing of video signal to IFO memory 50 and FI
Reading of signals from the FO memory 50 is not performed. Therefore, the FIFO is used only during a certain number of clocks from the horizontal synchronization signal.
The memory 50 performs writing and reading of the video signal.

The above-mentioned fixed number of clocks is determined by the television system, for example, 8 in the NTSC system.
80 clocks and 1105 clocks are mainly used in the PAL system. Further, after a certain number of clocks, a period up to the next horizontal synchronizing signal is within a horizontal retrace period of the video signal, and an actual video signal is not included in a period in which reading and writing to the FIFO memory are not performed. This is as described above.

As a result, as shown in FIG. 9D, the positioning of the video signal for each frame can be performed by the horizontal synchronizing signal, and accurate image processing can be performed. Next,
1 shows an image processing apparatus according to an embodiment using the present invention. FIG. 2 is a block diagram of an embodiment of an image processing apparatus when the present invention is used for color noise reduction (hereinafter, referred to as CNR). 2, reference numeral 31 denotes an image processing apparatus (see FIG. 1) according to the embodiment of the present invention, which performs the above-described operation.
A subtractor 32 outputs a difference between the output signal of the storage device 31 and the current video signal. 33 is a multiplier and a subtractor 32
Is multiplied by k. A subtractor 34 outputs a difference between the video signal and the output of the multiplier 33.

With such a configuration, first, when a video signal is input, a signal for one screen is stored in the storage device 31. Next, data is read from the head address, and a difference value from the video signal corresponding to the portion is obtained by the subtractor 32. Further, the difference between the value obtained by multiplying the output value of the subtractor 32 by k by the multiplier 33 and the value of the video signal is obtained by the subtractor 34. This makes it possible to remove noise due to the property that noise has no correlation between screens and the video signal is the same if there is no change between images. By calculating the average of the video signals of n screens, the power of the noise is reduced to 1 /
n, and the amplitude is 1 / n1 / ² .

The coefficient k of the multiplier 33 is selected between 0 <k <1. Noise can be reduced as k approaches 1 in a stationary portion, and image blur decreases as k approaches 0 in a moving image portion. it can. FIG. 3 is a block diagram of an embodiment of an image processing apparatus when the present invention is used for subtitle processing. In FIG. 3, reference numeral 41 denotes a caption clipping device, and among the video signals,
The subtitle signal is cut out and temporarily stored.
Reference numeral 42 denotes an image storage device (see FIG. 1) according to the embodiment of the present invention, which performs the above-described operation. 43 is an image expansion device,
This is an apparatus for extending a video signal having a screen ratio of 4: 3 to a video signal having a screen ratio of 16: 9. An adder 44 can take the sum of the output signal of the image storage device 42 and the output signal of the image expansion device 43.

With the above arrangement, only the subtitle portion is stored in the memory (subtitle clipping device 41 and image storage device 42), delayed for a certain period of time, and the screen ratio 4: 3 is set to 1
Caption processing can be performed by adding to the video signal extended to 6: 9.

[0030]

According to the present invention, accurate image processing can be performed without increasing the circuit scale, and the video signal during the horizontal retrace period does not appear on the screen. Further, by changing the fixed number of clocks, which is a set value of the clock generation circuit, it is possible to cope with various television systems.

[Brief description of the drawings]

FIG. 1 is a block diagram of a storage device and its peripheral circuits in an image processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram of an embodiment of an image processing apparatus in which the present invention is applied to color noise reduction.

FIG. 3 is a block diagram of an embodiment of an image processing apparatus in which the present invention is applied to subtitle processing.

FIG. 4 is a block diagram of a storage device and its peripheral circuits in a first image processing apparatus using a conventional burst lock method.

FIG. 5 is a block diagram of a storage device and its peripheral circuits in a second image processing apparatus using a conventional burst lock method.

FIG. 6 is a configuration diagram of a television video signal.

FIG. 7 is a time chart of each part of a storage device and its peripheral circuits in a conventional image processing apparatus.

FIG. 8 is a configuration diagram of a second embodiment of the present invention.

FIG. 9 is a time chart of each part of the storage device and its peripheral circuits according to the second embodiment of the present invention.

FIG. 10 is a configuration diagram of a FIFO memory.

[Explanation of symbols]

 21 clock generation circuit 22 image processing device

Continuation of the front page (56) References JP-A-5-130569 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 5/00-5/42 G06T 1/60 H04N 5 / 04 H04N 5/14 H04N 9/89

Claims (2)

(57) [Claims] A predetermined number of samplings are performed every horizontal scanning period.
A clock generation circuit for generating a clock signal for
The clock is used to synchronize the clock signal with the burst signal.
Burst for supplying the burst signal to a lock generation circuit
Signal supply means and sampling data for non-standard video signals.
Storage means for storing data, and a vertical synchronization signal stored in the storage means.
Vertical synchronizing signal supply means for supplying
Horizontal circuit for supplying a horizontal synchronizing signal to the circuit and the storage means
A synchronizing signal supply means;
After inputting the vertical sync signal to the stage, input the horizontal sync signal.
And a clock synchronized with the burst signal.
The video signal data sampled by the
A predetermined number of the above-mentioned memories are stored every horizontal scanning period starting from a synchronization signal.
And the next vertical synchronizing signal is input to the storage means.
When the input is completed, the video signal for one screen is terminated,
The vertical synchronization signal from the vertical synchronization signal supply means is
Each time it is input to the storage means, the video signal for one screen is
Stored in the storage means and stored in the storage means
Output the video signal for one screen one field before
The non-standard video signal is stored in the storage means.
Signal processing using only the video signal
Burst-lock image processing method. 2. A method according to claim 1 , wherein a predetermined number of samplings are performed every horizontal scanning period.
A clock generation circuit for generating a clock signal for
The clock is used to synchronize the clock signal with the burst signal.
Burst for supplying the burst signal to a lock generation circuit
Signal supply means and sampling data for non-standard video signals.
A first-in first-out memory for sequentially storing data,
Vertical sync signal supply to supply vertical sync signal to output memory
Means, said clock generation circuit and said first in first out
Horizontal synchronization signal supply means for supplying a horizontal synchronization signal to a memory
The horizontal synchronization signal according to the input of the horizontal synchronization signal
Starting from the synchronization signal, the burst signal is output every horizontal scanning period.
A predetermined number sampled with a clock signal synchronized with the signal
Video signal data into the first-in first-out memory.
The video signal for one screen every one vertical scanning period.
The vertical synchronization signal is stored in a first-out memory.
The vertical synchronization signal is supplied from the supply means to the first-in first-out memory.
Each time the data is input to the memory, it is stored in the first-in first-out memory.
The 1 field before the one screen output video signals
And the first-in-first-out is applied to the input non-standard video signal.
Signal processing using only the video signal stored in the advance memory
Burst lock method characterized by performing
Wherein the image processing apparatus.