JP3234729B2 - Power system stabilizer and control method using the same - Google Patents

Power system stabilizer and control method using the same

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Publication number
JP3234729B2
JP3234729B2 JP31313294A JP31313294A JP3234729B2 JP 3234729 B2 JP3234729 B2 JP 3234729B2 JP 31313294 A JP31313294 A JP 31313294A JP 31313294 A JP31313294 A JP 31313294A JP 3234729 B2 JP3234729 B2 JP 3234729B2
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JP
Japan
Prior art keywords
gain
power
active power
frequency
phase
Prior art date
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JP31313294A
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Japanese (ja)
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JPH08168177A (en
Inventor
茂 田口
実 萬城
陽一 加藤
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Hitachi Ltd
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Hitachi Ltd
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は同期発電機の励磁装置を
制御する電力系統安定化装置(PSS)に係り、動的定
態安定度を最適化する電力系統安定化制御方式に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power system stabilizing device (PSS) for controlling an exciting device of a synchronous generator, and more particularly to a power system stabilizing control method for optimizing a dynamic steady state stability.

【0002】[0002]

【従来の技術】図2に示すように、従来の電力系統安定
化装置は、同期機の運転状態の変化に対して平均的な安
定度向上を図るものが多い。同図の一点鎖線で囲んだP
SSは、電力系統の動揺情報として、計器用変圧器(P
T)3と変流器(CT)4から有効電力(P)を有効電
力検出装置6により検出し、信号Pから直流分除去回路
12を介して変化分(ΔP)を取り出し、ΔP信号の増
加時に端子電圧(VG)が増加するように、ΔP信号の
減少時にVGが減少するように、ゲイン調整回路10で
信号のゲイン、位相調整回路19で信号の位相を調整す
る。
2. Description of the Related Art As shown in FIG. 2, many conventional power system stabilizing devices aim to improve the average stability against changes in the operating state of a synchronous machine. P surrounded by a dashed line in FIG.
SS is an instrument transformer (P
T) 3 and the active current (P) from the current transformer (CT) 4 are detected by the active power detection device 6, the change (ΔP) is extracted from the signal P via the DC component removing circuit 12, and the ΔP signal is increased. The gain adjustment circuit 10 adjusts the signal gain and the phase adjustment circuit 19 adjusts the signal phase so that the terminal voltage (VG) sometimes increases and VG decreases when the ΔP signal decreases.

【0003】このように調整されたPSS出力Vpss
は、二点鎖線で囲んだ自動電圧調整装置(AVR)に入
力される。AVRの信号加算回路18は、Vpss、基準
電圧Vref及び端子電圧VG(負)を印加して、その出
力を増減して励磁機2に与え、Gen−AVR系(励磁
系)の動的定態安定度を向上している。
The PSS output Vpss adjusted in this way
Is input to an automatic voltage regulator (AVR) surrounded by a two-dot chain line. The AVR signal adding circuit 18 applies Vpss, the reference voltage Vref, and the terminal voltage VG (negative), increases or decreases the output, and supplies the output to the exciter 2 to dynamically generate a Gen-AVR system (excitation system). Improves stability.

【0004】上記例では、ゲイン調整回路や位相調整回
路の設定値を固定しているが、これらを運転状態に応じ
て変化させ、より動態安定度の向上を図るPSSが提案
されている。特開昭61−280714号公報に記載の
方式は、発電機出力と、発電機回転数または系統周波数
を検出する二つのPSSをもち、発電機の動揺量に応じ
て位相補正要素の時定数を変化させる。特開平1−10
3199号公報に記載の方式は、電力動揺の周期を検出
し、その変化よりファジー推論して位相進み遅れ回路を
補正する。
[0004] In the above example, the set values of the gain adjustment circuit and the phase adjustment circuit are fixed, but a PSS has been proposed in which these values are changed in accordance with the operation state to further improve the dynamic stability. The method described in Japanese Patent Application Laid-Open No. 61-280714 has two PSSs for detecting a generator output and a generator rotation speed or a system frequency, and sets a time constant of a phase correction element according to a fluctuation amount of the generator. Change. JP-A-1-10
The method described in Japanese Patent No. 3199 detects a period of power fluctuation, and corrects a phase advance / delay circuit by fuzzy inference based on the change.

【0005】[0005]

【発明が解決しようとする課題】運転状態に対応し設定
値を変化する従来のPSSにおいては、複数の回路の時
定数を補正するため構成が複雑となったり、一つの入力
からの推論によって補正するために補正の精度が低いな
どの問題があった。
In a conventional PSS in which a set value is changed in accordance with an operation state, the structure is complicated to correct the time constants of a plurality of circuits, or the correction is made by inference from one input. Therefore, there is a problem that the accuracy of correction is low.

【0006】本発明の目的は、複数の入力信号から運転
状態を推定して、簡単且つ高精度にゲイン補正ができ、
動的定態安定度を向上できる電力系統安定化装置とそれ
による制御方法を提供することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to estimate an operating state from a plurality of input signals and to easily and accurately correct a gain.
An object of the present invention is to provide a power system stabilizing device capable of improving the dynamic steady state stability and a control method using the same.

【0007】本発明の目的は、入力信号の異常ないしは
系統事故時に、同期機の出力が不安定となるのを防止
し、安定な制御を維持する電力系統安定化装置とそれに
よる制御方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a power system stabilizing device for preventing the output of a synchronous machine from becoming unstable and maintaining stable control when an input signal is abnormal or a system fault, and a control method using the same. Is to do.

【0008】[0008]

【課題を解決するための手段】本発明の目的は、電力系
統を安定化する電力系統安定化装置において、有効電力
の変化分から電力動揺の減衰率を求め、該減衰率に応じ
て有効電力ゲインを更新し、系統周波数の変化分からA
VRの遅れによる位相差を求め、該位相差に応じて位相
補正ゲインを更新し、前記有効電力またはその変化分と
前記有効電力ゲインの乗算値と、前記周波数またはその
変化分と前記位相補正ゲインの乗算値とのベクトル和を
前記AVRの入力とすることにより達成される。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a power system stabilizing device for stabilizing a power system, wherein a power fluctuation decay rate is obtained from a change in active power, and an active power gain is determined in accordance with the decay rate. Is updated and A is calculated from the change in the system frequency.
Calculating a phase difference due to a delay of VR, updating a phase correction gain according to the phase difference, multiplying the active power or a change thereof by the active power gain, the frequency or a change thereof and the phase correction gain; This is achieved by inputting the AVR as a vector sum with the multiplied value of.

【0009】前記有効電力ゲインの補正は、前記減衰率
が基準減衰率以下のとき、更新前のゲインに所定値を乗
算または加算することを特徴とする。
The correction of the active power gain is characterized in that when the attenuation rate is equal to or less than a reference attenuation rate, the gain before updating is multiplied or added by a predetermined value.

【0010】前記位相補正ゲインは、前記減衰率が基準
減衰率以下のとき、更新前のゲインに所定値を乗算また
は加算し、かつ、前記AVRの遅れによる位相差がその
範囲に0を含む所定範囲を超えるとき、前記位相差に応
じて正または負に増大する値を加算することを特徴とす
る。
When the attenuation rate is equal to or less than a reference attenuation rate, the phase correction gain multiplies or adds a gain before updating by a predetermined value, and the phase difference due to the delay of the AVR includes 0 in its range. When the value exceeds the range, a value that increases positively or negatively according to the phase difference is added.

【0011】前記AVRの遅れによる位相差は、前記系
統周波数または前記発電機の回転数の位相と前記励磁装
置の内部誘起電圧の位相の差となることを特徴とする。
[0011] The phase difference due to the delay of the AVR is a difference between the phase of the system frequency or the rotation speed of the generator and the phase of the internal induced voltage of the excitation device.

【0012】また、本発明の目的は、電力系統を安定化
する電力系統安定化装置において、系統の有効電力及び
周波数と、励磁装置の内部誘起電圧とから状態推定した
電力動揺の減衰率や周波数変動を基に、90°位相の異
なる有効電力(または変化分)と周波数(または変化
分)に乗ずる有効電力ゲインと位相補正ゲインの比率を
動的に変更して、前記周波数と前記内部誘起電圧の位相
が等しくなるように前記PSS出力を決定することによ
り達成される。
Another object of the present invention is to provide a power system stabilizing device for stabilizing a power system, the power fluctuation damping rate and the frequency estimated from the active power and frequency of the system and the internal induced voltage of the exciter. Based on the fluctuation, the ratio of the active power gain and the phase correction gain multiplied by the active power (or the change) and the frequency (or the change) having a phase difference of 90 ° is dynamically changed, so that the frequency and the internal induced voltage are changed. Is determined by determining the PSS output such that the phases of the PSS and PSS are equal.

【0013】さらに、本発明の目的は、前記有効電力ゲ
イン及び位相補正ゲインに、所定の制限を経て更新する
ことにより達成される。
Further, the object of the present invention is achieved by updating the active power gain and the phase correction gain through predetermined restrictions.

【0014】[0014]

【作用】本発明によれば、系統からの入力信号などに基
づいて、同期機の運転状態、即ち、電力動揺の減衰率や
AVR系遅れによる周波数位相差を推定し、その推定値
に応じて、有効電力ゲインと位相補正ゲインをダイナミ
ックに変化することができるので、運転状態に適応した
安定度の向上が可能になる。
According to the present invention, the operating state of the synchronous machine, that is, the power fluctuation decay rate and the frequency / phase difference due to the AVR system delay are estimated based on the input signal from the system and the like. Since the active power gain and the phase correction gain can be dynamically changed, it is possible to improve the stability adapted to the operation state.

【0015】また、重み加算係数リミッタ、重み加算係
数変化率リミッタ、系統事故検出装置により、前記有効
電力ゲインと位相補正ゲインの更新に制限を加え、入力
信号の異常ないし系統故障時に、同期機の安定な運転を
確保できる。
Further, a weight addition coefficient limiter, a weight addition coefficient rate-of-change limiter, and a system fault detection device limit the updating of the active power gain and the phase correction gain. Stable operation can be secured.

【0016】[0016]

【実施例】以下、本発明の実施例を図を参照して詳細に
説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

【0017】図1は、本発明の電力系統安定化装置(P
SS)を適用した励磁系(AVR−Gen系)の構成図
である。同図で、一点鎖線の囲みは一実施例によるPS
Sの構成を示している。
FIG. 1 shows a power system stabilizing device (P) according to the present invention.
FIG. 2 is a configuration diagram of an excitation system (AVR-Gen system) to which SS) is applied. In the same figure, the dashed-dotted line surrounds the PS according to one embodiment.
The configuration of S is shown.

【0018】本実施例のPSSは、電力系統の動揺情報
として、有効電力Pと内部周波数fを入力信号としてい
る。有効電力Pは、PT3とCT4から有効電力検出装
置5により検出し、周波数fはPT3から周波数検出装
置6により検出する。
The PSS of this embodiment uses an active power P and an internal frequency f as input signals as power system fluctuation information. The active power P is detected from PT3 and CT4 by the active power detection device 5, and the frequency f is detected from PT3 by the frequency detection device 6.

【0019】有効電力PはPゲイン調整回路10で重み
加算係数−Kpを乗算され、周波数fはfゲイン調整回
路11で重み加算係数Kfを乗算され、それらを加算し
て直流分除去回路12の入力とする。このように、Pゲ
イン調整回路10とfゲイン調整回路11の重み加算係
数−Kp、Kfにより調整し、2信号を加算することで
ゲイン調整と位相調整を共に実現している。
The active power P is multiplied by a weight addition coefficient −Kp in a P gain adjustment circuit 10, and the frequency f is multiplied by a weight addition coefficient Kf in an f gain adjustment circuit 11. Take as input. As described above, the gain adjustment and the phase adjustment are realized by adjusting the weighted addition coefficients −Kp and Kf of the P gain adjustment circuit 10 and the f gain adjustment circuit 11 and adding two signals.

【0020】直流分除去回路12は、不完全微分回路に
よって構成し、有効電力と周波数の加算信号から直流成
分を除去し、系統動揺情報である交流成分のみとする。
直流分除去回路12の出力は、出力リミッタ17を経由
してPSS出力信号Vpss とすることで、過大な出力信
号がAVRの信号加算回路18に与えられないようにし
ている。
The DC component removing circuit 12 is constituted by an incomplete differentiating circuit, and removes a DC component from an added signal of the active power and the frequency so as to leave only an AC component as system fluctuation information.
The output of the DC component removing circuit 12 is set to the PSS output signal Vpss via the output limiter 17 so that an excessive output signal is not supplied to the AVR signal adding circuit 18.

【0021】PSS出力信号Vpssは、自動電圧調整
装置AVRへの補助信号として信号加算回路18に与え
られる。AVRは、信号加算回路18の出力信号を増幅
回路14によって増幅し、励磁機2を制御することによ
り、同期機1の界磁電流を変化させ、動的定態安定度を
最適化するように構成されている。
The PSS output signal Vpss is supplied to the signal adding circuit 18 as an auxiliary signal to the automatic voltage regulator AVR. The AVR amplifies the output signal of the signal addition circuit 18 by the amplifier circuit 14 and controls the exciter 2 to change the field current of the synchronous machine 1 and optimize the dynamic steady state stability. It is configured.

【0022】ところで、有効電力P及び周波数fと、励
磁機2の界磁電圧Vf、界磁電流Ifから誘起電圧検出
回路7で求められた内部誘起電圧Eq’を状態推定器8
に入力する。状態推定器8は、これらの入力信号から減
衰率σと動揺周波数(△θ)を決定し、これらを重み加
算係数算出回路9に入力して有効電力P、周波数f各々
の重み加算係数を算出し、Pゲイン調整回路10、fゲ
イン調整回路11の重み加算係数−Kp、Kfの値を動
的に変更する。
By the way, the internal induced voltage Eq ′ obtained by the induced voltage detecting circuit 7 from the active power P and the frequency f, the field voltage Vf of the exciter 2 and the field current If is used as a state estimator 8.
To enter. The state estimator 8 determines the attenuation rate σ and the oscillation frequency (△ θ) from these input signals, and inputs them to the weight addition coefficient calculation circuit 9 to calculate the weight addition coefficients of the active power P and the frequency f. Then, the values of the weight addition coefficients -Kp and Kf of the P gain adjustment circuit 10 and the f gain adjustment circuit 11 are dynamically changed.

【0023】図3に、状態推定器8と重み加算係数算出
回路9の構成を示す。状態推定器8は、有効電力P、周
波数f及び内部誘起電圧Eq’各々の変化分△P、△
f、△Eq’検出する変化分検出回路20、21、22
を有している。なお、変化分検出回路20、21、22
は、直流分除去回路12と同様の構成となる。
FIG. 3 shows the configuration of the state estimator 8 and the weight addition coefficient calculation circuit 9. The state estimator 8 calculates the change amount {P,} of each of the active power P, the frequency f, and the internal induced voltage Eq ′.
f, change detection circuits 20, 21, 22 for detecting △ Eq '
have. The change detecting circuits 20, 21, 22
Has the same configuration as the DC component removing circuit 12.

【0024】振幅値検出回路23は△Pの振幅値Aを検
出し、振幅値比較器24により振幅基準値Arefと比較
し、A≧Arefのときは△Pを減衰率検出回路25に入
力して減衰率σを検出する。図4に示すように、△Pの
振幅曲線はA=Bε(-σt)となるので、これより電力
動揺の現在の減衰率σを求めることができる。
The amplitude value detection circuit 23 detects the amplitude value A of ΔP, compares it with the amplitude reference value Aref by the amplitude value comparator 24, and inputs ΔP to the attenuation rate detection circuit 25 when A ≧ Aref. To detect the attenuation rate σ. As shown in FIG. 4, since the amplitude curve of ΔP is A = Bε (−σt), the current attenuation rate σ of the power fluctuation can be obtained from this.

【0025】減衰率比較器26は、減衰率σを減衰率基
準値σref1と比較し、σ≦σref1のときは正の数(重み
?)αを1以上(α≧1)とする。重み加算係数加減器
27は、重み加算係数Kp、Kf’を(数1)によって
算出し、1周期ごとに前回の重み加算係数(Kold)よ
り大きくして、電力動揺の減衰率を増加させる。今回の
減衰率σが基準値σref1を超えると、重み加算係数K
p、Kf’は変化させない。
The attenuation rate comparator 26 compares the attenuation rate σ with an attenuation rate reference value σref1, and when σ ≦ σref1, sets a positive number (weight?) Α to 1 or more (α ≧ 1). The weight addition coefficient adder / subtractor 27 calculates the weight addition coefficients Kp and Kf ′ by (Equation 1), and increases the weight addition coefficient (Kold) every cycle to increase the power fluctuation attenuation rate. When the current attenuation rate σ exceeds the reference value σref1, the weight addition coefficient K
p and Kf 'are not changed.

【0026】[0026]

【数1】Kp=αKpold Kf'=αKfold なお、正の数αは、(数1)の乗算によらず、加算する
ようにしてもよい。これによって、電力動揺の減衰率σ
に対応するPゲイン調整回路10の重み加算係数Kpが
決定される。
Kp = αKpold Kf ′ = αKfold The positive number α may be added instead of multiplying (Equation 1). As a result, the power fluctuation attenuation rate σ
Is determined, the weight addition coefficient Kp of the P gain adjustment circuit 10 corresponding to.

【0027】一方、fゲイン調整回路11の重み加算係
数Kfは、内部誘起電圧と周波数の変化文の位相が一致
するように、(数1)で求めたKf’をさらに補正して
決定する必要がある。
On the other hand, the weighting addition coefficient Kf of the f gain adjustment circuit 11 needs to be determined by further correcting Kf ′ obtained by (Equation 1) so that the phase of the variation statement of the frequency matches the internal induced voltage. There is.

【0028】ところで、系統の電力動揺と周波数動揺の
間には強い相互関係がある。図5に図1の励磁系の構成
を一機無限大母線系とした概略の等価回路、図7にその
一機無限大母線系を線形近似化したブロック図を示す。
By the way, there is a strong correlation between the power fluctuation and the frequency fluctuation of the system. FIG. 5 is a schematic equivalent circuit in which the configuration of the excitation system in FIG. 1 is a single-machine infinite bus system, and FIG. 7 is a block diagram in which the single-machine infinite bus system is linearly approximated.

【0029】図7のブロック図で、角周波数変化分△ω
と内部誘起電圧変化分△Eq’の位相が一致すれば減衰
率σが大になるので、電力の動揺を抑制するためには、
△ωと△Eq’の位相を等しくする必要がある。なお、
△fの位相は△ωの位相と等しい。ここで、内部誘起電
圧Eq’は図6のベクトル図に示され、(数2)により
求まる。
In the block diagram of FIG. 7, the angular frequency change Δω
If the phase of the internal induced voltage change △ Eq ′ matches the attenuation rate σ, the power fluctuation can be suppressed by:
It is necessary to make the phases of Δω and ΔEq 'equal. In addition,
The phase of Δf is equal to the phase of Δω. Here, the internal induced voltage Eq ′ is shown in the vector diagram of FIG. 6, and is obtained by (Equation 2).

【0030】[0030]

【数2】Eq'=Ei−(xd−xd’)id ここで、Ei=xad・If xad=xd−xl id=(Eq’−Ecosδ)/(xe+xd’) xd:直軸同期リアクタンス xd’:直軸過渡リアクタンス xl:電機子漏洩リアクタンス △ωと△Eq’の位相を等しくするため、変化分検出回
路21で検出した内部誘起電圧の変化分△Eq’から、
位相検出回路28で位相θ△Eq'を検出する。同時に、
変化分検出回路22で検出した周波数の変化分△fか
ら、位相検出回路29で位相θ△fを検出する。
Eq ′ = Ei− (xd−xd ′) id where Ei = xad · If xad = xd−xlid = (Eq′−Ecosδ) / (xe + xd ′) xd: direct axis synchronous reactance xd ′ : Linear axis transient reactance xl: Armature leakage reactance In order to make the phases of Δω and △ Eq 'equal, from the variation △ Eq' of the internal induced voltage detected by the variation detecting circuit 21,
The phase detection circuit 28 detects the phase θ ΔEq ′ . at the same time,
The phase detection circuit 29 detects the phase θ Δf from the frequency change Δf detected by the change detection circuit 22.

【0031】次に、位相θ△Eq'と位相θ△fの位相差△
θを求め、位相補正ゲイン算出回路30に入力する。位
相補正ゲイン算出回路33は位相補正ゲインβを、位相
差△θが一定値(±φ)以内であれば0、一定値を超え
れば所定の関数関係、例えば定数kに比例する値として
(数3)より算出し、さらに上下限リミッタを通して出
力する。
[0031] Next, the phase difference of the phase θ △ Eq 'and the phase θ △ f △
θ is obtained and input to the phase correction gain calculation circuit 30. The phase correction gain calculation circuit 33 sets the phase correction gain β to 0 if the phase difference Δθ is within a predetermined value (± φ), and to a predetermined functional relationship, for example, a value proportional to a constant k if the phase difference Δθ exceeds the predetermined value (numerical value). 3) and output through upper and lower limiters.

【0032】[0032]

【数3】β=0 (if; −φ≦△θ≦φ) =k・△θ (else) 位相補正ゲインβは(数3)から明らかなように、周波
数fと内部誘起電圧Eq’の位相差△θが一定範囲(±
φ)を超えたとき、両者の位相調整を行うための変化分
である。
Β = 0 (if; −φ ≦ △ θ ≦ φ) = k · △ θ (else) As is apparent from (Formula 3), the phase correction gain β is the difference between the frequency f and the internal induced voltage Eq ′. The phase difference △ θ is within a certain range (±
When it exceeds φ), it is a change for performing phase adjustment between the two.

【0033】位相補正ゲイン乗算回路31はこの位相補
正ゲインβを、有効電力変化分△Pを基に算出された重
み加算係数Kf’に乗算して、fゲイン調整回路11の
重み加算係数Kfを(数4)より決定する。
The phase correction gain multiplication circuit 31 multiplies the phase correction gain β by the weight addition coefficient Kf ′ calculated based on the active power change ΔP, and calculates the weight addition coefficient Kf of the f gain adjustment circuit 11. Determined from (Equation 4).

【0034】[0034]

【数4】Kf=(1+β)・Kf’ 図8は、本実施例のPSSによる位相調整を説明するベ
クトル図で、同図(a)は調整前、同図(b)は調整後
を示している。図示のように、AVR−Gen系(励磁
系)で、有効電力Pの入力値Pinまたはその変化分△
Pinと、周波数fの入力値finまたはその変化分△
finは、90°位相が異なる。
## EQU4 ## Kf = (1 + .beta.). Kf 'FIG. 8 is a vector diagram for explaining the phase adjustment by the PSS of this embodiment. FIG. 8A shows the state before adjustment, and FIG. 8B shows the state after adjustment. ing. As shown in the figure, in the AVR-Gen system (excitation system), the input value Pin of the active power P or the change △
Pin and the input value fin of the frequency f or the change thereof △
The fins have a 90 ° phase difference.

【0035】電力動揺の減衰率を大きくするためには、
内部誘起電圧Eq’と周波数fの位相を等しくする必要
があるが、PSSの出力はAVR−Gen系によって遅
れ、内部有機電圧Eq’は周波数fより△θの位相差を
生じる。
In order to increase the power fluctuation damping rate,
It is necessary to make the phase of the internal induced voltage Eq 'equal to the frequency f, but the output of the PSS is delayed by the AVR-Gen system, and the internal organic voltage Eq' has a phase difference of △ θ from the frequency f.

【0036】そこで、(数3)により決定した位相補正
ゲインβにより、△fと△Eq’の位相が一致するよう
に、図8(b)に示すように例えばKfを大きくして、
Kp・△PinとKf・△finの比率(ベクトル和)
を変え、PSS出力を決定している。すなわち、位相補
正ゲインβにより、PSS出力の△fに対する進み角を
決定している。
Then, for example, Kf is increased by the phase correction gain β determined by (Equation 3) so that the phases of △ f and △ Eq 'coincide with each other, as shown in FIG.
Ratio of Kp · △ Pin and Kf · △ fin (vector sum)
Is changed to determine the PSS output. That is, the lead angle of the PSS output with respect to Δf is determined by the phase correction gain β.

【0037】図9は、変動する入力信号を同定する振動
状態同定手段の一例を示す。所定入力信号xがサンプリ
ング周期H(s)で4周期分取り込まれ、時系列信号x
(0)と、サンプリング遅延装置Z~1の1段を経た時系
列信号x(1)と、2段を経た時系列信号x(2)と、
3段を経た時系列信号x(3)との4時系列信号から、
周知の演算を経て信号状態を同定する。本実施例では、
時系列入力信号として有効電力変化分△Pinを用い、
同定の結果より振幅値A、減衰率σ、周波数ωを算出し
ている。すなわち、上記振幅値検出手段23、減衰率検
出手段25及び周波数検出手段6などを実現している。
FIG. 9 shows an example of a vibration state identification means for identifying a fluctuating input signal. A predetermined input signal x is captured for four periods at a sampling period H (s), and a time-series signal x
(0) and, as when passing through the first stage of the sampling delay device Z ~ 1-series signal x (1), and the time-series signal through the two-stage x (2),
From the four time series signals with the time series signal x (3) having passed through three stages,
The signal state is identified through a known operation. In this embodiment,
Using the active power change ΔPin as a time-series input signal,
The amplitude value A, the attenuation rate σ, and the frequency ω are calculated from the identification result. That is, the amplitude value detecting means 23, the attenuation rate detecting means 25, the frequency detecting means 6, and the like are realized.

【0038】このような本実施例のPSSによれば、系
統状態から推定した減衰率や周波数変動を基に、90°
位相の異なる△Pと△fのゲインの比率を動的に制御し
て、△ωと△Eq'の位相が等しくなるようにPSS出
力を決定するので、電力動揺の減衰率を大きくでき、A
VR−Gen系の動態安定度を向上できる。
According to such a PSS of the present embodiment, 90 ° is used based on the attenuation rate and the frequency fluctuation estimated from the system state.
Since the ratio of the gain of ΔP and the gain of Δf having different phases is dynamically controlled and the PSS output is determined so that the phases of Δω and ΔEq ′ become equal, the attenuation rate of the power fluctuation can be increased.
The dynamic stability of the VR-Gen system can be improved.

【0039】次に、本発明の第二の実施例を説明する。
図10に、重み加算係数リミッタを付加したPSSを示
す。入力信号に異常が発生した場合、あるいは、状態推
定器8や、重み加算係数算出回路9などに異常が発生し
た場合、重み加算係数が急変することを防止するため
に、重み加算係数算出回路9の各出力に、有効電力重み
加算係数リミッタ40、周波数重み加算係数リミッタ4
1を設置する。
Next, a second embodiment of the present invention will be described.
FIG. 10 shows a PSS to which a weight addition coefficient limiter has been added. When an abnormality occurs in the input signal, or when an abnormality occurs in the state estimator 8, the weight addition coefficient calculation circuit 9, or the like, the weight addition coefficient calculation circuit 9 is used to prevent a sudden change in the weight addition coefficient. , An active power weight addition coefficient limiter 40 and a frequency weight addition coefficient limiter 4
1 is set.

【0040】重み加算係数リミッタは、重み加算係数K
を入力値とし、その変化率の絶対値|dK/dt|が一
定値ε以下のときは、重み加算係数Kをそのまま出力す
る。一方、変化率の絶対値がε以上のときは、自己(重
み加算係数リミッタ)の1周期前の出力にε・Δtを加
算した値を、重み加算係数Kとして出力する。
The weight addition coefficient limiter calculates the weight addition coefficient K
When the absolute value | dK / dt | of the rate of change is equal to or smaller than the fixed value ε, the weight addition coefficient K is output as it is. On the other hand, when the absolute value of the rate of change is equal to or larger than ε, a value obtained by adding ε · Δt to the output of the self (weight addition coefficient limiter) one cycle before is output as the weight addition coefficient K.

【0041】本実施例では、重み加算係数算出回路9の
出力Kpに対しては(数5)、Kfに対しては(数6)
により、それぞれ変化率制限が行われる。ただし、si
gn(x)は、符号関数で、sign(x)=1(x≧
0)または−1(x<0)となる。Δtは計算周期であ
る。
In this embodiment, the output Kp of the weight addition coefficient calculation circuit 9 is given by (Equation 5), and the output Kp is given by (Equation 6)
Respectively, the rate of change is limited. Where si
gn (x) is a sign function, and sign (x) = 1 (x ≧
0) or -1 (x <0). Δt is a calculation cycle.

【0042】[0042]

【数5】 │dKpi/dt│<ε1 Kpi=Kpi │dKpi/dt│≧ε1 Kpi=Kpi-1+ε1・Δt・ sign(dKpi/dt)| DKpi / dt | <ε1 Kpi = Kpi | dKpi / dt | ≧ ε1 Kpi = Kpi−1 + ε1 · Δt · sign (dKpi / dt)

【0043】[0043]

【数6】 │dKfi/dt│<ε2 Kfi=Kfi │dKfi/dt│≧ε2 Kfi=Kfi-1+ε2・Δt・ sign(dKfi/dt) 本実施例によれば、重み加算係数Kの変化率が一定値ε
以上急変した場合、今回の出力値が、前回出力値にε・
Δtを加算した値に制限されるので、入力信号が異常な
場合にも補正係数が急変ないし過大になるのを防止で
き、PSS出力を安定に維持することができる。
| DKfi / dt | <ε2 Kfi = Kfi | dKfi / dt | ≧ ε2 Kfi = Kfi−1 + ε2 · Δt · sign (dKfi / dt) According to the present embodiment, the rate of change of the weight addition coefficient K is Constant value ε
If there is a sudden change above, the current output value will be
Since the correction coefficient is limited to the value obtained by adding Δt, the correction coefficient can be prevented from suddenly changing or becoming excessive even when the input signal is abnormal, and the PSS output can be stably maintained.

【0044】なお、上記実施例で、リミッタ40、41
は単に上下限値を制限し、加算係数が過大になることを
防止する構成、あるいは、変化率と上下限値の両方を制
限する構成としてもよい。
In the above embodiment, the limiters 40, 41
May be configured to simply limit the upper and lower limits to prevent the addition coefficient from becoming excessive, or to limit both the rate of change and the upper and lower limits.

【0045】次に、本発明の第三の実施例を説明する。
図11に、系統事故発生時の重み加算係数の切替回路を
示す。有効電力重み加算係数切替回路42、周波数重み
加算係数切替回路43は、入力された係数Kを系統正常
時の場合と異常時の場合で切替る。正常時は入力された
係数をそのまま出力し、系統事故検出装置24から事故
検出信号が出力される異常時は、1周期前の重み加算係
数をそのまま出力、あるいは、系統異常時に適した所定
値を出力する。
Next, a third embodiment of the present invention will be described.
FIG. 11 shows a circuit for switching the weight addition coefficient when a system fault occurs. The active power weighting addition coefficient switching circuit 42 and the frequency weighting addition coefficient switching circuit 43 switch the input coefficient K depending on whether the system is normal or abnormal. In the normal state, the input coefficient is output as it is, and in the event of an abnormality in which an accident detection signal is output from the system accident detection device 24, the weight addition coefficient one cycle before is output as it is, or a predetermined value suitable for system abnormality is output. Output.

【0046】これによれば、系統事故発生による入力信
号の不均衡に起因し、重み加算係数が異常値となること
を防止し、安定なPSS動作を確保できる。なお、第二
の実施例のリミッタに本実施例の切替機能を持たせるこ
とも可能である。
According to this, it is possible to prevent the weighted addition coefficient from becoming an abnormal value due to the imbalance of the input signal due to the occurrence of a system fault, and to secure a stable PSS operation. The limiter of the second embodiment can have the switching function of the present embodiment.

【0047】[0047]

【発明の効果】本発明によれば、系統の減衰率や周波数
動揺の状態測定を基に、有効電力と周波数の重み加算係
数ないしはその比率を動的に制御することにより、系統
の運転状態に適応し、動態安定度を向上できる効果があ
る。
According to the present invention, the active power and the frequency weighting addition coefficient or the ratio thereof are dynamically controlled based on the measurement of the system attenuation factor and the frequency fluctuation state, so that the operation state of the system can be changed. It has the effect of adapting and improving the dynamic stability.

【0048】本発明によれば、入力信号の異常ないしは
系統事故時に、重み加算係数の過大、急変を防止でき、
PSSの安定な動作を維持できる効果がある。
According to the present invention, it is possible to prevent the weight addition coefficient from becoming excessive or abrupt when an input signal abnormality or a system failure occurs,
There is an effect that a stable operation of the PSS can be maintained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の電力系統安定化装置(PSS)の一実
施例を示す構成図。
FIG. 1 is a configuration diagram showing an embodiment of a power system stabilizer (PSS) of the present invention.

【図2】従来の電力系統安定化装置の構成図。FIG. 2 is a configuration diagram of a conventional power system stabilization device.

【図3】本実施例の状態推定器と重み加算係数算出回路
の構成図。
FIG. 3 is a configuration diagram of a state estimator and a weight addition coefficient calculation circuit of the present embodiment.

【図4】有効電力変化分(電力動揺)の時間的変化と減
衰率を示す波形図。
FIG. 4 is a waveform chart showing a temporal change and an attenuation rate of an active power change (power fluctuation).

【図5】励磁系(AVR−Gen系)の構成を一機無限
大母線系としてモデル化した等価回路図。
FIG. 5 is an equivalent circuit diagram in which the configuration of the excitation system (AVR-Gen system) is modeled as a single-machine infinite bus system.

【図6】内部誘起電圧Eq’を説明するベクトル図。FIG. 6 is a vector diagram illustrating an internal induced voltage Eq ′.

【図7】図5のモデルを線形近似化したブロック線図。FIG. 7 is a block diagram obtained by linearly approximating the model of FIG. 5;

【図8】有効電力調整信号と周波数調整信号から電力P
SS出力を求めるベクトル図。
FIG. 8 shows the power P from the active power adjustment signal and the frequency adjustment signal.
FIG. 4 is a vector diagram for obtaining an SS output.

【図9】振動状態同定装置の機能ブロック図。FIG. 9 is a functional block diagram of the vibration state identification device.

【図10】第二の実施例を示し、重み加算係数変化率リ
ミッタを付加した電力系統安定化装置の構成図。
FIG. 10 shows a second embodiment, and is a configuration diagram of a power system stabilizing device to which a weight addition coefficient change rate limiter is added.

【図11】第三の実施例を示し、系統事故検出による重
み加算係数切替回路を付加した電力系統安定化装置の構
成図。
FIG. 11 is a configuration diagram of a power system stabilizing apparatus according to a third embodiment, to which a weight addition coefficient switching circuit based on system fault detection is added.

【符号の説明】[Explanation of symbols]

1…同期発電機、2…励磁機、3…PT、4…CT、5
…有効電力検出装置、6…周波数検出装置、7…内部誘
起電圧検出回路、8…状態推定器(減衰率及び位相差検
出器)、9…重み加算係数算出回路、10…Pゲイン調
整回路、11…fゲイン調整回路、12…直流分除去回
路、17…PSS出力リミッタ、18…AVRの信号加
算回路、20,21,22…変化分検出回路、23…振
幅値検出回路、24…減衰率検出器、27…重み加算係
数加減器、28,29…位相検出器、30…位相補正ゲ
イン算出回路、31…位相補正ゲイン乗算回路、40,
41…重み加算係数変化率リミッタ、42,43…重み
加算係数切替回路、44…系統事故検出装置。
1: Synchronous generator, 2: Exciter, 3: PT, 4: CT, 5
... active power detection device, 6 ... frequency detection device, 7 ... internal induced voltage detection circuit, 8 ... state estimator (decay rate and phase difference detector), 9 ... weight addition coefficient calculation circuit, 10 ... P gain adjustment circuit, 11: f gain adjustment circuit, 12: DC component removal circuit, 17: PSS output limiter, 18: AVR signal addition circuit, 20, 21, 22 ... change detection circuit, 23 ... amplitude value detection circuit, 24 ... attenuation rate Detector, 27: Weight addition coefficient adder / subtractor, 28, 29: Phase detector, 30: Phase correction gain calculation circuit, 31: Phase correction gain multiplication circuit, 40,
41 ... weight addition coefficient change rate limiter, 42, 43 ... weight addition coefficient switching circuit, 44 ... system fault detection device.

フロントページの続き (56)参考文献 特開 平1−129800(JP,A) 特開 平1−308198(JP,A) 特開 平4−165999(JP,A) 特開 平5−122998(JP,A) 特開 昭61−280714(JP,A) 特開 昭59−73000(JP,A) 特開 昭60−139132(JP,A) (58)調査した分野(Int.Cl.7,DB名) H02J 3/24 H02P 9/14 Continuation of front page (56) References JP-A-1-129800 (JP, A) JP-A-1-308198 (JP, A) JP-A-4-165999 (JP, A) JP-A-5-122998 (JP) JP-A-61-280714 (JP, A) JP-A-59-73000 (JP, A) JP-A-60-139132 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB Name) H02J 3/24 H02P 9/14

Claims (11)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 同期発電機の有効電力と系統周波数に応
じてゲイン及び位相の補正を行い、さらに自動電圧調整
置を介して前記同期発電機の励磁装置を調整して、電
力系統を安定化する電力系統安定化装置において、 前記有効電力の変化分から電力動揺の減衰率を求め、該
減衰率に応じて有効電力ゲインを更新し、前記系統周波
数の変化分から前記自動電圧調整装置の遅れによる位相
差を求め、該位相差に応じて位相補正ゲインを更新し、
前記有効電力または有効電力の時間的変化分と前記有効
電力ゲインの乗算値と、前記系統周波数または系統周波
数の時間的変化分と前記位相補正ゲインの乗算値とのベ
クトル和を前記自動電圧調整装置の入力とすることを特
徴とする電力系統安定化装置による制御方法。
1. A corrects the gain and phase in response to the active power and system frequency of the synchronous generator, by adjusting the exciter of the synchronous generator and further through the automatic voltage regulator <br/> equipment, In a power system stabilizing device for stabilizing a power system, an attenuation rate of power fluctuation is obtained from a change amount of the active power, an active power gain is updated according to the attenuation rate, and the automatic voltage adjustment is performed from a change amount of the system frequency. Find the phase difference due to the delay of the device , update the phase correction gain according to the phase difference,
A multiplication value of the real power or a temporal change in the real power and the real power gain, and the system frequency or the system frequency;
A control method by a power system stabilizing device , wherein a vector sum of a temporal change in number and a multiplied value of the phase correction gain is input to the automatic voltage regulator .
【請求項2】 請求項1において、 前記有効電力ゲインの補正は、前記減衰率が基準減衰率
以下のとき、更新前のゲインに所定値を乗算または加算
することを特徴とする電力系統安定化装置による制御方
法。
2. The power system stabilization according to claim 1, wherein the correction of the active power gain is performed by multiplying or adding a predetermined value to the gain before updating when the attenuation rate is equal to or less than a reference attenuation rate. Control method by device.
【請求項3】 請求項1または2において、 前記位相補正ゲインの補正は、前記減衰率が基準減衰率
以下のとき、更新前のゲインに所定値を乗算または加算
し、かつ、前記自動電圧調整装置の遅れによる位相差が
その範囲に0を含む所定範囲を超えるとき、前記位相差
に応じて正または負に増大する値を加算することを特徴
とする電力系統安定化装置による制御方法。
3. The correction of the phase correction gain according to claim 1, wherein, when the attenuation rate is equal to or less than a reference attenuation rate, the gain before updating is multiplied or added by a predetermined value, and the automatic voltage adjustment is performed. When the phase difference due to the delay of the device exceeds a predetermined range including 0 in the range, a value that increases positively or negatively according to the phase difference is added.
【請求項4】 請求項3において、 前記自動電圧調整装置の遅れによる位相差は、前記系統
周波数または前記同期発電機の回転数の位相と前記励磁
装置の内部誘起電圧の位相の差となることを特徴とする
電力系統安定化装置による制御方法。
4. The phase difference according to claim 3, wherein the phase difference due to the delay of the automatic voltage regulator is a difference between the system frequency or the phase of the rotation speed of the synchronous generator and the phase of the internal induced voltage of the excitation device. A control method using a power system stabilizing device characterized by the above-mentioned.
【請求項5】 同期発電機の有効電力と系統周波数に応
じてゲイン及び位相の補正を行い、さらに自動電圧調整
置を介して前記同期発電機の励磁装置を調整して、電
力系統を安定化する電力系統安定化装置において、 前記電力系統の有効電力及び周波数と、前記励磁装置の
内部誘起電圧とから状態推定した電力動揺の減衰率や周
波数変動を基に、90位相の異なる有効電力または有
効電力の時間的変化分に乗ずる有効電力ゲインと周波数
または周波数の時間的変化分に乗ずる位相補正ゲインの
比率を動的に変更して、前記周波数と前記内部誘起電圧
の位相が等しくなるように前記電力系統安定化装置の
力を決定することを特徴とする電力系統安定化装置によ
る制御方法。
5. corrects the gain and phase in response to the active power and system frequency of the synchronous generator, by adjusting the exciter of the synchronous generator and further through the automatic voltage regulator <br/> equipment, A power system stabilizing device for stabilizing a power system, comprising: a 90- degree phase based on a power fluctuation damping rate and a frequency variation estimated from a state based on an active power and a frequency of the power system and an internal induced voltage of the excitation device. Different active power or have
Active power gain and frequency multiplied by the temporal change of active power
Or by dynamically changing the temporal variation in Jozu that position phase correction gain ratio of the frequency, output of the power system stabilizer as phase equals the internal induced voltage and the frequency <br/> A control method by a power system stabilizing device, characterized by determining a force.
【請求項6】 請求項1、2、3、4または5におい
て、 前記有効電力ゲイン及び位相補正ゲインは、所定の制限
値の範囲で更新されることを特徴とする電力系統安定化
装置による制御方法。
6. The method according to claim 1, wherein the active power gain and the phase correction gain are set to predetermined limits.
A control method by a power system stabilizing device, wherein the control method is updated within a value range .
【請求項7】 請求項6において、 前記所定の制限値は、前記有効電力ゲインおよび/また
は位相補正ゲインの最大値または最大変化率を規定する
ことを特徴とする電力系統安定化装置による制御方法。
7. The control method according to claim 6, wherein the predetermined limit value defines a maximum value or a maximum change rate of the active power gain and / or the phase correction gain. .
【請求項8】 系統に電力を出力する同期発電機の励磁
装置を調整する自動電圧調整装置の励磁系に設けられ、
前記同期発電機の有効電力と系統周波数に応じてゲイン
及び位相の補正を行って電力系統を安定化する電力系統
安定化装置において、 系統から有効電力と周波数を検出する有効電力手段及び
周波数検出手段と、前記励磁装置の内部誘起電圧を求め
る内部誘起電圧検出手段と、 検出した有効電力に有効電力ゲインを乗算する有効電力
調整手段及び検出した周波数に位相補正ゲインを乗算す
る周波数ゲイン調整手段と、前記有効電力調整手段と前
記周波数ゲイン調整手段の出力を加算する加算手段及び
その出力の変化分を検出して前記自動電圧調整装置に出
力する直流分除去手段と、 前記有効電力の変化分から電力動揺の減衰率と、前記系
統周波数の変化分と前記内部誘起電圧の変化分から前記
自動電圧調整装置の遅れによる位相差を求める状態推定
手段と、 前記減衰率に応じて前記有効電力ゲインを、前記減衰率
及び前記位相差に応じて前記位相補正ゲインを更新する
重み加算係数算出手段と、 を備えることを特徴とする電力系統安定化装置。
8. provided excitation system of the automatic voltage regulator for adjusting the exciter of the synchronous generator to output power to the grid,
In a power system stabilizing device for stabilizing a power system by performing gain and phase correction according to the active power and system frequency of the synchronous generator, active power means and frequency detecting means for detecting active power and frequency from the system Internal induced voltage detecting means for obtaining an internal induced voltage of the excitation device, active power adjusting means for multiplying the detected active power by an active power gain, and frequency gain adjusting means for multiplying the detected frequency by a phase correction gain, An adding means for adding outputs of the active power adjusting means and the frequency gain adjusting means, and a DC component removing means for detecting a change in the output and outputting the detected output to the automatic voltage adjusting device; and a power fluctuation from the active power change. The attenuation rate, the change in the system frequency and the change in the internal induced voltage,
State estimating means for obtaining a phase difference due to a delay of the automatic voltage adjusting device ; and weight addition coefficient calculating means for updating the active power gain according to the attenuation rate and the phase correction gain according to the attenuation rate and the phase difference. A power system stabilizing device, comprising:
【請求項9】 請求項8において、 前記重み加算係数算出手段は、前記有効電力ゲイン及び
前記位相補正ゲインに所定の制限を行うリミッタを設け
ることを特徴とする電力系統安定化装置。
9. The power system stabilizing device according to claim 8, wherein the weighting addition coefficient calculating means includes a limiter for performing a predetermined limit on the active power gain and the phase correction gain.
【請求項10】 請求項9において、 前記リミッタは、系統事故発生後の各相の信号が不均衡
となっている期間、前記有効電力ゲイン及び前記位相補
正ゲインの更新を行わないことを特徴とする電力系統安
定化装置。
10. The method according to claim 9, wherein the limiter does not update the active power gain and the phase correction gain during a period when a signal of each phase is imbalanced after the occurrence of a system fault. Power system stabilizer.
【請求項11】 請求項8、9または10において、 前記状態推定手段は、前記有効電力の時系列信号を入力
して前記減衰率を同定する振動状態同定手段を有するこ
とを特徴とする電力系統安定化装置。
11. The electric power system according to claim 8, 9 or 10, wherein the state estimating means includes a vibration state identifying means for inputting the time series signal of the active power and identifying the damping rate. Stabilizer.
JP31313294A 1994-12-16 1994-12-16 Power system stabilizer and control method using the same Expired - Fee Related JP3234729B2 (en)

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