JP3231467B2 - Information recording medium with built-in CPU - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information recording medium having a built-in CPU, and more particularly to an information recording medium having a built-in CPU for executing a predetermined task corresponding to each of a plurality of externally applied instruction codes.

[0002]

2. Description of the Related Art As a new information recording medium replacing a magnetic card, an IC card has attracted attention. In particular, CPU
An IC card with a built-in is expected to be used in various fields because of its high security. Generally I
The C card has three types such as RAM, ROM, and EEPROM.
There are various types of memories, all of which are accessed by the built-in CPU. The transfer of data to and from the IC card is performed by a reader / writer device. When a predetermined instruction code is given from the reader / writer device to the IC card, the instruction code is decoded by the CPU in the IC card, and a predetermined job corresponding to the instruction code is executed. For example, in the case of a data write command, data given from the reader / writer device to the IC card is written in the memory in the IC card, and in the case of a data read command, data read from the memory in the IC card is used. Is transferred to the reader / writer device.

[0003] In general, dozens of types of instructions given to IC cards are prepared. For example, even for the same write command, a command for writing data in record units and a command for writing binary data are different commands. An instruction to lock / unlock a file, an instruction to define a new file, an instruction to delete a file, an instruction to verify a key, an instruction to execute a self-diagnosis routine, In fact, various commands are used to perform various tasks. These instructions are
Each instruction code is transmitted from the reader / writer device to the IC card in the form of a unique instruction code. CPU in IC card
Executes a predetermined routine in the ROM based on the given instruction code.

[0004]

As described above, there are usually several tens of instructions given to an IC card, and a separate processing routine is prepared for each of these instructions in the ROM. However, a portable information recording medium such as an IC card has a limited memory capacity due to the necessity of miniaturization, and it is preferable that the programs prepared in the ROM be as small as possible.

An object of the present invention is to provide an information recording medium having a built-in CPU capable of further reducing the size of a program for executing an externally applied instruction.

[0006]

SUMMARY OF THE INVENTION (1) the first invention is an information recording medium with a built-in CPU for executing predetermined work corresponding to each of a plurality of instruction codes given from the outside, in each work To perform common common processing
Common processing program and separate specific processing for each job
And a unique processing program for performing
And a memory for program storage that stores Te, a plurality of instructions code
For each code, start with a consecutive number in the order of frequency of use.
Instruction number table that associates the instruction numbers
Specific processing program to be branched to for each issue
The address and associating address table, from the outside
When given instruction code is given, instruction number table
By referencing files in order of frequency of use
Prepare the instruction number to execute and temporarily store this instruction number.
After executing the processing, the common processing program and the specific processing program
Have the function of executing the programs in a predetermined order.
When executing the processing program with
By referring to the address corresponding to the stored instruction number.
Address, and execute a unique processing program at this address.
Providing a processing execution section which has a function of executing selectively, the
It is like that.

(2) The second invention of the present application is a processing method for an information recording medium having a built-in CPU according to the first invention.
The execution unit may perform an increment process on the instruction number or
Is stored in the address table each time the decrement process is performed.
For moving a pointer pointing to one address of
And increment or decrement
Pointed by the pointer when the result of
Select the specific processing program at the indicated address destination
Is executed.

[0008]

[0009]

[0010]

[Operation] In general, a processing routine for some instructions has a part for performing common processing. In the present invention, the common processing part is extracted as a common processing routine, and the common processing routine is commonly used for executing a plurality of instructions. Therefore, the total program capacity can be reduced. In addition, when executing a processing routine specific to each instruction, branching is performed for each instruction in order of use frequency.
Define a specific instruction number and refer to this instruction number.
, The branching can be performed efficiently.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the illustrated embodiments. FIG. 1 is a block diagram showing a state where a general IC card 10 is connected to a reader / writer device 20. IC
In the card 10, an I / O device 11 for connecting to a reader / writer device 20, a CPU 12, a RAM 13,
The ROM 14 and the EEPROM 15 are built in. The CPU 12 receives a command given from the reader / writer device 20 via the I / O device 11, and executes the command. Of the three types of memory, the RAM 13 is a volatile memory and is used as a work area of the CPU 12. The ROM 14 and the EEPROM 15 are both non-volatile memories. The ROM 14 is read-only, while the EEPROM can be rewritten at any time. Therefore, a program to be executed by the CPU 12 is prepared in the ROM 14, and user data is recorded in the EEPROM 15 for each file.

FIG. 2 shows that when a predetermined command is given from the reader / writer device 20 to the IC card 10,
9 is a flowchart showing a procedure of a conventional processing method inside the card 10. First, in step S1, a command is input to the IC card 10. As previously mentioned,
This instruction is given to the CPU 12 as a predetermined instruction code (for example, a one-byte code). CP
U12 branches to a processing routine for performing the work corresponding to the instruction code in step S2. Then, in step S3, any one of the branch destinations
Two routines are executed. In the example shown in FIG.
Six types of routines are prepared for executing the types of instructions, but actually, separate routines are prepared in the ROM 14 for more instructions. As described above, when one independent routine is prepared for each instruction, a considerable capacity in the ROM 14 is occupied for storing these routines.

The present invention focuses on the fact that a plurality of routines generally include common processing contents, and a common processing routine is prepared for this common processing part. For example, consider a case where the six routines 1 to 6 shown in FIG. 2 each include five processes as shown in FIG. Then, processing A1 to A6
Since the processes have almost the same contents, they can be grouped as a common process A. Similarly, the processes C1 to C6 can be grouped as a common process C, and the processes E1 to E6 can also be grouped as a common process E. The ideal case is considered as a model. Normally, the six routines 1 to 6 are created separately and independently, so that, for example, the six processes A1 to A6 rarely completely match as program descriptions. However, these processes
If the processes are intended to have almost the same contents, six processes A1
It is possible to describe a common process A that can be generally used for .about.A6. The program capacity for the common process A may be larger than the program capacity for one process A1, but is considered to be smaller than the total program capacity of the six processes A1 to A6. Therefore, common processes A, C, and E are prepared, and the processes A1 to A6 are respectively performed.
If used instead of processes C1 to C6 and processes E1 to E6,
The overall program capacity can be reduced.

FIG . 4 is a graph showing the relationship between I and I based on the above-described concept.
5 is a flowchart showing a procedure of a specific processing method performed in the C card 10. First, in step S10, the IC
An instruction is input to the card 10. The IC card 10 executes the common process A in step S11, regardless of the input command being any of the six commands. When the common processing A is completed, a branch is performed in a succeeding step S12. Depending on whether the input instruction is one of the six instructions, the process branches to one of the six specific processes. Thus, in step S13, any one of the six unique processes B1 to B6 is executed. After the common process C is performed in the subsequent step S14, a branch is performed in step S15. That is, in step S16, any one of the six unique processes D1 to D6 is executed. And finally, step S
At 17, common processing E is performed. By performing such a procedure, a process equivalent to the process shown in FIG. 3 is performed for any instruction.

By the way, in step S12 in FIG.
As shown in S15, when shifting from common processing to each unique processing, it is necessary to branch. In the present invention, this branching is efficiently performed by the following method. First, an instruction number table as shown in FIG. 5 and an address table as shown in FIG. 6 are prepared in the ROM 14. The instruction number table is a table that associates instruction numbers (one-byte codes) of six instructions with instruction numbers consisting of consecutive numbers “1 to 6”. In the example shown in FIG. 5, for example, the instruction code “A6” is associated with the instruction number “1”.
On the other hand, the address table is a table for associating each instruction number with a start address of a unique process to be a branch destination. For example, if the six instruction codes “A6”, “B4”,..., “2A” shown in the table of FIG.
As shown in the table of FIG. 6, in the address table, the head address values of the unique processes B1 to B6 are recorded corresponding to the instruction numbers 1 to 6, respectively.
It is sufficient to record only the address value as an actual address table, and it is not necessary to record the instruction number itself. The table shown in FIG. 6 relates to the branch in step S12, and a similar address table in which the head address values of the unique processes D1 to D6 are recorded also for the branch in step S15.

By preparing such an instruction number table and address table, the following efficient branch processing can be performed. Here, the instruction code “E
This branching process will be described by taking a case where "2" is given as an example. First, in step S10, when an instruction is input, the CPU 12 sets the given instruction code “E
The instruction number corresponding to "2" is recognized by searching the instruction number table shown in FIG. In this example, the instruction code “E
The instruction number "3" corresponding to "2" is obtained. This instruction number “3” is temporarily written in a predetermined area of the RAM 13. Subsequently, after the common processing A in step S11 is performed, the branch processing in step S12 is performed. First, FIG.
The first column of the address table shown in FIG.
After a predetermined pointer is pointed to by a predetermined pointer, the R
The instruction number “3” temporarily written in the AM 13 is loaded into a predetermined register (or another area of the RAM 13). Then, the content of this register is decremented, and it is determined whether or not it becomes "0".
If the value is "0", the head address value of the unique processing recorded in the address table column pointed to by the pointer at that time is read, and the routine jumps from this head address. If it is not "0", move the pointer to the next column (move from the first column to the second column),
The contents of the register are decremented again, and it is determined whether or not the value has become "0". By repeating such processing, it is possible to branch to a proper unique processing routine when the register becomes “0”. In the above example, since the initial value of the register is "3", the register becomes "0" when the pointer moves to the third column (the position indicated by the address Add3 in the figure), and the process proceeds to the unique process B3. Will be branched. The process of decrementing the contents of a register and the process of determining whether or not the contents of a register are “0” are performed by a general CP.
Since this is a basic process provided by U12, it can be executed extremely efficiently.

Instead of using the address table, at the end of the routine of the common processing A, a program as shown in FIG. 7 (the CPU 12 executes a load instruction for a specific register, an increment instruction (INC), and a comparison instruction (CM
P), a program assuming that it has a function to execute a jump instruction (JMP) based on the comparison result)
May be added. First, in a step, the instruction number "3" temporarily written in the RAM 13 is loaded into the register R0. Then, in a step, the initial value “0” is loaded into the register R1. In the step, the contents of the register R1 are incremented, and in the step, the contents of both registers are compared. If the contents of the two registers match, in a step, the process jumps to the start address of the unique processing B1. If they do not match, step R1
Is incremented, and the contents of both registers are compared in a step. If they match, in a step, the process jumps to the start address of the unique process B2. If not, the contents of the register R1 are incremented in a step. Hereinafter, similarly, the steps of incrementing the register R1, comparing the two registers, and jumping if they match, may be repeated. Since the process of incrementing the contents of the registers and the process of comparing and judging the registers are basic processes provided in a general CPU 12,
Such branch processing can also be executed extremely efficiently.

In order to further improve the efficiency of the above-described branch processing, it is preferable to assign instruction numbers to the instruction codes in the order of use frequency in the instruction number table shown in FIG. In the example of FIG. 5, the instruction code “A6” is the instruction that is used most frequently, and the instruction codes “B4”, “E2”, “58”, “85”, “2”
It is only necessary to continue in the order of "A". In the branch processing using the decrement processing or the increment processing described above, as the instruction number is smaller, the number of times of decrement or increment is reduced, and the processing time is shortened. Therefore, if instruction numbers are assigned in order of use frequency, the more frequently used instructions are used, the shorter the processing time required for branching and the more efficient the instructions.

Although the present invention has been described based on the illustrated embodiment, the present invention is not limited to this embodiment, but can be implemented in various other modes. For example, the above-described embodiment is an example in which the present invention is applied to an IC card, but the present invention is widely applicable to an information recording medium having a built-in CPU. The example shown in FIG.
Although each of the two routines is an ideal model having common processes A, C, and E, in practice, for example, routines 1 and 2 share process A, and routines 2 and 3 share process C. It seems that common parts are often mixed and complicated among multiple routines. Even in such a case, for some routines having a common processing part, the part may be unified as a common processing. In short, the basic idea of the present invention lies in that when there is a part where the processing is common between a plurality of routines, this is put together as a common processing routine. You can go.

[0020]

As described above, according to the information recording medium of the present invention, the common processing routine for a plurality of instructions is commonly used, so that the total program capacity can be reduced. In addition, since instruction numbers are assigned to the instruction codes in order of use frequency, the time for referring to the instruction number table when executing instructions is reduced, and the processing can be speeded up.

[Brief description of the drawings]

FIG. 1 shows a general IC card 10 connected to a reader / writer 2
It is a block diagram showing the state connected to 0.

FIG. 2 is a diagram showing an example in which a predetermined command is given from the reader / writer device 20 to the IC card 10 shown in FIG.
0 is a flow chart showing the procedure of a conventional processing method inside 0.

FIG. 3 is a diagram showing an example of a model of processing contents of each routine shown in FIG. 2;

FIG. 4 is a diagram showing an example in which a predetermined command is given from the reader / writer device 20 to the IC card 10 shown in FIG.
0 is a flowchart showing the procedure of the processing method of the present invention inside 0.

FIG. 5 is a diagram showing an example of an instruction number table used for branching in the processing shown in FIG. 4;

FIG. 6 is a diagram illustrating an example of an address table used for branching in the processing illustrated in FIG. 4;

FIG. 7 is a diagram showing an example of a program routine used for branching in the processing shown in FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... IC card 11 ... I / O device 12 ... CPU 13 ... RAM 14 ... ROM 15 ... EEPROM 20 ... Reader / writer device

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-77820 (JP, A) JP-A-61-204737 (JP, A) JP-A-2-28766 (JP, A) JP-A-5-204 108568 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06K 19/07 G06F 9/06 410 G06F 15/00 310

Claims (2)

(57) [Claims] 1. A common processing program for performing common processing common to each task on an information recording medium incorporating a CPU for executing a predetermined task corresponding to each of a plurality of instruction codes given from outside.
Ram and unique to perform separate unique processing for each job
Processing programs and programs that store
RAM storage memory and multiple instruction codes, each successive in frequency of use
Instruction number table that associates instruction numbers consisting of
For each instruction number, the specific processing
An address table for associating program addresses, and when a predetermined instruction code is given from outside, the instruction
Refer to the order number table in descending order of frequency of use.
And obtain the corresponding instruction number, and temporarily store this instruction number.
After executing the preparatory processing for storing, the common processing program is executed.
And the specific processing program are executed in a predetermined order.
Having a function and executing the unique processing program
In this case, by referring to the address table,
Find the address corresponding to the stored instruction number, and
Function to selectively execute the destination specific processing program
Information recording medium which incorporates a processing execution section, a CPU, characterized in that it comprises a having
body. 2. The information recording medium according to claim 1, wherein the processing execution unit performs an increment process on the instruction number.
Or every time the decrement process is performed, the address table
Move pointer pointing to one address in file
Perform the above processing, and perform the increment processing or decrement
When the result of the print processing reaches a predetermined value, the pointer
Specific processing program of the address destination pointed to by
Built-in CPU characterized by selectively executing RAM
Information recording medium.