JP3231026B2 - Image playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an image reproducing device equipped with a data decoding processing circuit, equipped with data decoding processing circuit, in particular having a function of determining the validity of the decoded data
And an image reproducing apparatus .

[0002]

2. Description of the Related Art In recent years, it has become possible to acquire a high-quality still image by using a digital video device represented by a DSC (digital still camera). Compressed data (JPE) acquired by this digital video device
A system for extracting and reproducing an image of a specified area from the G data) will be described with reference to FIG. FIG.
In FIG. 4, a printer 900 and a computer 9000 are shown as systems for extracting and printing out an image of a designated area from the compressed data.

[0003] As shown in FIG.
Reference numeral 000 denotes a control device 9002 including a memory for storing compressed data (JPEG data), a decoding circuit for decoding compressed data, and an application for image processing, and a display device 9 for displaying image data output from the decoding circuit.
004 and an input device 9006. The compressed data is decrypted by the computer 9000 and then transferred to the printer.

FIG. 1 shows a process for printing out an image within a specified range using the above-described conventional system.
5 will be described. First, in step S90,
JPEG data which is compressed data is stored in
It is taken into 0. Next, in step S91, JP
The EG data is decoded, and all images are displayed on the display device 9004 using an application. In step S92, the user specifies a range to be cut out (extracted) using the input device 9006 while checking the displayed image. In step S93, clipped image data is created. In step S94, the extracted image data is transferred from the computer 9000 to the printer 900. As a result, in step S95, the image of the designated area is printed out by the printer.

[0005]

However, the amount of data tends to increase with the improvement of image quality. For this reason, according to the conventional method, there is a problem that as the size of an image to be taken out increases, the data transfer time for transferring data to the printer 900 increases, and it takes time to reproduce. Further, if a process of extracting image data of a required area after performing the decoding process, it takes time until the image data is transferred to the printer.

Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to provide a data decoding circuit capable of extracting required data at high speed.

[0007]

SUMMARY OF THE INVENTION Image reproduction according to the present invention
The device receives an encoded signal from the outside and plays it back.
A data decoding processing circuit for receiving compressed data obtained by encoding an image and information indicating a designated area from the outside, and decoding the data .
To play the image corresponding to the specified area based on the output
A data decoding processing circuit, comprising:
Decodes the compressed data received from the outside, and a decoding processing circuit for outputting decoded data, based on the specified region, whether decoded data for each of the decoded data is output from the decoding processing circuit belongs to the designated area determine the, and a determination processing circuit for outputting a discrimination result corresponding to the decoded data.

[0008] Preferably, the designated area is an image size, and the decoding processing circuit counts each time decoding data corresponding to each pixel constituting the image is decoded, and a decoding circuit for decoding the compressed data. A determination processing circuit configured to determine whether or not the decoded data is included in the image size according to the image size stored in the register and the count value output from the counter; And a determination circuit for performing the determination.

Preferably, the image size is 1 / n of the image
(Where n is a power of 2), and the register stores a plurality of bit strings and shifts the stored bit strings according to the image size.

[0010] Preferably, the image is composed of a plurality of blocks, the designated area is an image size in block units, and the decoding processing circuit comprises: a decoding circuit for decoding compressed data; And a counter that counts each time the compressed data corresponding to the block is decoded in units of blocks. The discrimination processing circuit includes a register that stores the image size in units of blocks, and an image size and counter in units of blocks that are stored in the registers. A determination circuit for determining whether or not the decoded data is included in the image size according to the output count value.

Preferably, the image includes data relating to a luminance component and data relating to a chrominance component arranged in a predetermined order, and the designated area is a luminance component, and the decoding processing circuit decodes the compressed data. A decoding circuit that includes a counter that counts each time compressed data corresponding to each pixel constituting an image is decoded, the discrimination processing circuit stores information indicating that only the luminance component is to be reproduced, A determination circuit for determining whether or not the decoded data corresponds to a luminance component according to the information stored in the register and the count value output by the counter.

Preferably, the decoding processing circuit includes a detection circuit for detecting a marker code included in the compressed data, the register further stores a thinning code included in the detected marker code, and the determination circuit includes: It is further determined whether or not the decoded data is to be thinned out by the thinning code.

When the determination processing circuit receives all the decoded data included in the designated area from the decoding processing circuit, it stops the decoding operation in the decoding processing circuit.

[0014]

Embodiments of the present invention will be described in detail with reference to the drawings. Note that the same components are denoted by the same reference numerals or the same symbols, and description thereof will be omitted.

[First Embodiment] A data decoding circuit according to a first embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1, a data decoding processing circuit 10 according to the first embodiment of the present invention is mounted on a printer 100. The printer 100 displays a control device 2 including a memory for storing compressed data (JPEG data), a decoding circuit for decoding compressed data, and an application for image processing, and image data output from the decoding circuit. Computer 1 including display device 4 and input device 6
000. The user inputs information on the image area (designated area) to be printed out from the input device 6. Information about the designated area input by the user is transmitted to the printer 100.

The printer 100 includes a data decryption processing circuit 1
0 and a printout processing circuit 12. The data decoding processing circuit 10 receives the compressed data and the information on the designated area from the computer 1000, and outputs decoded data and a decoded data valid signal indicating the validity of each decoded data. The printout processing circuit 12 reproduces (prints out) an image in the designated area based on the decoded data and a decoded data valid signal indicating the validity of each decoded data.

Referring to FIG. 2, the flow of the printout processing according to the first embodiment of the present invention will be described. First, in step S1, JPEG data as image data is taken into the control device 2 of the computer 1000.

In step S2, the JPEG data is decoded, and all the decoded images are displayed on the display device 4 using the application.

In step S3, the user inputs a designated area using the input device 6 while checking the displayed image data.

In step S 4, the JPEG data itself and information on the designated area are transmitted to the printer 100.

In step S5, the JPEG data is decoded. At this time, the validity of the required data is determined. Then, in step S6, the image of the designated area is printed out.

That is, the printer 100 receives compressed data having a small data amount from the computer 1000, decodes the data, and determines the validity of the data (whether the data is to be printed out or not) simultaneously with the decoding. The data validated by the result of the determination is printed out.

Next, the data decoding processing circuit 10 will be described with reference to FIG. As shown in FIG. 3, the data decoding processing circuit 10 includes a marker processing unit 20 and a decoding circuit 2.
2, data counter 24, designated area storage register 2
6 and a determination circuit 28.

The marker processing section 20 detects a marker code inserted in the compressed data. In particular,
As shown in FIG. 4, an SOI marker (code “FFD8”) indicating the start of an image, and a D defining a quantization table
A QT marker (code “FFDB”) and a DRI marker (code “FFD”) defining a restart interval
D "), a SOFO marker (reference code" FFC0 ") indicating a basic function DCT, a DHT defining a Huffman table
Marker (code “FFC4”), SOS marker (code “FFDA”) indicating the start of scanning, RST marker (code “FFD0” to “FFD”) indicating restart
7 "), an EOI marker indicating the end of the image (reference code" FF ")
D9 "), etc. By the above-mentioned" FFC0 ",
The image size of the original image is determined.

Referring to FIG. 3, decoding circuit 22 performs a decoding process on the compressed data according to the detected marker code. The data counter 24 counts up each time data of one pixel is expanded. The data counter 2
4 shares a counter for counting the compressed data used at the time of compression. As a counting method, the decoding circuit 2
There is a method of counting up using the pixel data valid signal output from 2.

The designated area storage register 26 stores information about the designated area. In addition, as a method of designating the designated area, there are a method of designating the start point and end point of the area, a method of designating the X size, a method of designating the Y size, and the like.

If the designated area deviates from the image size detected by the marker processing unit 20, for example, if it is larger than the image size of the original image, the image size of the original image is stored. The effective area to be printed out is determined by the value stored in the designated area storage register 26.

The discrimination circuit 28 includes a designated area storage register 2
According to the value stored in No. 6, valid / invalid of the decoded data output from the decoding circuit 22 is determined, and a decoded data valid signal is output as a result of the determination. Specifically, by comparing the count value with the valid area, it is determined that the decoded data entering the valid area is valid, and the other data is invalid. The above-described printout processing circuit 12 receives the decoded data and the decoded data valid signal from the determination circuit 28, and prints out the decoded data validated by the decoded data valid signal.

It should be noted that the determination circuit 28 determines when the decoding data contained in the effective area is completely output.
Is completed. After all of the decoded data included in the valid area is output, the decoded data valid signal becomes invalid.

As described above, the data decoding processing circuit according to the first embodiment makes it possible to extract the designated data together with the decoding processing. In addition, when the data decoding processing circuit is mounted on a printer, compressed data is transmitted from the computer side, so that the data transfer time is reduced as compared with the conventional method, and it is possible to print out at high speed. Become.

[Second Embodiment] A data decoding circuit according to a second embodiment of the present invention will be described with reference to FIG. As shown in FIG. 5, the data decoding processing circuit 30 according to the second embodiment of the present invention is included in the printer 200, and removes the compressed data and the chrominance components Cr and Cv from the luminance component Y.
And a mode designation for designating reproduction only (gray scale) from the computer 1000.

By specifying the mode, it is specified whether to reproduce (print out) the luminance component and the chrominance component or to reproduce only the luminance component from the compressed data having the luminance component Y and the chrominance components Cr and Cv. You. The user operates the input device 6
Enter the mode designation using. Information on the mode designation is stored in the computer 100 using the input device 6 described above.
0, and transmitted to the printer 200.

The printer 200 includes a data decryption processing circuit 3
0 and a printout processing circuit 12. The data decoding processing circuit 30 receives the compressed data and the information on the mode designation from the computer 1000, and outputs the decoded data and a decoded data valid signal indicating the validity of each decoded data. The printout processing circuit 12 prints out an image based on the decoded data and a decoded data valid signal indicating the validity of each decoded data.

That is, the printer is connected to the computer 10
The compressed data having a small data amount is received from 00 and decoded, and at the same time as decoding, the validity of the decoded data (whether the data is to be printed out or not) is determined, and a gray scale image is printed based on the determination result. Out.

Next, the data decoding circuit 30 will be described with reference to FIG. As shown in FIG. 6, the data decoding processing circuit 30 includes a marker processing unit 20 and a decoding circuit 2.
2, the data counter 24, and the mode designation register 32
And a determination circuit 28.

The marker processing section 20 outputs the image size of the original image and the thinning mode to the mode designation register 32. The thinning mode is defined for the SOFO marker corresponding to the Y component.

Here, the relationship between the image data and the thinning mode will be described with reference to an example. Image size 16 × 16
The image data is composed of a block array composed of blocks 0 to 3 as shown in FIG. The image data of each block has a Y component, a Cr component, and a Cv component, and is arranged according to the arrangement of Y, Cr, and Cb as shown in FIG. 7B. The subscripts added to Y, Cr, and Cv in the figure correspond to block numbers (for example, block 0 is represented by Y0, Cr0, and Cv0). The number described in each block indicates the order of data.

As shown in FIG. 7C, when the thinning mode is (4: 4: 4), all the color components (Y
0, Cr0, Cv0, Y1, Cr1, Cv1, Y2, C
r2, Cv2, Y3, Cr3, Cv3), if the thinning mode is (4: 2: 2), the color components other than the Cr and Cv components of block 0 and block 2 are set to (4: 2 : 0), the Cr, C of blocks 1 to 3
Reproduction is performed so as to include the color components other than the v component. If the gray scale is defined, the data stream is composed of only the Y component.

As shown in FIG. 8A, the image data having an image size of 32.times.8 is composed of a block array composed of blocks 0 to 3. The image data of each block has a Y component, a Cr component, and a Cv component.
As shown in (b), they are arranged in the order of Y, Cr, Cb.

As shown in FIG. 8C, if the thinning mode is (4: 4: 4), all the color components (Y
0, Cr0, Cv0, Y1, Cr1, Cv1, Y2, C
r2, Cv2, Y3, Cr3, Cv3), if the thinning mode is (4: 1: 1), the Cr,
Reproduction is performed so as to include the color components other than the Cv component.

Referring to FIG. 6, mode designation register 32
Stores information about the gray scale and information about the thinning mode. A component corresponding to the gray scale and the thinning mode is determined by the value stored in the mode designation register 32.

The decoding circuit 22 decodes both a luminance component and a chrominance component. The data counter 24 counts up each time data of one pixel is decoded.

The discriminating circuit 28 stores the values (information on the thinning mode and gray level) stored in the mode designation register.
In accordance with the scale information), the validity / invalidity of the decoded data output from the decoding circuit 22 is determined, and a decoded data valid signal is output as a result of the determination. Specifically, valid / invalid is determined according to the count value, and a decoded data valid signal is generated. When the user specifies a gray scale, data other than the luminance component Y is invalidated. Also, based on the count value and the information on the thinning mode, data thinned out in the thinning mode is invalid,
Otherwise, it is determined to be valid.

The above-described printout processing circuit 12
The decoded data and the decoded data valid signal are received from the determination circuit 28, and the decoded data validated by the decoded data valid signal is printed out.

The discrimination circuit 28 determines that the original image is gray.
When the scale is the scale, the output of the decoding circuit 22 is output as it is.

As described above, the data decoding processing circuit according to the second embodiment makes it possible to extract data corresponding to the designated gray scale together with the decoding processing. It is also possible to extract data corresponding to the thinning mode. In addition, when the data decoding processing circuit is mounted on a printer, compressed data is transmitted from the computer side, so that the data transfer time is reduced as compared with the conventional method, and it is possible to print out at high speed. Become.

By combining the data decoding processing circuit 10 according to the first embodiment with the data decoding processing circuit 30 according to the second embodiment of the present invention, an image in a range specified by the user is printed out by grace scale. It is possible to do.

[Third Embodiment] A data decoding processing circuit according to a third embodiment of the present invention will be described with reference to FIG. As shown in FIG. 9, a data decoding processing circuit 40 according to the third embodiment of the present invention is included in a printer 300, and includes information on compressed data and an image area (designated area block) in a block unit to be printed out. Is received from the computer 1000.

The user can designate to print out an image having a size of a multiple of a block unit with respect to the original image. The user uses the input device 6 to input information about the designated area block. Information on the designated area block is stored in the computer 100 using the input device 6 described above.
0, and transmitted to the printer 300.

The printer 300 includes a data decryption processing circuit 4
0 and a printout processing circuit 12. The data decoding processing circuit 40 receives the compressed data and the information on the designated area block from the computer 1000, and outputs decoded data and a decoded data valid signal indicating the validity of each decoded data. The printout processing circuit 12 prints out the image of the designated area block based on the decoded data and a decoded data valid signal indicating the validity of each decoded data.

That is, the printer 300 receives the compressed data having a small data amount from the computer 1000, decodes the data, and determines the validity of the decoded data (whether or not the data is to be printed out) at the same time as decoding. The data validated by the result of the determination is printed out.

Next, the data decoding processing circuit 40 will be described with reference to FIG. As shown in FIG. 10, the data decoding processing circuit 40 includes a marker processing unit 20, a decoding circuit 22, a data counter 44, a designated area storage register 42, and a determination circuit 28.

The data counter 44 counts up in block units. As the counting method, a method of counting up using the pixel data valid signal output from the decoding circuit 22 as described above, or a method of counting the number of DC signals using the DC signal and the AC signal output from the decoding circuit 22 is used. There is a counting method and the like. Marker processing unit 20
Outputs the image size of the original image and the thinning mode to the designated area storage register 42.

The designated area storage register 42 stores information on a designated area block. In this case, a multiple of the block size (8 × 8) is stored. If the designated area block deviates from the image size detected by the marker processing unit 20, for example, if it is larger than the image size of the original image, the image size of the original image is stored. The designated area storage register 42 further stores information on the thinning mode output from the marker processing unit 20.

That is, the effective area to be printed out is determined by the value stored in the designated area storage register 42, and the component corresponding to the thinning mode is determined.

The discriminating circuit 28 stores the designated area storage register 4
2, the validity / invalidity of the decoded data output from the decoding circuit 22 is determined, and a decoded data valid signal is output as a result of the determination. Specifically, by comparing the count value with the valid area, it is determined that the decoded data entering the valid area is valid and the rest is invalid, and based on the count value and the information on the thinning mode, It is determined that the data to be thinned out is invalid, and that the other data is valid.

The above-described printout processing circuit 12
The decoded data and the decoded data valid signal are received from the determination circuit 28, and the decoded data validated by the decoded data valid signal is printed out.

The discrimination circuit 28 terminates the decoding process in the decoding circuit 22 when the decoded data included in the valid area is output.

As described above, with the data decoding processing circuit according to the third embodiment, it is possible to easily extract the data of the designated block unit together with the decoding processing. It is also possible to extract data corresponding to the thinning mode. In addition, when the data decoding processing circuit is mounted on a printer, compressed data is transmitted from the computer side, so that the data transfer time is reduced as compared with the conventional method, and it is possible to print out at high speed. Become.

[Fourth Embodiment] A data decoding processing circuit according to a fourth embodiment of the present invention will be described with reference to FIG. As shown in FIG. 11, a data decoding processing circuit 50 according to the fourth embodiment of the present invention is included in a printer 400, and stores compressed data and information on an image area (1 / n designation) to be printed out. 1000
Receive from

The user can designate to extract and print out an image of 1 / n (where n is a power of 2) of the original image. The user uses the input device 6 to make 1 / n
Enter information about the specification. The information on the 1 / n designation is input to the computer 1000 using the input device 6 described above.
And transmitted to the printer 400.

The printer 400 includes a data decryption processing circuit 5
0 and a printout processing circuit 12. The data decoding processing circuit 50 receives the compressed data and the information on the 1 / n designation from the computer 1000, and outputs the decoded data and a decoded data valid signal indicating the validity of each decoded data. The printout processing circuit 12 prints out the image of the designated area block based on the decoded data and a decoded data valid signal indicating the validity of each decoded data.

That is, the printer 400 receives the compressed data having a small data amount from the computer 1000, decodes the data, and simultaneously determines the validity of the decoded data (whether or not the data is to be printed out). The data validated by the result of the determination is printed out.

Next, the data decoding processing circuit 50 will be described with reference to FIG. As shown in FIG. 12, the data decoding processing circuit 50 includes a marker processing unit 20, a decoding circuit 22, a data counter 24, a designated area storage register 52, and a determination circuit 28.

The marker processing section 20 outputs the image size of the original image and information on the thinning mode to the designated area storage register 52. The designated area storage register 52 is
Stores information on n designation.

1 for the X direction of the image composed of the XY plane
An example of / n designation is shown. As shown in FIG. 13, for example, the size of the original image is X = 1024 pixels and Y = 480.
Pixels. In the case of 1/1 (original image size), it is assumed that the tenth bit (from the LSB side) of the designated area storage register 52 is “1”. On the other hand, in the case of 1/2 designation,
“1” is shifted by one bit to the LSB side (the ninth bit). The image size is 512. In the case of 1/4 designation, "1" is shifted to the LSB side by 2 bits (eighth bit). The image size is 256. In the case of 1/8 designation, "1" is shifted by 3 bits (the seventh bit) to the LSB side. The image size is 128. It should be noted that 1 / n is designated in the Y direction in the same procedure by a bit string (not shown). At this time, the size of the 1 / n area is
It is assumed that the size is smaller than the image size of the original image detected by the marker processing unit 20.

The designated area storage register 52 further stores information on the thinning mode output from the marker processing section 20. That is, the effective area to be printed out is determined by the value stored in the designated area storage register 52, and the component corresponding to the thinning mode is determined.

The discriminating circuit 28 stores the designated area storage register 5
2, the validity / invalidity of the decoded data output from the decoding circuit 22 is determined, and a decoded data valid signal is output as a result of the determination. Specifically, by comparing the count value with the valid area, it is determined that the decoded data entering the valid area is valid and the rest is invalid, and based on the count value and the information on the thinning mode, It is determined that the data to be thinned out is invalid, and that the other data is valid.

The printout processing circuit 12 described above
The decoded data and the decoded data valid signal are received from the determination circuit 28, and the decoded data validated by the decoded data valid signal is printed out.

The discrimination circuit 28 terminates the decoding process in the decoding circuit 22 when the decoded data included in the valid area is output.

As described above, the data decoding processing circuit according to the fourth embodiment makes it possible to easily extract 1 / n (n is a power of 2) data of the specified original image together with the decoding processing. It is also possible to extract data corresponding to the thinning mode. In addition, when the data decoding processing circuit is mounted on a printer, compressed data is transmitted from the computer side, so that the data transfer time is reduced as compared with the conventional method, and it is possible to print out at high speed. Become.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0073]

As described above, according to the image reproducing apparatus equipped with the data decoding processing circuit according to the present invention, while decoding the compressed data received from the outside, whether the decoded data belongs to the designated area to be inputted in advance . It is possible to determine whether or not . This makes it possible to reproduce the data in the designated area (data determined to be valid) at high speed.

Therefore, when the data decoding circuit is mounted on a printer, the printer receives the compressed data, and extracts the image data to be printed out while decoding the data, thereby realizing high-speed printout. It becomes possible.

In particular, it is possible to easily extract data corresponding to an image size and components corresponding to a gray scale in response to a user input. As a result, an arbitrary image can be reproduced from the original image.

Further, since the decoding process is stopped after extracting valid data, a higher-speed reproduction process is realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a relationship between a data decoding processing circuit 10 and a computer 1000 according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a flow of a printout process according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a data decoding processing circuit 10 according to the first embodiment of the present invention.

FIG. 4 is a diagram for explaining a marker code.

FIG. 5 is a diagram showing a relationship between a data decoding processing circuit 30 and a computer 1000 according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a data decoding processing circuit 30 according to a second embodiment of the present invention.

FIGS. 7A to 7C are diagrams for explaining the relationship between image data and a thinning mode with an example;

FIGS. 8A to 8C are diagrams for explaining the relationship between image data and a thinning mode with an example;

FIG. 9 is a diagram showing a relationship between a data decoding processing circuit 40 and a computer 1000 according to a third embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a data decoding processing circuit 40 according to a third embodiment of the present invention.

FIG. 11 is a diagram showing a relationship between a data decoding processing circuit 50 and a computer 1000 according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a data decoding processing circuit 50 according to a fourth embodiment of the present invention.

FIG. 13 is a diagram for describing a designated area storage register 52;

FIG. 14 is a diagram for describing a conventional system for extracting an image of a designated area from compressed data and printing out the image.

FIG. 15 is a flowchart illustrating a flow of a process for printing out an image within a designated range using a conventional system.

[Explanation of symbols]

 Reference Signs List 2 control device 4 display device 6 input device 10, 30, 40, 50 data decoding processing circuit 12 printout processing circuit 20 marker processing section 22 decoding circuit 24, 44 data counter 28 discriminating circuit 26, 42, 52 designated area storage register 32 Mode designation register 100-400 Printer 1000 Computer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ identification symbol FI H04N 11/04 H04N 7/13 Z (58) Investigated field (Int.Cl. ⁷ , DB name) H04N 1/41-1 / 419 H04N 1/38 H03M 7/30 H04N 5/91 H04N 7/24 H04N 11/04

Claims (7)

(57) [Claims] An image receiving apparatus receives an encoded signal from outside.
An image reproducing apparatus for reproducing, which shows a specified area and compressed data obtained by encoding an image.
A data decoding circuit for decoding by receiving information from the outside, based on the output of the data decoding processing circuit, the designated territory
Image reproduction processing means for reproducing an image corresponding to the area
Wherein the data decoding processing circuit decodes the compressed data received from the outside, and a decoding processing circuit for outputting decoded data, based on the designated area, each time the decoded data from the decoding circuit is outputted the decoded data to determine whether or not belonging to the designated area, and a determination processing circuit for outputting a discrimination result corresponding to the decoded data to the image
Playback device . 2. The image processing apparatus according to claim 1, wherein the designated area is an image size, the decoding processing circuit includes: a decoding circuit that decodes the compressed data; and a decoding circuit that decodes the compressed data corresponding to each pixel constituting the image. A register that stores the image size, and the decoded data is stored in the image according to the image size stored in the register and the count value output by the counter. The image reproducing apparatus according to claim 1, further comprising: a determination circuit configured to determine whether the image is included in the size. 3. The image size is 1 / n (where n is a power of 2) of the image, and the register stores a plurality of bit strings, and stores the stored bit strings according to the image size. 3. The image according to claim 2, wherein the image is shifted.
Image reproduction device . 4. The image is composed of a plurality of blocks, the designated area is an image size of the block unit, the decoding processing circuit is a decoding circuit for decoding the compressed data, The compressed data corresponding to each pixel constituting
A counter that counts each time decoding is performed on a block-by-block basis with eight pixels as one block; the discrimination processing circuit includes: a register that stores the image size of the block; The image reproducing apparatus according to claim 1, further comprising: a determination circuit that determines whether or not the decoded data is included in the image size according to a size and a count value output by the counter. 5. The image includes data relating to a luminance component and data relating to a chrominance component, which are arranged in a predetermined order, wherein the designated area is the luminance component, and the decoding processing circuit comprises: A decoding circuit that decodes the compressed data; and a counter that counts each time compressed data corresponding to each pixel constituting the image is decoded. The discrimination processing circuit indicates that only the luminance component is reproduced. A register for storing information, and a determination circuit for determining whether or not the decoded data corresponds to the luminance component according to the information stored in the register and a count value output by the counter. Item 2. The image reproducing device according to Item 1. 6. The decoding processing circuit includes a detection circuit that detects a marker code included in the compressed data, the register further stores a thinning code included in the detected marker code, The image reproducing device according to claim 2, wherein the determination circuit further determines whether the decoded data is a target to be decimated by the decimating code. 7. The image reproducing apparatus according to claim 1, wherein the determination processing circuit stops the decoding operation in the decoding processing circuit when receiving all of the decoding data included in the designated area from the decoding processing circuit. .