JP3230483B2 - Method for testing life of gate insulating film in semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a gate insulating film in a semiconductor device, and more particularly to a method for testing the life of a gate insulating film having an extremely thin film thickness through which a direct tunnel current flows.

[0002]

2. Description of the Related Art Most LSIs (Large Scale Integrated Circuits) represented by memory products, logic products and the like are constituted by MOS (Metal Oxide Semiconductor) transistors which are excellent in integration degree. As described above, in a MOS LSI in which the transistor is integrated (hereinafter simply referred to as LSI), the size of the transistor is further reduced as the performance thereof is improved. The thickness of the constituent gate insulating film tends to become thinner, and recently several tens of
There is a demand for a thickness of on-crystal. As described above, when the thickness of the gate insulating film is reduced, the gate insulating film is easily broken down, which affects the reliability of the LSI.

For this reason, when an LSI is shipped as a product, a life test is performed on a gate insulating film in advance to predict the life of the gate insulating film, thereby assuring quality to the user. Such a life test is based on TDDB (T
In this method, a voltage is applied to the gate insulating film through the gate electrode, and the time until the dielectric breakdown occurs, that is, the lifetime is predicted. When a voltage is continuously applied to the gate insulating film, a leak current starts to flow as time elapses, and after a certain time elapses, the leak current increases to cause dielectric breakdown of the gate insulating film.

FIG. 6 shows a MOS structure in which a polycrystalline Si film serving as a gate electrode as a metal M, an oxide film (SiO 2 film) serving as a gate insulating film as an oxide O, and an S film as a semiconductor S
The energy band when an i-substrate is used is described. Ef is a Fermi level of a polycrystalline Si film and a Si substrate,
Φb indicates the barrier height, and Ge indicates the energy gap of the oxide film.

The barrier height Φb is represented by the height between the Fermi level Ef of the polycrystalline Si film and the left shoulder of the diamond-shaped energy gap Ge of the same oxide film. The value of the barrier height Φb is determined by the combination of the gate insulating film material and the semiconductor material, and is approximately 3.1 eV (electron volt) in the case of the combination of the oxide film and the Si substrate as described above. Here, the gradient θ of the energy gap Ge of the oxide film changes according to the electric field Eox based on the voltage Vox applied to the oxide film. As the Eox increases, θ decreases.

Here, the voltage Vox applied to the oxide film is expressed by the following equation. Vox = Vg−Vfb (1) where Vg: gate voltage Vfb: flat band voltage As is apparent from the equation (1), the voltage Vox applied to the oxide film serving as the gate insulating film is the gate voltage applied to the gate electrode. The value is lower than Vg by the flat band voltage Vfb.

Here, as shown in FIG. 7, the conventional gate insulating film life test method uses the above-described oxide film applied voltage Vox.
At the barrier height Φb or higher and the operating voltage of the same transistor (the gate voltage during operation is 1.2 to 1.3).
(V)) Vo is selected more than Vo. In the figure, Vox
1, Vox2, Vox3, Vox4,... Indicate the values of the individual oxide film applied voltages Vox, and the solid line L is a line connecting the life values obtained corresponding to the respective values of Vox. By extending the solid line L linearly as indicated by a broken line M, the life of the gate insulating film at the operating voltage Vo is predicted (prediction point P). The reason why the oxide film applied voltage Vox is selected to a value equal to or higher than the barrier height Φb is to perform a so-called acceleration test and predict the life as short as possible.

When the thickness of the gate insulating film becomes as thin as about several tens of angstroms, for example, between about 5 angstroms and less than 40 angstroms, depending on the value of the oxide film applied voltage Vox across the barrier height Φb, the gate insulating film becomes A phenomenon occurs that the leakage current mechanism in the film is different. That is, when Vox> Φb, FN (Fowlo
(R Nordheim) current flows, while DT (Direct Tunnel) current flows when Vox ≦ Φb.

FIGS. 9 and 10 show these phenomena in energy bands. FIG. 9 shows the former example, and FIG. 10 shows the latter example. In the former example, the Ge jumps in from the gate electrode Ef, which is the starting point of the electron.
Is located at a lower position (lower energy), while in the latter example, the right shoulder is at a higher position (higher energy) than Ef.

For example, Japanese Patent Application Laid-Open No. 9-283750 discloses a method for testing the life of an extremely thin gate insulating film. This publication discloses a method of performing TDDB measurement on a gate insulating film having a thickness of, for example, 50 angstroms.

[0011]

However, the method for testing the life of a gate insulating film described in the above publication is based on the value of the oxide film applied voltage Vox at the barrier height Φb.
Since the phenomenon that the leakage current mechanism is different is not taken into account, there is a problem that the life prediction in the region where the DT current flows in the case of Vox ≦ Φb becomes erroneous. That is, as shown in FIG. 8, due to the difference in the leakage current mechanism between the FN current and the DT current, the former has a property that the voltage dependence is larger than the latter.
Therefore, as shown in FIG. 7, it is difficult to predict the life of the gate insulating film at the operating voltage Vo by linearly extending the solid line L as indicated by the broken line M. As a result, the service life is estimated to be shorter than the actual one. In general, the larger the value of the barrier height Φb, the easier the DT current flows through the thin gate insulating film.

The present invention has been made in view of the above circumstances, and provides a semiconductor insulating film capable of accurately predicting the life of an extremely thin gate insulating film through which a direct tunnel current flows. It is an object of the present invention to provide a method for testing the life of a gate insulating film in the above.

[0013]

According to a first aspect of the present invention, a gate electrode is provided on an extremely thin gate insulating film formed on a surface of a semiconductor substrate, and the gate electrode is provided on the gate electrode. According to a method for testing the life of the gate insulating film in a semiconductor device in which a direct tunnel current flows when a voltage is applied, the gate voltage is set to Vg, and the energy barrier height determined by a combination of the semiconductor substrate and the gate insulating film is determined. Φb, the voltage applied to the gate insulating film is Vox, and the operating voltage of the semiconductor device is Vo, and the gate voltage Vg is selected so as to satisfy the condition of Vo ≦ Vox ≦ Φb.

According to a second aspect of the present invention, there is provided a method for testing the life of a gate insulating film in a semiconductor device according to the first aspect, wherein the thickness of the gate insulating film is 5 Å or more.
It is characterized by being less than 0 angstroms.

According to a third aspect of the present invention, there is provided a method for testing the life of a gate insulating film in a semiconductor device according to the first or second aspect, wherein the semiconductor substrate is made of silicon and the gate insulating film is made of silicon oxide. It is characterized by being made of a film.

[0016] The invention according to claim 4 is based on claim 1,
4. A method for testing the life of a gate insulating film in a semiconductor device according to item 2 or 3,
The method is characterized in that the semiconductor substrate is heated at a temperature of 40 ° C. or more and 250 ° C. or less.

According to a fifth aspect of the present invention, there is provided a method for testing the life of a gate insulating film in a semiconductor device according to any one of the first to fourth aspects. While keeping the substrate temperature constant,
The method is characterized in that the above-mentioned operation is performed by changing the gate voltage.

According to a sixth aspect of the present invention, there is provided a method for testing the life of a gate insulating film in a semiconductor device according to any one of the first to fourth aspects. The method is characterized in that the temperature is varied while maintaining the voltage constant.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. First Embodiment FIG. 1 is an electrical connection diagram showing a method for testing the life of a gate insulating film according to a first embodiment of the present invention. In this example, the same life test method is applied to a gate oxide film 2 having a thickness of about 20 angstroms.
Is provided in the gate oxide film 2 under the condition that the temperature t of the Si substrate 1 is held at approximately 150 ° C. by being housed in the heating chamber 6 using the P-type Si substrate 1 formed on the surface. The test apparatus 4 was connected so that a negative gate voltage Vg was applied to the gate electrode 3 made of the polycrystalline Si film. The same life test method was repeated using a plurality of the same Si substrates 1 for different gate voltages Vg.

The thickness of the gate oxide film 2 is larger than that of the gate oxide film 2 by 1.0 to 1.5 μ
m field oxide films 5 are formed. This field oxide film 5 functions as an oxide film for element isolation of the LSI.
Further, the polycrystalline Si film forming the gate electrode 3 is made N-type by previously doping an N-type impurity by an ion implantation method or the like.

FIG. 2 is a characteristic diagram showing a life test result of the same gate oxide film 2 obtained by the life test method of this embodiment. The gate voltage Vg (horizontal axis) and the 50% breakdown time (vertical axis)
The relationship is shown. Here, the 50% destruction time is
When a predetermined gate voltage Vg is applied to a plurality of Si substrates to be tested, the half of the Si substrates 1 is estimated to be in a state where dielectric breakdown is predicted.

As can be seen from the figure, the characteristic changes between the line L1 having a small gradient and the line 2 having a large gradient at a gate voltage Vg of about -3.7 (V). Here, the flat band voltage Vfb is approximately -0.6 (V).
Therefore, the value of Vox is given by using equation (1). Vox = Vg−Vfb = (− 3.7) − (− 0.6) = − 3.1 (1)

That is, the value of the oxide film applied voltage Vox obtained by the equation (1) becomes 3.1 (V) in absolute value, and is determined by the combination of the Si substrate 1 and the gate oxide film 2. Is substantially equal to the value of the barrier height Φb of 3.1 (eV). Therefore, the characteristics in FIG.
This indicates that the ratio of time to dielectric breakdown is larger in the region where the DT current flows than in the region where the FN current flows, with respect to b at 3.1 (V). This makes it possible to estimate the actual life as compared with the conventional method. That is, the life can be accurately estimated by performing the life test while selecting the gate voltage Vg so as to include the condition of Vox ≦ Φb. This is because the life test is performed by selecting the above-described conditions and using the same leakage current mechanism as the actual operation of the LSI.

FIG. 3 is a characteristic diagram showing another life test result of the same gate oxide film 2 obtained by the life test method of this embodiment, and shows the relationship between the breakdown time (horizontal axis) and the cumulative failure rate (vertical axis). Shows the relationship. Here, the analogous defective rate indicates a rate at which a plurality of Si substrates 1 that have been tested for each Vg undergo dielectric breakdown at regular intervals and the defective rates are accumulated.

As is apparent from FIG.
Are -3.7 (V), -3.5 (V), and -3.3, respectively.
The five characteristics selected as (V), -3.25 (V), and -3.2 (V) indicate that the smaller the Vg value, that is, the higher the oxide film applied voltage Vox is the barrier height Φb value of 3.1.
(EV) indicates that the smaller the value is, the longer the failure time is to be accumulated.

The reason for setting the life test temperature higher than the normal temperature is to perform an accelerated test. The higher this temperature is set, the higher the test efficiency becomes. However, the temperature condition is set so as not to affect the components of the LSI, which is limited by the melting point of the solder used as the brazing material, and is selected to be approximately 250 ° C. or less. When the temperature is selected to be 150 ° C. or higher, the characteristics of FIG. 2 move substantially parallel upward, and conversely, when the temperature is selected to be 150 ° C. or lower, the characteristics of FIG. To move.

As described above, according to the configuration of this example, the gate voltage Vg is set so that the voltage Vox applied to the gate oxide film ≦ the barrier height Φb by the combination of the oxide film and the Si substrate.
Since the life test of the gate insulating film is performed by selecting so as to include the following condition, the life test can be performed with the same leakage current mechanism as the actual operation of the LSI. Therefore, the lifetime can be accurately predicted for a gate insulating film having an extremely thin film thickness through which a direct tunnel current flows.

Second Embodiment The configuration of the same life test method of the second embodiment is the same as that of the first embodiment described above.
The difference from the embodiment is that the gate voltage Vg is kept constant in the substantially same electrical connection diagram as FIG.
The point is that the temperature t is made variable. That is, the gate oxide film 2 having a thickness of about 20 angstroms is formed, the gate voltage Vg is maintained at −3.7 (V), and the temperature t is set to 40.
The life test was performed by varying the temperature in the range of 150 to 150 ° C.

FIG. 4 is a characteristic diagram showing life test results obtained by the same life test method, and shows the relationship between temperature (horizontal axis) and 50% destruction time (vertical axis). In the figure, by setting the gate voltage Vg = −3.7 (V), V
The characteristics in a group where ox is selected as Φb = 3.1 (eV) are shown. As can be seen from the figure, it can be seen that the 50% destruction time changes depending on the temperature t, and the destruction time becomes shorter as the temperature t increases. This is because the degree of acceleration of the test increases as the temperature t increases.

FIG. 5 is a characteristic diagram showing another life test result obtained by the life test method of this example, and shows the relationship between the destruction time (horizontal axis) and the cumulative failure rate (vertical axis). As is clear from FIG.
Five characteristics selected at ° C, 100 ° C, 70 ° C, and 40 ° C indicate that the lower the temperature t value, the more failures accumulate over a longer destruction time. When the gate voltage Vg is selected to be -3.7 (V) or higher, the characteristics shown in FIG. 4 move substantially parallel upward, and conversely, when the gate voltage Vg is selected to be -3.7 (V) or lower. As a result, the characteristic shown in FIG. 4 moves substantially parallel downward.

As described above, according to the structure of this embodiment, the same life test is performed by selecting the gate voltage Vg so as to include the condition of Vox ≦ Φb. Substantially the same effect can be obtained.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and the design may be changed without departing from the scope of the present invention. Is also included in the present invention. For example, a combination of a gate insulating film and a semiconductor substrate is an oxide film (Oxide Fi
lm) and Si, as well as nitride films (Nitride F
ilm) and Si (barrier height Φb: ~ 2e)
V), a combination of a tantalum oxide film (Ta ₂ O ₅ ) and Si (barrier height φb: 1 to 1.5 eV) can be selected. Alternatively, MIS (Metal Insulator Semiconduct
or) as long as the transistor is a MNOS (Metal Nitride-
Oxide Semiconductor) transistors.

The conductivity type of the semiconductor substrate may be reversed between N type and P type. In this case, the polarity of the gate voltage applied to the gate electrode is also reversed. Further, the life test on the gate insulating film may be performed after forming the source region and the drain region. Further, in the above-described embodiment, the thickness of the gate oxide film is set to approximately 20 angstroms. However, the present invention is not limited to this, and the same effect as in the above-described embodiment can be obtained if the thickness is in the range of 5 angstroms to 40 angstroms. Can be.

[0034]

As described above, according to the gate insulating film life testing method of the present invention, the gate insulating film Vg is
Since the life test of the gate insulating film is performed by selecting so as to include the condition that the voltage Vox applied to the gate insulating film ≦ the barrier height Φb, the life test is performed by making the leakage current mechanism the same as the actual operation of the LSI. It can be carried out. Therefore, the lifetime can be accurately predicted for a gate insulating film having an extremely thin film thickness through which a direct tunnel current flows.

[Brief description of the drawings]

FIG. 1 is an electrical connection diagram showing a life test method of a gate insulating film according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing a life test result obtained by the life test method, showing a relationship between a gate voltage and a 50% breakdown time.

FIG. 3 is a characteristic diagram showing another life test result obtained by the same life test method, and showing a relationship between a destruction time and a cumulative failure rate.

FIG. 4 shows a life test result obtained by the same life test method according to the second embodiment of the present invention.
It is a characteristic view which shows the relationship with% destruction time.

FIG. 5 is a characteristic diagram showing another life test result obtained by the same life test method and showing a relationship between a destruction time and a cumulative failure rate.

FIG. 6 is a diagram illustrating an energy band in a MOS structure.

FIG. 7 is a characteristic diagram illustrating a relationship between a voltage and a gate insulating film life time for explaining a conventional gate insulating film life testing method.

FIG. 8 is a characteristic diagram for explaining voltage dependency of an FN current and a DT current in a MOS structure.

FIG. 9 is a characteristic diagram for explaining an energy band in which an FN current flows in a MOS structure.

FIG. 10 is a characteristic diagram for explaining an energy band in which a DT current flows in a MOS structure.

[Explanation of symbols]

 Reference Signs List 1 P-type Si substrate 2 Gate oxide film 3 Gate electrode 4 Test device 5 Field oxide film 6 Heating chamber Φb Barrier height Vox Voltage applied to gate insulating film Vg Voltage applied to gate electrode

Claims (6)

(57) [Claims] 1. A lifetime of a gate insulating film in a semiconductor device in which a gate electrode is provided on an extremely thin gate insulating film formed on a surface of a semiconductor substrate, and a direct tunnel current flows when a gate voltage is applied to the gate electrode. A test method, wherein the gate voltage is Vg, the energy barrier height determined by the combination of the semiconductor substrate and the gate insulating film is Φb, and the voltage applied to the gate insulating film is Vo.
x, wherein the operating voltage of the semiconductor device is Vo, and the gate voltage Vg is selected so as to satisfy the condition of Vo ≦ Vox ≦ Φb. 2. The method according to claim 1, wherein the thickness of the gate insulating film is not less than 5 angstroms and not more than 40 angstroms. 3. The method according to claim 1, wherein the semiconductor substrate is made of silicon, and the gate insulating film is made of a silicon oxide film. 4. The semiconductor device according to claim 1, wherein the method for testing the life of the gate insulating film is performed at a temperature of the semiconductor substrate of 40 ° C. or more and 250 ° C. or less. Test method of gate insulating film in Japan. 5. The method according to claim 1, wherein the method of testing the life of the gate insulating film is performed by varying the gate voltage while keeping the temperature of the semiconductor substrate constant. Test method for a gate insulating film in a semiconductor device of the present invention. 6. The method according to claim 1, wherein the method of testing the life of the gate insulating film is performed by changing the temperature of the semiconductor substrate while keeping the gate voltage constant. Test method for a gate insulating film in a semiconductor device of the present invention.