JP3229750B2 - Polycrystalline semiconductor film, semiconductor device and solar cell using the same - Google Patents
Polycrystalline semiconductor film, semiconductor device and solar cell using the sameInfo
- Publication number
- JP3229750B2 JP3229750B2 JP11817394A JP11817394A JP3229750B2 JP 3229750 B2 JP3229750 B2 JP 3229750B2 JP 11817394 A JP11817394 A JP 11817394A JP 11817394 A JP11817394 A JP 11817394A JP 3229750 B2 JP3229750 B2 JP 3229750B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor film
- substrate
- grain boundary
- polycrystalline semiconductor
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 190
- 239000013078 crystal Substances 0.000 claims description 105
- 239000000758 substrate Substances 0.000 claims description 90
- 238000000034 method Methods 0.000 claims description 32
- 239000010408 film Substances 0.000 description 226
- 229910021417 amorphous silicon Inorganic materials 0.000 description 27
- 239000010409 thin film Substances 0.000 description 22
- 238000006243 chemical reaction Methods 0.000 description 15
- 239000007789 gas Substances 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 11
- 238000004544 sputter deposition Methods 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 230000002411 adverse Effects 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 230000001678 irradiating effect Effects 0.000 description 6
- 230000006798 recombination Effects 0.000 description 6
- 238000005215 recombination Methods 0.000 description 6
- 239000007790 solid phase Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229910052715 tantalum Inorganic materials 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000010248 power generation Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000007858 starting material Substances 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000010979 ruby Substances 0.000 description 1
- 229910001750 ruby Inorganic materials 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- -1 specifically Substances 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/546—Polycrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Recrystallisation Techniques (AREA)
- Micromachines (AREA)
- Thin Film Transistor (AREA)
- Photovoltaic Devices (AREA)
Description
【0001】[0001]
【産業上の利用分野】この発明は、多結晶半導体膜、こ
の多結晶半導体膜を光電変換層に用いた太陽電池、上記
多結晶半導体膜をチャネル層に用いた薄膜トランジスタ
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline semiconductor film, a solar cell using the polycrystalline semiconductor film as a photoelectric conversion layer, and a thin film transistor using the polycrystalline semiconductor film as a channel layer.
【0002】[0002]
【従来の技術】近年、液晶ディスプレイや密着型イメー
ジセンサ等の駆動素子として、薄膜トランジスタが広く
用いられている。この薄膜トランジスタにおいてキャリ
ア走行路を司る活性層として使用されているのが薄膜半
導体である。2. Description of the Related Art In recent years, thin film transistors have been widely used as driving elements for liquid crystal displays, contact image sensors, and the like. In this thin film transistor, a thin film semiconductor is used as an active layer for controlling a carrier traveling path.
【0003】この薄膜半導体は、従来の単結晶からなる
半導体とは異なり、ガラスや石英等の絶縁性基板上にも
形成できるという特徴を備えると共に、比較的大面積の
基板上にも形成できることから、これまでの単結晶半導
体では困難なデバイスへの応用が可能とされている。[0003] Unlike a conventional single-crystal semiconductor, this thin-film semiconductor has a feature that it can be formed on an insulating substrate such as glass or quartz, and can be formed on a relatively large-area substrate. However, it has been possible to apply to devices that are difficult with conventional single crystal semiconductors.
【0004】このような薄膜半導体としては、従来非晶
質シリコン膜に代表されるような非晶質半導体が主に利
用されていたが、そもそも非晶質半導体膜は物性からく
る問題として半導体中のキャリア移動度が小さいため
に、その応用範囲は限られていた。Conventionally, an amorphous semiconductor typified by an amorphous silicon film has been mainly used as such a thin-film semiconductor. However, an amorphous semiconductor film has a problem in terms of physical properties. Because of its low carrier mobility, its application range was limited.
【0005】この移動度の問題は、例えば従来であれ
ば、非晶質半導体膜からなる薄膜トランジスタでは賄え
ない場合、駆動素子用として集積回路(IC)をこの支
持基板上にオンチップし、このICとその基板に形成さ
れた素子とをワイヤボンディングで接続する、といった
工程を必要としていた。[0005] This mobility problem cannot be solved by, for example, a conventional thin film transistor made of an amorphous semiconductor film, and an integrated circuit (IC) for a driving element is mounted on the support substrate on a chip. A step of connecting the IC and an element formed on the substrate by wire bonding has been required.
【0006】そこで、最近この非晶質半導体に替わる材
料として、特に注目を受け研究されているのが多結晶半
導体膜である。この多結晶半導体膜は、形成法の違いに
より種々のものがあるが、とりわけ低温で大面積形成が
可能な多結晶半導体膜の形成方法についての研究が活発
に進められている。Accordingly, a polycrystalline semiconductor film has recently been receiving attention and being studied as a material that can replace the amorphous semiconductor. There are various types of polycrystalline semiconductor films depending on the formation method. In particular, research on a method of forming a polycrystalline semiconductor film capable of forming a large area at a low temperature has been actively conducted.
【0007】この多結晶半導体膜は上記非晶質半導体膜
と比べて、キャリア移動度が3桁も大きく、上述したよ
うな工程を採用する必要もなく、支持基板上にあらゆる
素子を組み込むことが可能となり製造コストの削減等が
可能となる。This polycrystalline semiconductor film has a carrier mobility three orders of magnitude higher than that of the above-mentioned amorphous semiconductor film, so that it is not necessary to adopt the above-described steps, and it is possible to incorporate all elements on a supporting substrate. This makes it possible to reduce manufacturing costs and the like.
【0008】一方、太陽電池の分野においても薄膜多結
晶半導体を用いた太陽電池は、低コストで光電変換効率
を高くすることができるものとして期待されている。こ
の多結晶半導体膜からなる太陽電池では、多結晶半導体
膜内の結晶粒径の大型化と、膜内のキャリア移動度を向
上するための必須条件である。On the other hand, in the field of solar cells, a solar cell using a thin-film polycrystalline semiconductor is expected to be able to increase photoelectric conversion efficiency at low cost. In a solar cell made of this polycrystalline semiconductor film, it is an essential condition for increasing the crystal grain size in the polycrystalline semiconductor film and improving the carrier mobility in the film.
【0009】具体的な多結晶半導体膜の製造方法として
は、化学的気相成長法(CVD)により直接多結晶半導
体膜を形成する方法や、出発材料として非晶質半導体膜
を用い、これを600℃程度の温度領域で数十時間の熱
処理を施し多結晶化することで多結晶半導体膜を形成す
る、所謂固相成長法や、更には出発材料である非晶質半
導体膜にレーザ等のエネルギビームを照射することで、
局所的に溶融させ多結晶半導体膜を得る、レーザ再結晶
化法、等が提案されている。As a specific method of manufacturing a polycrystalline semiconductor film, a method of directly forming a polycrystalline semiconductor film by chemical vapor deposition (CVD), or a method using an amorphous semiconductor film as a starting material, A so-called solid phase growth method in which a polycrystalline semiconductor film is formed by performing a heat treatment for several tens of hours at a temperature range of about 600 ° C. to form a polycrystalline semiconductor film, and further, a laser or the like is applied to the amorphous semiconductor film as a starting material. By irradiating the energy beam,
A laser recrystallization method or the like in which a polycrystalline semiconductor film is locally melted to obtain a polycrystalline semiconductor film has been proposed.
【0010】一般に、この多結晶半導体膜の電気的特性
を大きく左右するものとして挙げられるのが結晶粒界で
ある。多結晶半導体膜は、通常、この結晶粒界で囲まれ
た多数個の結晶粒の集合からなるものであって、この結
晶粒界は、この半導体膜内でのキャリア走行を阻害する
ように作用する。このため斯る結晶粒界の生成を抑制す
るように多結晶半導体膜を形成することが重要となる。Generally, the crystal grain boundaries are ones that greatly affect the electrical characteristics of the polycrystalline semiconductor film. A polycrystalline semiconductor film usually consists of a set of a large number of crystal grains surrounded by the crystal grain boundaries, and the crystal grain boundaries act to hinder carrier traveling in the semiconductor film. I do. Therefore, it is important to form a polycrystalline semiconductor film so as to suppress generation of such crystal grain boundaries.
【0011】この点、上記各種製造方法の内でも、固相
成長法やレーザ再結晶化法によって形成された多結晶半
導体膜は、通常結晶粒が数μmの大きなものが得られる
ことから、結果として結晶粒界の数を低減することが可
能となり、良好な多結晶半導体膜を形成することができ
る。例えば、米国特許第5,221,365号公報に開
示されているように、表面に微少な凹凸形状を備えた基
板上に成膜された非晶質半導体膜を熱処理し、粒径の大
きい多結晶半導体膜を形成する方法がある。In this respect, among the above-mentioned various manufacturing methods, a polycrystalline semiconductor film formed by a solid phase growth method or a laser recrystallization method usually has a large crystal grain of several μm, and thus the result is large. As a result, the number of crystal grain boundaries can be reduced, and a favorable polycrystalline semiconductor film can be formed. For example, as disclosed in U.S. Pat. No. 5,221,365, an amorphous semiconductor film formed on a substrate having fine irregularities on its surface is subjected to a heat treatment so that a large-sized amorphous semiconductor film is formed. There is a method for forming a crystalline semiconductor film.
【0012】[0012]
【発明が解決しようとする課題】然し乍ら、上記多結晶
半導体膜の形成方法によれば、比較的大きな結晶粒が得
られるものの、この多結晶半導体膜の膜面内における上
記結晶粒界の位置を制御することはできない。即ち、形
成された多結晶半導体膜中の膜面内における結晶粒界
は、多結晶化の膜内での熱効率や熱伝導、あるいは使用
する基板の表面状態や核発生位置、結晶成長速度等の種
々の要因によってその位置は決定されてしまい、通常結
晶粒界の位置及びこれに付随して決定されることになる
結晶粒のサイズを制御することができない。However, according to the above-described method for forming a polycrystalline semiconductor film, although relatively large crystal grains can be obtained, the position of the crystal grain boundary in the film plane of the polycrystalline semiconductor film is determined. There is no control. That is, the crystal grain boundaries in the film plane in the formed polycrystalline semiconductor film are the heat efficiency and heat conduction in the polycrystallized film, or the surface state of the substrate used, the nucleation position, the crystal growth rate, etc. The position is determined by various factors, and it is not possible to control the position of the crystal grain boundary and the size of the crystal grain which is to be concomitantly determined.
【0013】このため、たとえば薄膜トランジスタのチ
ャネル領域となっている多結晶半導体膜中に結晶粒界が
存在したならばキャリアの走行が阻害されることにな
り、良好なスイッチング特性が得られないこととなって
しまう。For this reason, for example, if a crystal grain boundary exists in the polycrystalline semiconductor film serving as a channel region of the thin film transistor, the traveling of carriers is hindered, and good switching characteristics cannot be obtained. turn into.
【0014】また、太陽電池においても、発電に寄与し
ない結晶粒界がランダムに存在することにより、単位面
積当たりの発電効率が低下する。さらに、光キャリアが
結晶粒界で再結合し、光電変換特性に悪影響を及ぼすと
いう問題がある。[0014] Also in the solar cell, the generation efficiency per unit area is reduced due to the random existence of crystal grain boundaries that do not contribute to power generation. Further, there is a problem that the photocarriers are recombined at the crystal grain boundaries and adversely affect the photoelectric conversion characteristics.
【0015】そこで、本発明は、上記した問題点を解決
するためになされたものにして、本発明の第1の目的
は、膜面内における結晶粒界の位置を制御した多結晶半
導体膜及びその製造方法を提供することにある。Accordingly, the present invention has been made to solve the above-mentioned problems, and a first object of the present invention is to provide a polycrystalline semiconductor film in which the position of a crystal grain boundary in a film plane is controlled, and It is to provide a manufacturing method thereof.
【0016】本発明の第2の目的は、大きな粒径で、チ
ャネル領域となる多結晶半導体膜中に結晶粒界が存在せ
ずに、良好なスイッチング特性が得られる薄膜トランジ
スタを提供することにある。A second object of the present invention is to provide a thin film transistor having a large grain size and having good switching characteristics without the presence of crystal grain boundaries in a polycrystalline semiconductor film serving as a channel region. .
【0017】本発明の第3の目的は、大きな粒径を有す
る多結晶半導体膜を用い、発電に寄与しない粒界を制御
して集電効率を向上させる太陽電池を提供することにあ
る。A third object of the present invention is to provide a solar cell using a polycrystalline semiconductor film having a large grain size and controlling a grain boundary that does not contribute to power generation to improve current collection efficiency.
【0018】[0018]
【課題を解決するための手段】本発明の多結晶半導体膜
は、微小な平面を備えた隆起を多数個、表面に備えるこ
とで、隣接する該領域間の段差により上記表面を凹凸と
した基板上に、形成された多結晶半導体膜であって、該
多結晶半導体膜の膜面内における結晶粒界が、上記基板
の段差上に設けられていることにあり、また上記段差に
よる高低差が、30Å以上500Å以下としたことにあ
る。A polycrystalline semiconductor film according to the present invention is provided with a plurality of bumps having minute planes on a surface thereof, so that the surface is uneven due to a step between adjacent regions. A polycrystalline semiconductor film formed thereon, wherein a crystal grain boundary in a film plane of the polycrystalline semiconductor film is provided on a step of the substrate, and a height difference due to the step is reduced. , 30 ° or more and 500 ° or less.
【0019】[0019]
【0020】本発明の太陽電池は、表面に多数の凹凸を
設けて微小な平面を備えた領域を多数個備え、隣接する
該領域間に結晶粒界制御用の段差が設けられた第1電極
としての基板と、この基板上に基板表面の凹凸形状を反
映して位置制御された結晶粒界を含む一導電型の多結晶
半導体膜と、この多結晶半導体膜に形成された他導電型
の半導体層と、この半導体層上に形成された透明電極
と、を備え、上記多結晶半導体膜の膜内における結晶粒
界が、上記基板の段差上に設けられ、上記結晶粒界に位
置する透明電極上に集電極を設けている。The solar cell according to the present invention has a first electrode provided with a large number of regions having a fine flat surface with a large number of irregularities on the surface, and a step for controlling a grain boundary between adjacent regions. As a substrate, a polycrystalline semiconductor film of one conductivity type including a crystal grain boundary whose position is controlled by reflecting the uneven shape of the substrate surface on the substrate, and a polycrystalline semiconductor film of another conductivity type formed on the polycrystalline semiconductor film. A semiconductor layer, and a transparent electrode formed on the semiconductor layer, wherein a crystal grain boundary in the polycrystalline semiconductor film is provided on a step of the substrate, and a transparent crystal positioned at the crystal grain boundary is provided. A collecting electrode is provided on the electrode.
【0021】本発明の薄膜トランジスタは、表面に複数
の凹凸を設けて微小な平面を備えた領域を複数個備え、
隣接する該領域間に結晶粒界制御用の段差が設けられた
基板と、この基板上に基板表面の凹凸形状を反映して位
置制御された結晶粒界を含む多結晶半導体膜と、上記結
晶粒界に挟まれた領域をチャネル領域とし、そのチャネ
ル領域を挟んで形成されたソース、ドレイン領域と、か
らなり、上記多結晶半導体膜の膜内における結晶粒界
が、上記基板の段差上に設けられている。The thin film transistor according to the present invention comprises a plurality of regions having a fine flat surface provided with a plurality of irregularities on the surface,
A substrate provided with a step for controlling a grain boundary between adjacent regions, a polycrystalline semiconductor film including a grain boundary whose position is controlled on the substrate by reflecting the uneven shape of the substrate surface; the region between the grain boundaries as a channel region, a source formed across the channel region, a drain region, Tona is, the crystal grain boundary in the film of the polycrystalline semiconductor film
Are provided on the step of the substrate .
【0022】[0022]
【作用】本発明の多結晶半導体膜では、相隣接する、微
小な平面を備えた領域間の段差上に設けられた結晶粒界
によって囲まれた結晶粒内の、結晶の配向を特定方向に
揃えることも可能となり、半導体膜中の電気的特性を均
一なものとすることができることとなる。According to the polycrystalline semiconductor film of the present invention, the orientation of the crystal in a specific direction in a crystal grain surrounded by a crystal grain boundary provided on a step between adjacent regions having minute planes is adjusted. It is also possible to make them uniform, so that the electrical characteristics in the semiconductor film can be made uniform.
【0023】本発明の太陽電池によれば、基板の段差に
よって位置が特定されている結晶粒界が在る多結晶半導
体膜部分の表面に光キャリア収集のための集電極を設け
ることで、一般に光キャリアを再結合させ光電変換特性
に悪影響を及ぼすその結晶粒界近傍に集電極が設けら
れ、その様な再結合の発生を抑制することができる。According to the solar cell of the present invention, the collector electrode for collecting photocarriers is generally provided on the surface of the polycrystalline semiconductor film portion where the crystal grain boundary whose position is specified by the step of the substrate exists. A collecting electrode is provided in the vicinity of the crystal grain boundary that recombines the photocarriers and adversely affects the photoelectric conversion characteristics, so that occurrence of such recombination can be suppressed.
【0024】本願発明の多結晶半導体膜を薄膜トランジ
スタのチャンネル領域として用いれば、チャネル領域の
多結晶半導体膜部分には結晶粒界の存在しない状態を作
ることができ、これによれば、従来のような粒界による
キャリア走行の阻害がなくなり、スイッチング特性が良
好な素子得ることができる。When the polycrystalline semiconductor film of the present invention is used as a channel region of a thin film transistor, a state where no crystal grain boundary exists in the polycrystalline semiconductor film portion of the channel region can be formed. An element having good switching characteristics can be obtained without obstruction of carrier traveling due to a large grain boundary.
【0025】[0025]
【実施例】図1(A)ないし図1(D)は、本発明の多
結晶半導体膜を製造する方法を工程別に示す素子構造の
断面図である。図1(A)に示す第1工程では、SiN
XやSiO2が形成されたガラスや石英等からなる基板1
の表面に、任意の形状の微小な平面を備えた領域を多数
個形成すべく、従来周知のフォト・リソグラフィによる
レジスト2をパターニング形成する。1A to 1D are cross-sectional views of an element structure showing a method of manufacturing a polycrystalline semiconductor film according to the present invention for each step. In the first step shown in FIG.
Substrate 1 made of glass or quartz on which X or SiO 2 is formed
In order to form a large number of regions having minute planes of an arbitrary shape on the surface of the substrate, a resist 2 is formed by patterning using conventionally known photolithography.
【0026】次に図1(B)に示す第2工程では、レジ
スト2が形成された基板表面を、反応性イオンエッチン
グによりエッチングした後、レジスト2を除去する。こ
れにより、微小な平面を備えた多数個の領域3ができ、
その基板表面には凹凸が形成される。Next, in a second step shown in FIG. 1B, the surface of the substrate on which the resist 2 is formed is etched by reactive ion etching, and then the resist 2 is removed. Thereby, a large number of regions 3 having minute planes are formed,
Asperities are formed on the substrate surface.
【0027】レジスト2によるパターニングは、このエ
ッチングにより領域3、3間において段差4ができるよ
うに、例えば図2Aに示すようなレジストパターンが使
用される。図2Aは図1Aに示した基板1の表面側から
該基板1を垂直に臨んだもので、基板1上に形成された
レジスト2はライン状にパターン形成されている。For patterning with the resist 2, for example, a resist pattern as shown in FIG. 2A is used so that a step 4 is formed between the regions 3 by the etching. FIG. 2A is a vertical view of the substrate 1 from the surface side of the substrate 1 shown in FIG. 1A, and a resist 2 formed on the substrate 1 is patterned in a line shape.
【0028】斯る場合にあっては、レジストの保護によ
ってエッチングされない部分(2に相当する)と、され
る部分2´とがライン状に区分されていることから、エ
ッチングによりその領域3、3間には段差4ができるこ
ととなる。(図1(B)参照)。特に、エネルギビーム
による多結晶化にあっては、この段差は明瞭なものであ
るのが好ましく、例えば段差による凹凸部分の表面形状
は断面で見た場合90度の角度に近いものほど好まし
い。In such a case, since the portion (corresponding to 2) that is not etched by the protection of the resist and the portion 2 'to be etched are divided into a line shape, the regions 3, 3 are etched. A step 4 is formed between them. (See FIG. 1B). Particularly, in the case of polycrystallization by an energy beam, it is preferable that the step is clear. For example, the surface shape of the uneven portion due to the step is preferably as close to 90 ° as viewed in cross section.
【0029】本実施例における領域のサイズはラインの
短手方向としては、各ライン間を0.1μm〜100μ
m程度とし、上記反応性イオンエッチングのための反応
性ガスとしては、基板材料を石英若しくはSiO2 膜が
形成されたガラス基板とした場合にあってはCHF3 ガ
スやCH4、H2 とN2 の混合ガス等が利用できる。In this embodiment, the size of the region is 0.1 μm to 100 μm between each line as the short side direction of the line.
m, and the reactive gas for the reactive ion etching is CHF 3 gas, CH 4 , H 2 and N 2 when the substrate material is quartz or a glass substrate on which a SiO 2 film is formed. 2 mixed gas etc. can be used.
【0030】特に、本発明にあっては、上記領域のサイ
ズ選択は重要であるが、これに加えて段差の大きさ(深
さ)の設定も重要な要素となる。Particularly, in the present invention, the selection of the size of the region is important, but in addition, the setting of the size (depth) of the step is also an important factor.
【0031】その段差の大きさは、上記第2工程での反
応性イオンエッチングによるエッチングの程度(深さ)
によって制御することができるが、通常本願発明の効果
を得るには、その深さを30Å〜500Åとするのが好
ましく、より好ましくは、50Å〜300Åの範囲に設
定することである。特に、30Å以下では、斯る段差部
分において結晶粒界が発生せず、一方500Å以上で
は、微小な領域における結晶粒が段差部分で大きく分離
し、連続した多結晶半導体膜が形成できないという問題
が生じるからである。これらは、いずれも電子顕微鏡の
観察結果により判明している。The size of the step depends on the degree (depth) of the etching by the reactive ion etching in the second step.
In general, in order to obtain the effect of the present invention, the depth is preferably set to 30 ° to 500 °, and more preferably, set to a range of 50 ° to 300 °. In particular, when the angle is 30 ° or less, no crystal grain boundary is generated in such a stepped portion. On the other hand, when the angle is 500 ° or more, crystal grains in a minute region are largely separated at the stepped portion, and a continuous polycrystalline semiconductor film cannot be formed. This is because it occurs. These have all been clarified by the results of observation with an electron microscope.
【0032】この微小な領域の形状は、本実施例では図
2(A)で示したごとく、ライン状としたがこれに限る
ことはなく、形成される多結晶半導体膜の利用にあわせ
て、その形状を決定すればよく、具体的には、矩形状、
格子状、菱形状、円状等の任意の形状でよい。In this embodiment, the shape of the minute region is a line shape as shown in FIG. 2A. However, the present invention is not limited to this. What is necessary is just to determine the shape, specifically, a rectangular shape,
Any shape such as a lattice shape, a rhombus shape, and a circular shape may be used.
【0033】また、隣接する微小領域による段差の大き
さは、本実施例のようにすべて同一にする必要はなく、
上記深さの範囲となるものであれば不揃いなものであっ
てもよい。Further, the size of the steps due to the adjacent minute regions does not need to be all the same as in the present embodiment.
Irregularities may be used as long as the depths fall within the above range.
【0034】次に、図1(C)に示す第3工程では、微
小な領域が形成された基板1の表面に、非晶質シリコン
からなる非晶質半導体膜5を形成する。膜厚は、300
Å〜1200Åとし、上記段差4部分が覆われるように
形成する。この非晶質半導体膜5は、例えば、プラズマ
CVD法により形成され、その成膜条件はシラン(Si
H4 )ガス流量が30〜80sccm(Standar
d Cubic Centimeters per M
inute)、基板温度が100〜600℃、圧力が1
3.3〜266Pa、パワーが13.56MHz、3〜
100Wである。Next, in a third step shown in FIG. 1C, an amorphous semiconductor film 5 made of amorphous silicon is formed on the surface of the substrate 1 on which the minute regions have been formed. The film thickness is 300
The thickness is set to {1200} so as to cover the four steps. The amorphous semiconductor film 5 is formed by, for example, a plasma CVD method, and the film forming condition is silane (Si).
H 4) gas flow 30~80sccm (Standar
d Cubic Centimeters per M
inute), substrate temperature 100-600 ° C, pressure 1
3.3 to 266 Pa, power is 13.56 MHz, 3 to
100W.
【0035】そして、図1(D)に示す第4工程では、
上記非晶質半導体膜5に対してエネルギビーム6を照射
し、その照射領域を多結晶化させることで多結晶シリコ
ンからなる多結晶半導体膜7を得ることができる。Then, in the fourth step shown in FIG.
By irradiating the energy beam 6 to the amorphous semiconductor film 5 and polycrystallizing the irradiated area, a polycrystalline semiconductor film 7 made of polycrystalline silicon can be obtained.
【0036】斯る工程によって得られた多結晶半導体膜
の模式図が図2(B)である。同図も図2(A)と同様
に基板の表面に垂直となる方向から臨んだ図であり、こ
れによれば、ライン状の段差4部分に結晶粒界8が揃う
ように生成していることが分かり、横方向の結晶成長が
その段差部分で止まっていることが確認できる。FIG. 2B is a schematic view of the polycrystalline semiconductor film obtained by such a process. This figure is also a view seen from a direction perpendicular to the surface of the substrate, as in FIG. 2A. According to this figure, the crystal grain boundaries 8 are formed so as to be aligned with the linear stepped portions 4. It can be seen that the crystal growth in the lateral direction has stopped at the step.
【0037】なお、図2Bから分かるように、ラインの
長手方向には予め段差を設けていなかったことから、従
来の種々の要因によって結晶成長が停止しており、これ
による結晶粒界の形状及び位置はランダムなものとなっ
ている。As can be seen from FIG. 2B, since no step was formed in advance in the longitudinal direction of the line, the crystal growth was stopped by various conventional factors, and the shape of the crystal grain boundary and the The positions are random.
【0038】このエネルギービームの照射を施した非晶
質半導体膜としては、本実施例ではCVD法によって形
成されたものを使用したが、本発明は斯る製造方法に限
られたものではなく、この他に蒸着法、スパッタ法等に
よって形成されたものでも良く、更には、エネルギービ
ームの照射を受ける半導体膜としては、既に多結晶とな
っているものであってもよい。この場合、当初の粗悪な
多結晶半導体をエネルギビームの照射によって、本発明
の効果である結晶粒界の位置制御が施された良質の多結
晶半導体膜改質することが可能となる。As the amorphous semiconductor film irradiated with the energy beam, a film formed by the CVD method in this embodiment is used, but the present invention is not limited to such a manufacturing method. In addition, a film formed by a vapor deposition method, a sputtering method, or the like may be used, and a semiconductor film to be irradiated with an energy beam may be a polycrystalline film. In this case, by irradiating the initially poor polycrystalline semiconductor with an energy beam, it becomes possible to modify a high-quality polycrystalline semiconductor film in which the position control of the crystal grain boundary, which is an effect of the present invention, is performed.
【0039】この粗悪な多結晶半導体膜の具体的な例と
しては、常温のような低温で形成された多結晶シリコン
膜等のようなものであり、斯る多結晶半導体膜では膜中
の結晶粒界が非常に多く、キャリア移動度についても極
めて小さなものである。然し乍ら、エネルギビームが照
射される非晶質半導体膜や多結晶半導体膜のいずれのも
のであっても、その照射による多結晶化を良好なものと
するためには、半導体膜中の不純物、具体的には酸素、
水素、窒素、炭素等の濃度ができる限り少ないことが好
ましい。その理由は、いずれの不純物も多結晶化の際
の、結晶成長を阻害するように作用するからで、このた
め、これら不純物を除去するために、例えば、半導体膜
の形成装置の到達真空度を高めたり、或いは半導体膜形
成後、熱処理を施すことで膜中の不純物を放出させる等
の処理を行うことで、半導体膜中の不純物濃度の低減を
図ることが好ましい。A specific example of the poor polycrystalline semiconductor film is a polycrystalline silicon film formed at a low temperature such as a normal temperature. It has a very large number of grain boundaries and an extremely small carrier mobility. However, regardless of whether the film is an amorphous semiconductor film or a polycrystalline semiconductor film to which an energy beam is irradiated, impurities in the semiconductor film, specifically, Oxygen,
It is preferable that the concentration of hydrogen, nitrogen, carbon and the like be as low as possible. The reason is that any of the impurities acts to inhibit crystal growth during polycrystallization, and therefore, in order to remove these impurities, for example, the ultimate vacuum degree of a semiconductor film forming apparatus is reduced. It is preferable that the concentration of impurities in the semiconductor film be reduced by increasing the temperature or performing a process of releasing impurities in the film by performing a heat treatment after the formation of the semiconductor film.
【0040】また、使用するエネルギビームとしては、
短波長パルスレーザ、銅蒸気レーザ、ルビーレーザ、Y
AGレーザ等で、具体的には、ArFエキシマレーザや
F2エキシマレーザ、KrFエキシマレーザ、XeCl
エキシマレーザ、XeFエキシマレーザ等を使用するこ
とができ、照射条件としては表1のごとくである。The energy beam used is as follows:
Short wavelength pulse laser, copper vapor laser, ruby laser, Y
An AG laser or the like, specifically, ArF excimer laser, F 2 excimer laser, KrF excimer laser, XeCl
An excimer laser, a XeF excimer laser, or the like can be used, and irradiation conditions are as shown in Table 1.
【0041】[0041]
【表1】 [Table 1]
【0042】特に、レーザ照射にあたっては、1つの照
射領域について10パルス以上の照射を施して多結晶化
させることが好ましく、より好ましくは照射される半導
体膜が形成された基板を100℃以上600℃以下の温
度範囲の加熱を行いつつレーザビームの照射を行うこと
が膜の多結晶化には好適である。とりわけ、その温度範
囲の中でも200℃以上500℃以下とするのがよく、
本実施例では約400℃に設定し多結晶化を施した。In particular, when irradiating a laser, it is preferable that one irradiation region is irradiated with 10 pulses or more to be polycrystallized. More preferably, the substrate on which the semiconductor film to be irradiated is formed is 100 ° C. to 600 ° C. Irradiation with a laser beam while heating in the following temperature range is suitable for polycrystallization of a film. In particular, the temperature is preferably 200 ° C. or more and 500 ° C. or less in the temperature range,
In this embodiment, the temperature was set to about 400 ° C. to perform polycrystallization.
【0043】かかる照射によれば、多結晶化は、半導体
の表面自由エネルギーが最小化する方位、即ち配向方向
を備えながら、膜面に対して平行に横方向に成長する。
特に表面がフリーサーフェスのシリコン膜の場合にあっ
ては、(111)面に配向することとなる。According to such irradiation, the polycrystallization grows in a lateral direction parallel to the film surface while having an orientation in which the surface free energy of the semiconductor is minimized, that is, an orientation direction.
In particular, when the surface is a silicon film having a free surface, it is oriented to the (111) plane.
【0044】また、本実施例では使用しなかったが、照
射を受ける非晶質半導体膜あるいは多結晶半導体膜に予
めSiOx等の酸化膜やSiNx等の窒素酸化膜等から
なるキャップ膜を膜表面に形成し、かかるキャップ膜を
介して、エネルギビームを照射することで、配向方向を
[100]や[110]等に制御することも可能であ
る。Although not used in this embodiment, a cap film made of an oxide film such as SiOx or a nitrogen oxide film such as SiNx is previously formed on the amorphous semiconductor film or the polycrystalline semiconductor film to be irradiated. It is also possible to control the orientation direction to [100] or [110] by irradiating an energy beam through such a cap film.
【0045】このような、横方向への結晶成長のドライ
ビングフォースは、表面自由エネルギーの異方向性のた
めに、下地となる基板表面に予め設けられた段差の位置
でその表面自由エネルギーの値が変化することとなり、
結果として横方向への結晶成長が停止してしまうことと
なる。In such a driving force for crystal growth in the lateral direction, the value of the surface free energy at the position of the step provided in advance on the surface of the substrate serving as an underlayer is due to the different direction of the surface free energy. Will change,
As a result, the lateral crystal growth stops.
【0046】従って、微少な平面を備えた領域のサイズ
や位置を制御しておくことで、所望の位置に結晶粒界を
生成することが可能となり、且つ隣接する段差の間隔に
よって、結晶粒のサイズを所望の値に設定することがで
きる。Therefore, by controlling the size and position of the region having the minute plane, it is possible to generate a crystal grain boundary at a desired position, and to control the size of the crystal grain by the distance between adjacent steps. The size can be set to a desired value.
【0047】また、本発明者等によれば、隣接する段差
の間隔の設定によっては、領域内の結晶粒中にも結晶粒
界が発生してしまうこともあるが、この場合であって
も、該結晶粒界によって分解されてしまった結晶粒はい
ずれも、上述したように全て(111)面に揃っている
ことから、たとえ微小領域内にその様な結晶粒界が生じ
てしまったとしても、これによる影響は多結晶半導体膜
の電気的特性に殆ど影響を与えないことを確認してい
る。According to the present inventors, depending on the setting of the interval between adjacent steps, a crystal grain boundary may be generated in the crystal grains in the region. Since all of the crystal grains that have been decomposed by the crystal grain boundaries are aligned on the (111) plane as described above, even if such crystal grain boundaries are generated in the minute region, However, it has been confirmed that the influence of this hardly affects the electrical characteristics of the polycrystalline semiconductor film.
【0048】従って、本願発明の多結晶半導体膜を例え
ば薄膜トランジスタのチャンネル領域として利用する場
合にあっては、チャンネル領域の多結晶半導体膜部分に
は結晶粒界の存在しない状態を作ることができ、これに
よれば、従来のような粒界によるキャリア走行の阻害が
なくなり、スイッチング特性が良好な素子得ることがで
きることとなる。Therefore, when the polycrystalline semiconductor film of the present invention is used, for example, as a channel region of a thin film transistor, a state where no crystal grain boundary exists in the polycrystalline semiconductor film portion of the channel region can be formed. According to this, the carrier traveling is not hindered by the grain boundary as in the related art, and an element having good switching characteristics can be obtained.
【0049】更には、本願発明の多結晶半導体膜では、
その結晶粒界で囲まれた結晶粒内の結晶性は、固相成長
法による膜と比較して、粒内の欠陥密度は小さい高品質
なものである。Further, in the polycrystalline semiconductor film of the present invention,
As for the crystallinity in the crystal grains surrounded by the crystal grain boundaries, the defect density in the grains is high quality as compared with a film formed by the solid phase growth method.
【0050】また、本願発明による多結晶半導体膜を太
陽電池における光電変換用の半導体材料として利用して
もよく、この場合にあっては、段差によって位置が特定
されている結晶粒界が在る多結晶半導体膜部分の表面に
光キャリア収集のための集電極を設けることが好まし
い。これによれば、発電に寄与しない結晶粒界部が光照
射を妨げる集電極下に位置するので、単位面積当たりの
効率の低下が防げる。さらに、一般に光キャリアを再結
合させ光電変換特性に悪影響を及ぼすその結晶粒界近傍
に集電極を設けることで、その様な再結合の発生を抑制
することが可能となる。Further, the polycrystalline semiconductor film according to the present invention may be used as a semiconductor material for photoelectric conversion in a solar cell. In this case, there is a crystal grain boundary whose position is specified by a step. It is preferable to provide a collecting electrode for collecting photocarriers on the surface of the polycrystalline semiconductor film portion. According to this, since the crystal grain boundary portion that does not contribute to power generation is located below the collector electrode that hinders light irradiation, a decrease in efficiency per unit area can be prevented. Further, by providing a collecting electrode near the crystal grain boundary which generally recombines photocarriers and adversely affects photoelectric conversion characteristics, it is possible to suppress the occurrence of such recombination.
【0051】更に、本願発明による多結晶半導体膜によ
れば、従来半導体としての機械的強度の低下現象をもた
らす結晶粒界の、位置制御ができることから、半導体と
しての機械強度を制御することができることとなり、例
えば、マイクロマシン用の多結晶半導体材料として利用
することも可能である。Further, according to the polycrystalline semiconductor film of the present invention, since the position of a crystal grain boundary which causes a phenomenon of a decrease in mechanical strength as a conventional semiconductor can be controlled, the mechanical strength as a semiconductor can be controlled. Thus, for example, it can be used as a polycrystalline semiconductor material for a micromachine.
【0052】[0052]
【実施例】尚、実施例では多結晶シリコン膜についての
み説明したが、本願発明による多結晶半導体膜はこれら
に限られずゲルマニウム、ガリウムによる半導体膜であ
っても同様である。Although only the polycrystalline silicon film has been described in the embodiments, the polycrystalline semiconductor film according to the present invention is not limited to these, and the same applies to a semiconductor film made of germanium or gallium.
【0053】次に、本願発明による多結晶半導体膜をp
n接合型太陽電池における光電変換用半導体材料として
用いた実施例につき図3(A)ないし図4(E)に従い
説明する。Next, the polycrystalline semiconductor film according to the present invention is
Embodiments used as a semiconductor material for photoelectric conversion in an n-junction solar cell will be described with reference to FIGS. 3A to 4E.
【0054】まず、図3(A)に示すように、前述した
実施例の図1(A)及び図1(B)に示す工程とと同様
に、任意の形状の微少な平面を多数個形成すべく、レジ
ストをパターニングし、このレジストをマスクとして反
応性イオンエッチングによりエッチングし、基板10表
面に凹凸を形成する。この凹凸により、微小な平面を備
えた多数この領域12、12が形成される。この領域間
において、段差11が形成される。この実施例では、基
板としてタンタル(Ta),タングステン(W)等の高
融点金属が用いられ、この基板10が一方の電極として
用いられる。また、段差11は100〜500Å、段差
間の幅、すなわち微小領域12、12の幅は200μm
〜2cmとした。First, as shown in FIG. 3A, a large number of small planes having an arbitrary shape are formed in the same manner as in the steps shown in FIGS. 1A and 1B of the above-described embodiment. For this purpose, the resist is patterned and etched by reactive ion etching using the resist as a mask to form irregularities on the surface of the substrate 10. Due to the unevenness, a large number of these regions 12, 12 having minute planes are formed. A step 11 is formed between these regions. In this embodiment, a high melting point metal such as tantalum (Ta) or tungsten (W) is used as a substrate, and this substrate 10 is used as one electrode. The height of the step 11 is 100 to 500 °, and the width between the steps, that is, the width of the minute regions 12 is 200 μm.
22 cm.
【0055】次に、図3(B)に示す工程では、微小な
領域12、12が形成された基板10上の表面に、リン
をドープしたn型非晶質シリコン膜13を500〜20
00オングストロームの膜厚でプラズマCVD法により
成膜する。この成膜条件はSiH4 ガス流量が30〜8
0sccm、ホスフィン(PH3 )ガス流量が10〜3
0sccm、基板温度が400〜600℃、圧力が1
3.3〜266Pa、パワーが13.56MHz、30
〜100Wである。Next, in the step shown in FIG. 3B, an n-type amorphous silicon film 13 doped with phosphorus is formed on the surface of the substrate 10 on which the minute regions 12 and 12 are formed by 500 to 20 nm.
A film is formed by a plasma CVD method to a thickness of 00 Å. The film forming conditions are such that the SiH 4 gas flow rate is 30 to 8
0 sccm, phosphine (PH 3 ) gas flow rate is 10 to 3
0 sccm, substrate temperature 400-600 ° C, pressure 1
3.3-266 Pa, power 13.56 MHz, 30
100100W.
【0056】次に、図3(C)に示す工程では、エキシ
マレーザ6を用い、n型非晶質シリコン膜12を照射
し、その照射領域を多結晶化させることで、多結晶シリ
コンからなるn型多結晶半導体膜14を得る。この時の
レーザエネルギー密度は200〜500mJ/cm2 、
ショット数は100〜1000ショット、レーザ照射時
の基板温度は300〜500℃とした。この時、形成さ
れたn型多結晶半導体膜14は基板10の段差11部分
に結晶粒界15が揃うように形成される。Next, in the step shown in FIG. 3C, the n-type amorphous silicon film 12 is irradiated with the excimer laser 6 and the irradiated region is polycrystallized, so that the film is made of polycrystalline silicon. An n-type polycrystalline semiconductor film 14 is obtained. The laser energy density at this time was 200 to 500 mJ / cm 2 ,
The number of shots was 100 to 1000 shots, and the substrate temperature during laser irradiation was 300 to 500 ° C. At this time, the formed n-type polycrystalline semiconductor film 14 is formed such that the crystal grain boundaries 15 are aligned with the step 11 of the substrate 10.
【0057】続いて、このn型多結晶半導体膜14上に
上記図3(B)に示す工程と同様にn型非晶質シリコン
膜を形成する工程と、上記図3(C)に示す工程と同様
にエキシマレーザ6による多結晶化を繰り返し、膜厚1
0〜50μm程度のn型多結晶膜14を形成する。この
ように繰り返し、非晶質シリコンの成膜とその多結晶化
を行うのは、エキシマレーザによる多結晶化では膜厚2
000Å程度までが膜質の良好な膜が得られる限界であ
るので、良好な膜を多層積層し、所望の膜厚を得るよう
にしたものである。また、多層に積層する際にも、上に
積層される多結晶半導体膜は下地多結晶半導体膜の結晶
粒界の上方を受け継ぎ、同様の位置に結晶粒界が形成さ
れる。すなわち、基板10の段差11部分に結晶粒界1
5が揃うように形成される。Subsequently, a step of forming an n-type amorphous silicon film on the n-type polycrystalline semiconductor film 14 in the same manner as the step shown in FIG. 3B, and a step shown in FIG. The polycrystallization by the excimer laser 6 is repeated in the same manner as
An n-type polycrystalline film 14 of about 0 to 50 μm is formed. The film formation of the amorphous silicon and the polycrystallization thereof are repeated as described above because the film thickness of 2 is obtained by the polycrystallization using the excimer laser.
Since the film thickness of about 000 ° is the limit at which a film with good film quality can be obtained, a good film is laminated in multiple layers to obtain a desired film thickness. In addition, when a multilayer is stacked, a polycrystalline semiconductor film stacked thereover inherits above a crystal grain boundary of a base polycrystalline semiconductor film, and a crystal grain boundary is formed at a similar position. That is, the crystal grain boundary 1 is formed at the step 11 portion of the substrate 10.
5 are formed.
【0058】次に、図4(D)に示す工程では、熱拡散
でボロン等を多結晶半導体膜14表面に拡散し、p型多
結晶半導体層16を形成する。この時の接合深さは0.
1μmとした。Next, in the step shown in FIG. 4D, boron or the like is diffused into the surface of the polycrystalline semiconductor film 14 by thermal diffusion to form a p-type polycrystalline semiconductor layer 16. The bonding depth at this time is 0.
It was 1 μm.
【0059】そして、図4(E)に示す工程では、表面
にITO等からなる透明電極17をp型多結晶半導体層
16上にスパッタ法で500〜2000Åの膜厚で成膜
し、基板10の段差11上、即ち多結晶半導体膜14の
位置制御された結晶粒界15上にAl(アルミニウム)
からなる集電極18を形成する。In the step shown in FIG. 4E, a transparent electrode 17 made of ITO or the like is formed on the surface of the p-type polycrystalline semiconductor layer 16 by sputtering at a thickness of 500 to 2,000 ° in the step shown in FIG. (Al) on the step 11 of the polycrystalline semiconductor film 14, that is, on the grain boundary 15 of the polycrystalline semiconductor film 14 whose position is controlled.
Is formed.
【0060】このように、段差によって位置が特定され
ている結晶粒界が在る多結晶半導体膜部分の表面に光キ
ャリア収集のための集電極を設けることで、一般に光キ
ャリアを再結合させ光電変換特性に悪影響を及ぼすその
結晶粒界近傍に集電極が設けられ、その様な再結合の発
生を抑制することができる。As described above, by providing the collecting electrode for collecting photocarriers on the surface of the polycrystalline semiconductor film portion where the crystal grain boundary whose position is specified by the step is present, the photocarriers are generally recombined and the photoelectric conversion is performed. A collecting electrode is provided in the vicinity of the crystal grain boundary, which adversely affects the conversion characteristics, and the occurrence of such recombination can be suppressed.
【0061】次に、本願発明による多結晶半導体膜をp
n接合型太陽電池における光電変換用半導体材料として
用いた第2実施例につき図5(A)ないし図5(D)に
従い説明する。Next, the polycrystalline semiconductor film according to the present invention is
A second embodiment used as a semiconductor material for photoelectric conversion in an n-junction solar cell will be described with reference to FIGS. 5 (A) to 5 (D).
【0062】前述の第1の実施例の図3(A)ないし図
3(C)に示す工程と同様に、Ta、Wの高融点金属基
板10の表面に100〜500Åの段差11、その幅が
200μm〜2cmになるように凹凸を形成し、多数の
微小領域12、12を形成する。そして、リンをドープ
したn型非晶質シリコン膜13を500〜2000Åの
膜厚でプラズマCVD法により成膜する。そして、エキ
シマレーザ6を用い、非晶質シリコン膜13を多結晶化
し、基板10の段差部分11に結晶粒界13を持つn型
多結晶半導体膜14を形成する。As in the steps shown in FIGS. 3A to 3C of the first embodiment, the surface 11 of the Ta, W high melting point metal substrate 10 has a step 11 of 100 to 500.degree. Are formed so as to be 200 μm to 2 cm, and a large number of minute regions 12 are formed. Then, an n-type amorphous silicon film 13 doped with phosphorus is formed to a thickness of 500 to 2000 ° by a plasma CVD method. Then, the amorphous silicon film 13 is polycrystallized using the excimer laser 6 to form an n-type polycrystalline semiconductor film 14 having a crystal grain boundary 13 at the step portion 11 of the substrate 10.
【0063】次に、図5(A)に示す工程では、多結晶
膜半導体14上にリンをドープした非晶質シリコン膜2
0を10〜50μmの膜厚でプラズマCVD法により成
膜する。この成膜条件はSiH4 ガス流量が30〜80
sccm、PH3 ガス流量が10〜30sccm、基板
温度が400〜600℃、圧力が13.3〜266P
a、パワーが13.56MHz、30〜100Wであ
る。Next, in the step shown in FIG. 5A, the amorphous silicon film 2 doped with phosphorus is
0 is formed by a plasma CVD method in a film thickness of 10 to 50 μm. The film forming conditions are such that the flow rate of the SiH 4 gas is 30 to 80.
sccm, PH 3 gas flow rate is 10-30 sccm, substrate temperature is 400-600 ° C., pressure is 13.3-266P
a, The power is 13.56 MHz, 30 to 100 W.
【0064】続いて、図5(B)に示す工程では、非晶
質シリコン膜20を500〜700℃、20時間で結晶
化させる固相成長法により、多結晶化させ、多結晶シリ
コン膜21を形成する。この時、図5(B)に示すよう
に、形成された多結晶シリコン膜21は下地の多結晶シ
リコン膜14の結晶粒界15の情報を受け継ぎ、同様の
位置に粒界15ができる。Subsequently, in the step shown in FIG. 5B, the amorphous silicon film 20 is polycrystallized by a solid phase growth method in which the amorphous silicon film 20 is crystallized at 500 to 700 ° C. for 20 hours. To form At this time, as shown in FIG. 5B, the formed polycrystalline silicon film 21 inherits information of the crystal grain boundary 15 of the underlying polycrystalline silicon film 14, and the grain boundary 15 is formed at a similar position.
【0065】次に、図5(C)に示す工程では、熱拡散
でボロン等を多結晶半導体膜21表面に拡散し、p型多
結晶半導体層22を形成する。Next, in the step shown in FIG. 5C, boron or the like is diffused into the surface of the polycrystalline semiconductor film 21 by thermal diffusion to form a p-type polycrystalline semiconductor layer 22.
【0066】そして、図5(D)に示す工程では、多結
晶半導体層22表面にITO等からなる透明電極17を
成膜し、基板10の段差11上、即ち多結晶半導体膜2
1の位置制御された結晶粒界15上にAlからなる集電
極18を形成する。Then, in the step shown in FIG. 5D, a transparent electrode 17 made of ITO or the like is formed on the surface of the polycrystalline semiconductor layer 22, and is formed on the step 11 of the substrate 10, that is, on the polycrystalline semiconductor film 2.
A collector electrode 18 made of Al is formed on the crystal grain boundary 15 whose position is controlled.
【0067】このように、段差によって位置が特定され
ている結晶粒界が在る多結晶半導体膜部分の表面に光キ
ャリア収集のための集電極を設けることで、一般に光キ
ャリアを再結合させ光電変換特性に悪影響を及ぼすその
結晶粒界近傍に集電極が設けられ、その様な再結合の発
生を抑制することができる。As described above, by providing the collecting electrode for collecting the photocarriers on the surface of the polycrystalline semiconductor film portion where the crystal grain boundary whose position is specified by the step is provided, the photocarriers are generally recombined and the photoelectric conversion is performed. A collecting electrode is provided in the vicinity of the crystal grain boundary, which adversely affects the conversion characteristics, and the occurrence of such recombination can be suppressed.
【0068】次に、本願発明による多結晶半導体膜を太
陽電池における光電変換用半導体材料として用いた第3
実施例につき図6に従い説明する。この実施例は、pn
接合型太陽電池のpn接合界面にi型非晶質シリコン層
を介在させたものである。Next, a third example in which the polycrystalline semiconductor film according to the present invention was used as a semiconductor material for photoelectric conversion in a solar cell.
An embodiment will be described with reference to FIG. This embodiment uses pn
This is one in which an i-type amorphous silicon layer is interposed at a pn junction interface of a junction type solar cell.
【0069】前述の第1の実施例の図3(A)ないし図
3(C)に示す工程と同様に、Ta、Wの高融点金属基
板10の表面に100〜500Åの段差11、その幅が
200μm〜2cmなるように凹凸を形成し、多数の微
小領域12、12を形成する。そして、リンをドープし
たn型非晶質シリコン膜を500〜2000Åの膜厚で
プラズマCVD法により成膜する。そして、エキシマレ
ーザ6を用い、非晶質シリコン膜4を多結晶化し、基板
10の段差部分11に結晶粒界を持つn型多結晶半導体
膜を形成する。そして、上記図3(C)に示す工程と同
様にエキシマレーザ6による多結晶化を繰り返し、膜厚
10〜50μm程度のn型多結晶膜13を形成するか、
または、上記図4Aに示すように多結晶膜半導体上にリ
ンをドープした非晶質シリコン膜を10〜50μmプラ
ズマCVD法により成膜し、この非晶質シリコン膜を5
00〜700℃、20時間で結晶化させる固相成長法に
より、多結晶化させ、多結晶シリコン膜を形成すること
により、多結晶半導体膜21が形成される(図6(A)
参照)。Similar to the steps shown in FIGS. 3A to 3C of the first embodiment, the surface of the Ta, W high melting point metal substrate 10 has a step 11 of 100 to 500.degree. Are formed so as to be 200 μm to 2 cm, and a large number of minute regions 12 are formed. Then, an n-type amorphous silicon film doped with phosphorus is formed to a thickness of 500 to 2000 ° by a plasma CVD method. Then, the amorphous silicon film 4 is polycrystallized using the excimer laser 6 to form an n-type polycrystalline semiconductor film having a crystal grain boundary at the step portion 11 of the substrate 10. Then, similarly to the step shown in FIG. 3C, the polycrystallization by the excimer laser 6 is repeated to form the n-type polycrystalline film 13 having a thickness of about 10 to 50 μm.
Alternatively, as shown in FIG. 4A, an amorphous silicon film doped with phosphorus is formed on a polycrystalline film semiconductor by a plasma CVD method of 10 to 50 μm.
The polycrystalline semiconductor film 21 is formed by forming a polycrystalline silicon film by polycrystallization by a solid phase growth method of crystallizing at 00 to 700 ° C. for 20 hours (FIG. 6A).
reference).
【0070】図6(B)に示す工程では、多結晶半導体
膜21上にi型非晶質シリコン23を20〜350Åの
膜厚でプラズマCVD法により成膜する。この成膜条件
はSiH4 ガス流量が30〜80sccm、基板温度が
400〜600℃、圧力が13.3〜266Pa、パワ
ーが13.56MHz、30〜100Wである。In the step shown in FIG. 6B, i-type amorphous silicon 23 is formed on polycrystalline semiconductor film 21 to a thickness of 20 to 350 ° by a plasma CVD method. The film formation conditions are as follows: SiH 4 gas flow rate is 30 to 80 sccm, substrate temperature is 400 to 600 ° C., pressure is 13.3 to 266 Pa, power is 13.56 MHz, and 30 to 100 W.
【0071】続いて、図6(C)に示す工程では、この
i型非晶質シリコン23上にp型非晶質シリコン24を
50〜100Åの膜厚でプラズマCVD法により成膜す
る。この成膜条件はSiH4 ガス流量が30〜80sc
cm、ジボラン(B2H6)ガス流量が30sccm、基
板温度が400〜600℃、圧力が13.3〜266P
a、パワーが13.56MHz,30〜100Wであ
る。Subsequently, in a step shown in FIG. 6C, a p-type amorphous silicon film 24 is formed on the i-type amorphous silicon film 23 with a thickness of 50 to 100 ° by a plasma CVD method. The film forming conditions are such that the SiH 4 gas flow rate is 30 to 80 sc
cm, diborane (B 2 H 6 ) gas flow rate is 30 sccm, substrate temperature is 400 to 600 ° C., pressure is 13.3 to 266P.
a, The power is 13.56 MHz, 30 to 100 W.
【0072】そして、図6(D)に示す工程では、p型
非晶質シリコン24表面に透明電極17を成膜し、基板
10の段差11上、即ち多結晶半導体膜21の位置制御
された結晶粒界15上にAl集電極18を形成する。Then, in the step shown in FIG. 6D, a transparent electrode 17 is formed on the surface of the p-type amorphous silicon 24, and the position of the polycrystalline semiconductor film 21 is controlled on the step 11 of the substrate 10, that is. An Al collector electrode 18 is formed on the crystal grain boundary 15.
【0073】尚、本工程では、下地の多結晶半導体膜の
形成にエキシマレーザを用いたが、YAGレーザ等の他
のレーザでも可能である。In this step, an excimer laser is used for forming the underlying polycrystalline semiconductor film, but another laser such as a YAG laser can be used.
【0074】多結晶化の方法としては、上記のエネルギ
ービーム法以外に、固相成長法や、真空中若しくは不活
性ガス雰囲気中で、基板上に成膜した多結晶膜若しくは
非晶質膜をハロゲンランプで急速に加熱し、結晶化させ
る、いわゆるRTA法や,基板上に成膜した多結晶膜若
しくは非晶質膜にSiO2にキャップ膜を成膜し、全体
を1350℃に加熱し、そしてヒータまたは集光した水
銀ランプで幅1mm、長さ50〜125mmの領域を1
450℃に加熱溶融し、この溶融領域を1〜2mm/s
ecで操作し全体を結晶化させる、いわゆるZMR法
や、高周波や交流磁界を用いて加熱溶融する方法等の再
結晶法を用いることができる。As the polycrystallization method, in addition to the above-described energy beam method, a solid phase growth method, a polycrystalline film or an amorphous film formed on a substrate in a vacuum or an inert gas atmosphere may be used. A capping film is formed on SiO 2 on a polycrystalline film or an amorphous film formed on a substrate by so-called RTA method of rapidly heating and crystallizing with a halogen lamp, and the whole is heated to 1350 ° C. Then, an area of 1 mm in width and 50 to 125 mm in length is defined as 1
Heated and melted to 450 ° C, and this melted area is 1-2 mm / s
A recrystallization method such as a so-called ZMR method in which the whole is crystallized by operating with ec, or a method of heating and melting using a high frequency or an alternating magnetic field can be used.
【0075】なお、上述した各実施例においては、多結
晶半導体膜の位置制御された結晶粒界上に集電極を設け
ているが、更に、これら結晶粒界の中央部に集電極を設
けるように構成しても良い。このように、段差によって
位置が特定されている結晶粒界がある多結晶半導体膜部
分の中間部の表面に光キャリア収集のための集電極を設
けることで、光キャリアの再結合の発生をより抑制する
ことができ、光電変換効率の低下が抑制できる。In each of the above-described embodiments, the collector electrode is provided on the crystal grain boundary whose position is controlled in the polycrystalline semiconductor film. However, the collector electrode is further provided at the center of the crystal grain boundary. May be configured. As described above, by providing the collecting electrode for collecting the photocarriers on the surface of the intermediate portion of the polycrystalline semiconductor film portion where the crystal grain boundaries whose positions are specified by the steps are provided, the occurrence of the recombination of the photocarriers can be further reduced. Can be suppressed, and a decrease in photoelectric conversion efficiency can be suppressed.
【0076】次に、本願発明による多結晶半導体膜をチ
ャネル部に用いた薄膜トランジスタ(TFT)の実施例
につき図7〜図8に従い説明する。図7(A)はこの実
施例のTFTの断面図、図7(B)は金属配線を取り除
いた状態で図7(A)を上から見た平面図である。本実
施例では基板に凸部を設けることにより得られた結晶粒
界を制御された多結晶シリコン膜上に、TFTのチャン
ネル部を形成している。Next, an embodiment of a thin film transistor (TFT) using a polycrystalline semiconductor film for a channel portion according to the present invention will be described with reference to FIGS. FIG. 7A is a sectional view of the TFT of this embodiment, and FIG. 7B is a plan view of FIG. 7A viewed from above with the metal wiring removed. In this embodiment, a channel portion of a TFT is formed on a polycrystalline silicon film in which a crystal grain boundary obtained by providing a projection on a substrate is controlled.
【0077】図7(A)に示すように、ガラスなどから
なる透明絶縁基板30には、TFTのチャネル部になる
部分に段差100〜500Åの凸部31が形成されてい
る。この基板30上に、前述したこの発明の多結晶半導
体膜32が設けられる。この基板30上にp-(または
n-)型またはi型の非晶質シリコン膜をプラズマCV
D法などにより500〜1000Å形成し、エキシマレ
ーザの照射により、多結晶化し、多結晶半導体膜32が
得られる。この多結晶半導体膜32の凸部31上にゲー
ト絶縁膜33を介してゲート電極34が設けられ、この
ゲート電極34をマスクとしてセルフアラインによりn
(またはp)型のソース、ドレイン領域35、36が設
けられている。ゲート電極34の保護膜39とコンタク
トホールを介してソース、ドレイン領域35、36とそ
れぞれオーミックコンタクトするソース、ドレイン電極
37、38が設けられている。この実施例のTFTは、
図7(B)に示すように、チャネルと直交する結晶粒界
15、すなわち、Y軸方向は段差部に位置するように位
置制御されており、チャネル部と平行なX軸方向に結晶
粒界15が走る。従って、ソース、ドレイン領域間を流
れる電流が結晶粒界を横切ることがない構造が可能にな
り、高速動作のTFTが作成できる。As shown in FIG. 7A, on a transparent insulating substrate 30 made of glass or the like, a convex portion 31 having a step of 100 to 500 ° is formed in a portion to be a channel portion of the TFT. On this substrate 30, the above-described polycrystalline semiconductor film 32 of the present invention is provided. P This substrate 30 - (or n -) type or i-type amorphous silicon film of plasma CV
A film having a thickness of 500 to 1000 ° is formed by the D method or the like, and is polycrystallized by irradiation with an excimer laser, whereby a polycrystalline semiconductor film 32 is obtained. A gate electrode 34 is provided on convex portion 31 of polycrystalline semiconductor film 32 via gate insulating film 33, and n is formed by self-alignment using gate electrode 34 as a mask.
(Or p) type source and drain regions 35 and 36 are provided. Source / drain electrodes 37 and 38 are provided in ohmic contact with the source / drain regions 35 and 36 through the protective film 39 of the gate electrode 34 and the contact holes, respectively. The TFT of this embodiment is
As shown in FIG. 7 (B), the crystal grain boundary 15 that is perpendicular to the channel, i.e., Y-axis direction is a position control so as to be positioned in the stepped portion, the channel portion parallel to the X-axis direction in the crystal grain boundaries 15 runs. Accordingly, a structure in which a current flowing between the source and drain regions does not cross a crystal grain boundary is possible, and a high-speed operation TFT can be manufactured.
【0078】次に、この実施例のTFTの工程を図8
(A)ないし図8(C)に従い説明する。図8(A)に
示す工程では、段差100〜500Åの凸部31が設け
られたガラスなどの透明絶縁性基板30上にp-型非晶
質シリコン膜を例えば、プラズマCVD法により、50
0〜1000Åの膜厚で形成する。この成膜条件はSi
H4 ガス流量が30〜80sccm、B2H6ガス流量が
0〜30sccm、基板温度が400〜600℃、圧力
が13.3〜266Pa、パワーが13.56MHz、
30〜100Wである。次に、エキシマレーザ6を照射
し非晶質シリコン膜を多結晶化し、p-型多結晶半導体
膜32を形成する。この時レーザエネルギー密度は15
0〜350mJ/cm2 、基板温度は20〜400℃と
する。この多結晶化により、多結晶化半導体膜32は段
差部分に結晶粒界15が位置するように制御される。Next, the steps of the TFT of this embodiment will be described with reference to FIG.
This will be described with reference to FIGS. In the step shown in FIG. 8A, a p − -type amorphous silicon film is formed on a transparent insulating substrate 30 such as glass provided with a projection 31 with a step of 100 to 500 ° by, for example, a plasma CVD method.
It is formed with a thickness of 0 to 1000 °. This film formation condition is Si
H 4 gas flow rate 30~80sccm, B 2 H 6 gas flow rate 0~30Sccm, the substrate temperature is 400 to 600 ° C., a pressure 13.3~266Pa, power 13.56 MHz,
30 to 100W. Next, the amorphous silicon film is polycrystallized by irradiating the excimer laser 6 to form a p − type polycrystalline semiconductor film 32. At this time, the laser energy density is 15
0 to 350 mJ / cm 2 , and the substrate temperature is 20 to 400 ° C. By this polycrystallization, the polycrystalline semiconductor film 32 is controlled so that the crystal grain boundary 15 is located at the step.
【0079】続いて、図8(B)に示す工程では、この
多結晶半導体膜32をパターニングした後、この多結晶
半導体膜32上に、SiO2からなるゲート絶縁膜33
をCVD法、スパッタ法を用い基板温度200〜600
℃で1000〜2000Åの膜厚で成膜する。そのゲー
ト絶縁膜33上に多結晶シリコンをCVD法等を用いて
200〜500℃の基板温度で500〜2000Å成膜
し、フォトリソグラフィ工程を経てゲート電極34を形
成する。Subsequently, in a step shown in FIG. 8B, after patterning the polycrystalline semiconductor film 32, a gate insulating film 33 made of SiO 2 is formed on the polycrystalline semiconductor film 32.
Substrate temperature of 200 to 600 using a CVD method and a sputtering method.
The film is formed at a temperature of 1000C to a thickness of 1000 to 2000C. Polycrystalline silicon is formed on the gate insulating film 33 by a CVD method or the like at a substrate temperature of 200 to 500 ° C. to a temperature of 500 to 2000 °, and a gate electrode 34 is formed through a photolithography process.
【0080】この状態でゲート電極34をマスクとし、
ソース、ドレイン領域形成のためイオン注入により、P
(燐)イオンをエネルギー10〜100KeV、ドーズ
量2×1015〜1016cm-2で注入する。その後、エキ
シマレーザ、熱アニール等によりソース、ドレイン領域
35、36の活性化とゲート電極34の結晶性の回復を
同時に行う。なお、イオン注入条件等によって、活性化
を行わない場合もある。In this state, using the gate electrode 34 as a mask,
By ion implantation to form source and drain regions, P
(Phosphorus) ions are implanted at an energy of 10 to 100 KeV and a dose of 2 × 10 15 to 10 16 cm −2 . Thereafter, activation of the source and drain regions 35 and 36 and recovery of the crystallinity of the gate electrode 34 are simultaneously performed by excimer laser, thermal annealing or the like. Note that activation may not be performed depending on ion implantation conditions and the like.
【0081】次に図8(C)に示す工程では、保護絶縁
膜39をCVD法、スパッタ法等で500〜1000Å
成膜する。そして、フォトリソグラフィ工程によりソー
ス、ドレイン領域35、36上に保護絶縁膜39を貫通
するコンタクトホールを1〜2μm角で開け、真空蒸着
法、スパッタ法等によりAl,Cr等の金属成膜800
0〜15000Å成膜する。この金属成膜をフォトリソ
グラフィ工程により、パタニングし、ソース、ドレイン
電極37、38を形成することにより薄膜トランジスタ
が作製できる。この工程において、イオン打ち込みはP
イオンを用いたが、もちろんAs(ヒ素)イオン等でも
問題ない。また、チャネル領域をn-型またはi型の多
結晶半導体膜で構成し、ソース、ドレイン領域にB(ボ
ロン)をイオン注入してもよい。Next, in the step shown in FIG. 8C, the protective insulating film 39 is formed by a CVD method, a sputtering method or the like to a thickness of 500 to 1000 °.
Form a film. Then, a contact hole penetrating the protective insulating film 39 is formed in a square of 1 to 2 μm on the source and drain regions 35 and 36 by a photolithography process, and a metal film 800 of Al, Cr or the like is formed by a vacuum deposition method, a sputtering method, or the like.
0-15000Å is formed. This metal film is patterned by a photolithography process, and source and drain electrodes 37 and 38 are formed, whereby a thin film transistor can be manufactured. In this step, ion implantation is performed at P
Although ions were used, of course, there is no problem with As (arsenic) ions or the like. Alternatively, the channel region may be formed of an n − -type or i-type polycrystalline semiconductor film, and B (boron) may be ion-implanted into the source and drain regions.
【0082】次に、本願発明による多結晶半導体膜をチ
ャネル部に用いた薄膜トランジスタ(TFT)の第2の
実施例につき図9〜図10に従い説明する。図9はこの
実施例のTFTの断面図である。本実施例では基板に設
けたゲート電極の段差により、多結晶半導体の結晶粒界
を制御し、この多結晶シリコン膜上に、TFTのチャン
ネル部を形成している。図9に示すように、ガラスなど
からなる透明絶縁基板40に膜厚500Å以下のCr,
Mo,Taなどからなるゲート電極41が形成されてい
る。このゲート電極41により基板上40上には〜50
0Åの段差が形成されることになる。このゲート電極4
1を含め基板40上に1000〜2000Åの膜厚の絶
縁膜42がCVD法等により設けられる。この絶縁膜4
2上に前述したこの発明の多結晶半導体膜43が設けら
れる。多結晶半導体膜43は絶縁膜42上に非晶質シリ
コン膜をプラズマCVD法などにより500〜1000
Å形成し、エキシマレーザの照射により、多結晶化する
ことにより得られる。この多結晶半導体膜43上にリン
をドープした500〜1000Åのn型非晶質シリコン
または多結晶シリコン膜をプラズマCVD法などにより
形成した後、パターニングにより、ソース、ドレイン領
域45、46が形成される。ソース、ドレイン領域4
5、46上にそれぞれソース、ドレイン電極47、48
が設けられ、この実施例のTFTが得られる。この実施
例のTFT前述の実施例と同様に、チャネルと直交する
結晶粒界は段差部に位置するように位置制御されてお
り、チャネル部と平行に結晶粒界が走る。従って、ソー
ス、ドレイン領域間を流れる電流が結晶粒界を横切るこ
とがない構造が可能になり、高速動作のTFTが作成で
きる。Next, a second embodiment of a thin film transistor (TFT) using a polycrystalline semiconductor film according to the present invention for a channel portion will be described with reference to FIGS. FIG. 9 is a sectional view of the TFT of this embodiment. In this embodiment, the crystal grain boundary of the polycrystalline semiconductor is controlled by the step of the gate electrode provided on the substrate, and the channel portion of the TFT is formed on the polycrystalline silicon film. As shown in FIG. 9, a transparent insulating substrate 40 made of glass or the like is
A gate electrode 41 made of Mo, Ta, or the like is formed. Due to the gate electrode 41, 〜50 is formed on the substrate 40.
A step of 0 ° will be formed. This gate electrode 4
An insulating film 42 having a thickness of 1000 to 2000 Å is provided on the substrate 40 including the substrate 1 by a CVD method or the like. This insulating film 4
2 is provided with the above-described polycrystalline semiconductor film 43 of the present invention. The polycrystalline semiconductor film 43 is formed by forming an amorphous silicon film on the insulating film 42 by 500 to 1000 by a plasma CVD method or the like.
Å Obtained by forming and polycrystallizing by irradiation with excimer laser. After forming a 500-1000 ° P-doped n-type amorphous silicon or polycrystalline silicon film doped with phosphorus on the polycrystalline semiconductor film 43 by a plasma CVD method or the like, source and drain regions 45 and 46 are formed by patterning. You. Source and drain regions 4
Source and drain electrodes 47, 48 on
Is provided, and the TFT of this embodiment is obtained. In the TFT of this embodiment, similarly to the above-described embodiment, the position of the crystal grain boundary orthogonal to the channel is controlled so as to be located at the step, and the crystal grain boundary runs parallel to the channel portion. Accordingly, a structure in which a current flowing between the source and drain regions does not cross a crystal grain boundary is possible, and a high-speed operation TFT can be manufactured.
【0083】次に、この第2の実施例である薄膜トラン
ジスタの製造方法を図10(A)ないし図10(C)に
従い説明する。Next, a method of manufacturing the thin film transistor according to the second embodiment will be described with reference to FIGS. 10 (A) to 10 (C).
【0084】先ず透明絶縁性基板40上にゲート電極4
1となるCr,Mo,Ta等の金属層を蒸着、スパッタ
等を用いて〜500Å成膜し、この金属層をパターニン
グしてゲート電極41を形成する。その後、絶縁膜42
をCVD法、スパッタ法等を用い200〜600℃の温
度で1000〜2000Åの膜厚で成膜する。そして、
絶縁膜42の上に非晶質シリコン膜をPECVD法、L
PCVD法、スパッタ法、蒸着法等で基板温度100か
ら500℃で500〜1000Å形成する。次に、エキ
シマレーザ6を照射し非晶質シリコン膜を多結晶化し、
多結晶半導体膜43を形成する。この時のレーザエネル
ギー密度は150〜350mJ/cm2、基板温度は2
0〜400℃とする。この多結晶化により、多結晶化半
導体膜43は段差部分に結晶粒界15が位置するように
制御される(図10(A))。First, the gate electrode 4 is formed on the transparent insulating substrate 40.
A metal layer of Cr, Mo, Ta or the like to be 1 is formed to a thickness of about 500 ° by vapor deposition, sputtering or the like, and this metal layer is patterned to form a gate electrode 41. After that, the insulating film 42
Is formed at a temperature of 200 to 600 ° C. with a thickness of 1000 to 2000 ° by using a CVD method, a sputtering method or the like. And
An amorphous silicon film is formed on the insulating film 42 by PECVD, L
The substrate is formed at a temperature of 100 to 500 ° C. by 500 to 1000 ° by PCVD, sputtering, vapor deposition or the like. Next, the amorphous silicon film is irradiated with an excimer laser 6 to be polycrystallized.
A polycrystalline semiconductor film 43 is formed. The laser energy density at this time is 150 to 350 mJ / cm 2 , and the substrate temperature is 2
0 to 400 ° C. By this polycrystallization, the polycrystallized semiconductor film 43 is controlled so that the crystal grain boundary 15 is located at the step (FIG. 10A).
【0085】次に、図10(B)に示す工程では、多結
晶膜43上にP(燐)をドープしたn型非晶質シリコン
膜または多結晶シリコン膜をPECVD法,LPCVD
法、スパッタ法、蒸着法等で基板温度100〜500℃
で500〜1000Å形成する。このPをドープした半
導体膜をフォトリソ工程を経てパターニングし、ソー
ス、ドレイン領域45、46を作製する。Next, in the step shown in FIG. 10B, an n-type amorphous silicon film or a polycrystalline silicon film doped with P (phosphorus) is
Substrate temperature of 100 to 500 ° C by sputtering, sputtering, evaporation, etc.
500 to 1000 °. The P-doped semiconductor film is patterned through a photolithography process to form source and drain regions 45 and 46.
【0086】続いて、図10(C)で示す工程では、ソ
ース、ドレイン領域45、46上に真空蒸着法、スパッ
タ法によりAl,Cr等の金属膜を8000〜1500
0Å成膜する。そしてこの金属膜をフォトレジスト工程
により、パターニングすることによりソース、ドレイン
電極47、48を形成する。Subsequently, in a step shown in FIG. 10C, a metal film of Al, Cr, or the like is formed on the source and drain regions 45 and 46 by a vacuum evaporation method or a sputtering method in the range of 8000 to 1500.
0 ° is formed. Then, the metal film is patterned by a photoresist process to form source and drain electrodes 47 and 48.
【0087】これらTFTは、例えば、液晶表示装置
(LCD)に用いることができる。LCDでは高速性が
必要な周辺駆動部と、あまり速度が必要でない画素部に
分けられる。そこで周辺駆動回路に用いるTFTを本特
許で作製した、結晶粒界が制御されたTFTで高速化
し、画素部は歩留まり等を考えて従来の製法で作製する
ように構成すればよい。These TFTs can be used, for example, in a liquid crystal display (LCD). LCDs are divided into a peripheral drive unit that requires high speed and a pixel unit that does not require much speed. Therefore, the TFT used for the peripheral driving circuit may be configured to be manufactured by a conventional manufacturing method in consideration of the yield and the like by increasing the speed with the TFT manufactured in this patent and having a controlled crystal grain boundary.
【0088】[0088]
【発明の効果】本発明の多結晶半導体膜では、相隣接す
る、微小な平面を備えた領域間の段差上に設けられた結
晶粒界によって囲まれた結晶粒内の、結晶の配向を特定
方向に揃えることも可能となり、半導体膜中の電気的特
性を均一なものとすることができることとなる。According to the polycrystalline semiconductor film of the present invention, a connection formed on a step between adjacent regions having minute planes is formed.
Crystal grain surrounded by the crystal grains by boundaries, it becomes possible to align the orientation of the crystal in a specific direction, so that the electrical characteristics of the semiconductor film can be made uniform.
【0089】本発明の太陽電池によれば、基板の段差に
よって位置が特定されている結晶粒界が在る多結晶半導
体膜部分の表面に光キャリア収集のための集電極を設け
ることで、一般に光キャリアを再結合させ光電変換特性
に悪影響を及ぼすその結晶粒界近傍に集電極が設けら
れ、その様な再結合の発生を抑制することができる。According to the solar cell of the present invention, the collector electrode for collecting photocarriers is generally provided on the surface of the polycrystalline semiconductor film portion where the crystal grain boundary whose position is specified by the step of the substrate exists. A collecting electrode is provided in the vicinity of the crystal grain boundary that recombines the photocarriers and adversely affects the photoelectric conversion characteristics, so that occurrence of such recombination can be suppressed.
【0090】本発明の多結晶半導体膜を薄膜トランジス
タのチャンネル領域として用いれば、チャネル領域の多
結晶半導体膜部分には結晶粒界の存在しない状態を作る
ことができ、これによれば、従来のような粒界によるキ
ャリア走行の阻害がなくなり、スイッチング特性が良好
な素子得ることができる。When the polycrystalline semiconductor film of the present invention is used as a channel region of a thin film transistor, a state in which no crystal grain boundary exists in the polycrystalline semiconductor film portion of the channel region can be formed. An element having good switching characteristics can be obtained without obstruction of carrier traveling due to a large grain boundary.
【図1】図1の(A)ないし(D)は、本発明の多結晶
半導体膜の製造方法を工程別に示した素子構造の断面図
である。FIGS. 1A to 1D are cross-sectional views of an element structure showing a method of manufacturing a polycrystalline semiconductor film according to the present invention for each step.
【図2】図2の(A)及び(B)は、本発明の多結晶半
導体の平面図である。FIGS. 2A and 2B are plan views of a polycrystalline semiconductor of the present invention.
【図3】図3の(A)ないし(C)は、本発明の多結晶
半導体膜をpn接合型太陽電池に用いた実施例を工程別
に示した断面図である。FIGS. 3A to 3C are cross-sectional views illustrating an example in which a polycrystalline semiconductor film of the present invention is used for a pn junction type solar cell in each step.
【図4】図4の(D)及び(E)は上記実施例を工程別
に示した断面図である。4 (D) and 4 (E) are cross-sectional views showing the above-described embodiment in each step.
【図5】図5の(A)ないし(D)は、本発明の多結晶
半導体膜をpn接合型太陽電池に用いた第2実施例を工
程別に示した断面図である。FIGS. 5A to 5D are cross-sectional views showing a second embodiment in which the polycrystalline semiconductor film of the present invention is used for a pn junction type solar cell, in each step.
【図6】図6の(A)ないし(D)は、本発明の多結晶
半導体膜をpn接合型太陽電池に用いた第3実施例を工
程別に示した断面図である。FIGS. 6A to 6D are cross-sectional views showing a third embodiment in which the polycrystalline semiconductor film of the present invention is used for a pn junction type solar cell, according to each process.
【図7】図7の(A)及び(B)は、本発明の多結晶半
導体膜をチャネル領域に用いた薄膜トランジスタを示
し、(A)は断面図、(B)は平面図である。7A and 7B show a thin film transistor using a polycrystalline semiconductor film of the present invention for a channel region, FIG. 7A is a cross-sectional view, and FIG. 7B is a plan view.
【図8】図8の(A)ないし(C)は、本発明の多結晶
半導体膜をチャネル領域に用いた薄膜トランジスタを工
程別に示した断面図である。FIGS. 8A to 8C are cross-sectional views showing a thin film transistor using a polycrystalline semiconductor film of the present invention for a channel region in each step.
【図9】本発明の多結晶半導体膜をチャネル領域に用い
た薄膜トランジスタを示す断面図である。FIG. 9 is a cross-sectional view illustrating a thin film transistor using the polycrystalline semiconductor film of the present invention for a channel region.
【図10】図10の(A)ないし(C)は、本発明の多
結晶半導体膜をチャネル領域に用いた薄膜トランジスタ
を工程別に示した断面図である。FIGS. 10A to 10C are cross-sectional views illustrating a thin film transistor using a polycrystalline semiconductor film of the present invention for a channel region in each step.
1 基板 2 レジスト 3 微小領域 4 段差 5 非晶質半導体膜 8 結晶粒界 Reference Signs List 1 substrate 2 resist 3 minute region 4 step 5 amorphous semiconductor film 8 crystal grain boundary
───────────────────────────────────────────────────── フロントページの続き (72)発明者 綾 洋一郎 大阪府守口市京阪本通2丁目5番5号 三洋電機株式会社内 (56)参考文献 特開 平5−275333(JP,A) 特開 平5−275451(JP,A) 特開 平1−239094(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/18 H01L 21/20 H01L 21/34 H01L 21/36 H01L 21/84 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoichiro Aya 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP 5-275333 (JP, A) JP Hei 5-275451 (JP, A) JP-A 1-239094 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/18 H01L 21/20 H01L 21/34 H01L 21 / 36 H01L 21/84
Claims (10)
備えた領域を多数個備え、隣接する該領域間に結晶粒界
制御用の段差が設けられた基板と、この基板上に基板表
面の凹凸形状を反映して膜内部に位置制御された結晶粒
界を有して形成された多結晶半導体膜と、からなり、上
記多結晶半導体膜の膜内における結晶粒界が、上記基板
の段差上に設けられていることを特徴とする多結晶半導
体膜。1. A substrate having a large number of irregularities on its surface, a large number of regions having minute planes, and a step for controlling a grain boundary between adjacent regions, and a substrate on the substrate. and a polycrystalline semiconductor film which is formed with a position-controlled crystal grain boundaries inside film reflecting the uneven shape of the surface consists of the upper
The crystal grain boundary in the polycrystalline semiconductor film is
A polycrystalline semiconductor film, which is provided on a step .
00Å以下とする請求項1に記載された多結晶半導体
膜。2. The height difference caused by the step is 30 ° or more and 5 ° or more.
2. The polycrystalline semiconductor film according to claim 1, wherein the thickness is not more than 00 ° .
面でほぼ90度の角度に形成されている請求項2に記載
の多結晶半導体膜。3. The surface shape of the uneven portion due to the step is cut off.
3. The method according to claim 2, wherein the plane is formed at an angle of about 90 degrees.
Polycrystalline semiconductor film.
備えた領域を多数個備え、隣接する該領域間に結晶粒界
制御用の段差が設けられた基板と、この基板上に基板表
面の凹凸形状を反映して位置制御された結晶粒界を含み
内部に半導体接合を有する多結晶半導体膜と、からな
り、上記多結晶半導体膜の膜内における結晶粒界が、上
記基板の段差上に設けられていることを特徴とする半導
体装置。4. A fine plane by providing a large number of irregularities on the surface.
A large number of provided regions, and a grain boundary between the adjacent regions.
A board provided with a step for control, and a board
Includes grain boundaries whose position is controlled to reflect the surface irregularities
A polycrystalline semiconductor film having a semiconductor junction inside;
The crystal grain boundary in the polycrystalline semiconductor film is
A semiconductor provided on a step of the substrate.
Body device .
備えた領域を多数個備え、隣接する該領域間に結晶粒界
制御用の段差が設けられた第1電極としての基板と、こ
の基板上に基板表面の凹凸形状を反映して位置制御され
た結晶粒界を含む一導電型の多結晶半導体膜と、この多
結晶半導体膜に形成された他導電型の半導体層と、この
半導体層上に形成された透明電極と、を備え、上記多結
晶半導体膜の膜内における結晶粒界が、上記基板の段差
上に設けられ、上記結晶粒界に位置する透明電極上に集
電極を設けていることを特徴とする太陽電池。 5. A minute plane by providing a large number of irregularities on the surface.
A large number of provided regions, and a grain boundary between the adjacent regions.
A substrate as a first electrode provided with a step for control;
Position is controlled on the substrate by reflecting the unevenness of the substrate surface.
A polycrystalline semiconductor film of one conductivity type including a crystal grain boundary,
A semiconductor layer of another conductivity type formed on the crystalline semiconductor film;
A transparent electrode formed on a semiconductor layer.
The crystal grain boundaries in the single crystal semiconductor film are
On the transparent electrode located at the crystal grain boundary.
A solar cell comprising an electrode.
に更に集電極を設けたことを特徴とする請求項5に記載
の太陽電池。 6. On a transparent electrode located between steps of the substrate.
6. The device according to claim 5, further comprising a collector electrode.
Solar cell.
備えた領域を多数個備え、隣接する該領域間に結晶粒界
制御用の段差が設けられた基板と、この基板上に基板表
面の凹凸形状を反映して位置制御された結晶粒界を含む
一導電型の多結晶半導体膜と、この多結晶半導体膜上に
形成された真性非晶質半導体層と、この真性半導体層上
に形成された他導電型の非晶質半導体とからなり、上記
多結晶 半導体膜の膜内における結晶粒界が、上記基板の
段差上に設けられていることを特徴とする半導体装置。7. A substrate provided with a large number of regions having minute planes by providing a large number of irregularities on the surface, and a step for controlling a grain boundary between adjacent regions, and a substrate provided on the substrate. reflecting the uneven surface position-controlled grain boundary of including
A polycrystalline semiconductor film of one conductivity type, and
Intrinsic amorphous semiconductor layer formed and on the intrinsic semiconductor layer
Consisting of an amorphous semiconductor of another conductivity type formed in
The crystal grain boundaries in the polycrystalline semiconductor film are
A semiconductor device provided on a step .
備えた領域を多数個備え、隣接する該領域間に結晶粒界
制御用の段差が設けられた第1電極としての基板と、こ
の基板上に基板表面の凹凸形状を反映して位置制御され
た結晶粒界を含む一導電型の多結晶半導体膜と、この多
結晶半導体膜上に形成された真性非晶質半導体層と、こ
の真性非晶質半導体層上に形成された他導電型の非晶質
半導体層と、この非晶質半導体層上に形成された透明電
極と、を備え、上記多結晶半導体膜の膜内における結晶
粒界が上記基板の段差上に設けられ、上記結晶粒界に位
置する透明電極上に集電極を設けていることを特徴とす
る太陽電池。 8. A fine plane by providing a large number of irregularities on the surface.
A large number of provided regions, and a grain boundary between the adjacent regions.
A substrate as a first electrode provided with a step for control;
Position is controlled on the substrate by reflecting the unevenness of the substrate surface.
A polycrystalline semiconductor film of one conductivity type including a crystal grain boundary,
An intrinsic amorphous semiconductor layer formed on the crystalline semiconductor film;
Of other conductivity type formed on intrinsic amorphous semiconductor layer
A semiconductor layer and a transparent electrode formed on the amorphous semiconductor layer;
And a crystal in the polycrystalline semiconductor film.
A grain boundary is provided on the step of the substrate and located at the crystal grain boundary.
The collector electrode is provided on the transparent electrode to be placed.
Solar cells.
に更に集電極を設けたことを特徴とする請求項8に記載
の太陽電池。9. On a transparent electrode located between steps of the substrate.
9. The device according to claim 8, further comprising a collector electrode.
Solar cells.
を備えた領域を複数個備え、隣接する該領域間に結晶粒
界制御用の段差が設けられた基板と、この基板上に基板
表面の凹凸形状を反映して位置制御された結晶粒界を含
む多結晶半導体膜と、上記結晶粒界に挟まれた領域をチ
ャネル領域とし、そのチャネル領域を挟んで形成された
ソース、ドレイン領域と、からなり、上記多結晶半導体
膜の膜内における結晶粒界が、上記基板の段差上に設け
られていることを特徴とする半導体装置。10. A substrate provided with a plurality of regions provided with a plurality of irregularities on the surface and having a minute plane, and a step for controlling a grain boundary provided between adjacent regions, and a substrate provided on the substrate. A polycrystalline semiconductor film including a crystal grain boundary whose position is controlled by reflecting the unevenness of the surface, and a region sandwiched by the crystal grain boundary are checked.
Channel region and the channel region
A source and drain region, wherein the polycrystalline semiconductor is
A crystal grain boundary in the film is provided on the step of the substrate.
A semiconductor device characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11817394A JP3229750B2 (en) | 1994-02-22 | 1994-05-31 | Polycrystalline semiconductor film, semiconductor device and solar cell using the same |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6-24329 | 1994-02-22 | ||
JP2432994 | 1994-02-22 | ||
JP11817394A JP3229750B2 (en) | 1994-02-22 | 1994-05-31 | Polycrystalline semiconductor film, semiconductor device and solar cell using the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07288227A JPH07288227A (en) | 1995-10-31 |
JP3229750B2 true JP3229750B2 (en) | 2001-11-19 |
Family
ID=26361822
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP11817394A Expired - Fee Related JP3229750B2 (en) | 1994-02-22 | 1994-05-31 | Polycrystalline semiconductor film, semiconductor device and solar cell using the same |
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JP (1) | JP3229750B2 (en) |
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TW317643B (en) | 1996-02-23 | 1997-10-11 | Handotai Energy Kenkyusho Kk | |
JP4027449B2 (en) * | 1996-02-23 | 2007-12-26 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor thin film and semiconductor device |
GB2358081B (en) | 2000-01-07 | 2004-02-18 | Seiko Epson Corp | A thin-film transistor and a method for maufacturing thereof |
JP2008252068A (en) | 2007-03-08 | 2008-10-16 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method for manufacturing same |
JP5371144B2 (en) | 2007-06-29 | 2013-12-18 | 株式会社半導体エネルギー研究所 | Semiconductor device, method for manufacturing semiconductor device, and electronic device |
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1994
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Also Published As
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JPH07288227A (en) | 1995-10-31 |
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