JP3227600B2 - DA converter that can realize high accuracy and high temperature stability without fine adjustment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the electric field. In addition, fine adjustment of resistors and the like is not required, and high accuracy and high temperature stability can be realized.
It relates to the A converter. Further, the present invention relates to an AD converter realized by using the DA converter.

[0002]

2. Description of the Related Art The configuration of a conventional DA converter is as follows. Originally, a DA converter converts a digital quantity into an analog quantity, and usually, a binary number is often used as a digital display method. Therefore, this will be described. First, in order to convert a digital quantity into an analog quantity, a voltage or current corresponding to each digital quantity is prepared. In the case of a binary number, a carry occurs when it becomes 2 in a certain place due to its nature.
The voltage or current corresponding to each position is weighted twice. Then, by adding a voltage or a current corresponding to the digit of 1 to the given digital amount, an analog amount corresponding to the digital amount is output. FIG. 2 shows a principle diagram of a general DA converter. Note that for simplicity of explanation, 4
The example of the bit DA converter was shown. The most important issue here is how to accurately weight currents or voltages. The key point that determines the linearity of the DA converter is here.

As a typical conventional technique, a method using an R-2 · R resistance ladder network as shown in FIG. 3 has been generally used. The operation principle will be described briefly. FIG. 3 shows an example of a 4-bit CMOS DA converter. First, at the branch point, Ic is divided into two parts. For the sake of simplicity, the on-resistances of the CMOS change-over switches Sa, Sb, Sc, Sd are negligibly small, while the off-resistances are infinite. Assume it is large. Further, since the potential of the inverting input terminal of the operational amplifier 1 is at the ground level, the potential of the switch Sd is at the ground level regardless of which side the switch Sd is turned on. Therefore, on the right side of the branch point, only 2
It is the same as two resistors of R are connected in parallel. Therefore, the current shunts equally. (Shown in FIG. 3). That is, Equation 1 is obtained.

On the right side of the branch point, the combined resistance between the branch point and the ground is R. A similar argument holds at the bifurcation point, as shown in Equation 2. Similarly, Ib and Ia are as shown in Expressions 3 and 4. In this way, the current flowing through the changeover switches Sa, Sb, Sc, and Sd is weighted twice.

In this case, the changeover switch Sa corresponds to the most significant bit, and the changeover switch Sd corresponds to the least significant bit. That is, when the most significant bit becomes 1, the changeover switch Sa is turned on to the operational amplifier side. For example, if the digital code 1101 is given, the changeover switches Sa, Sb, and Sd are connected to the inverting input terminals of the operational amplifier, and the currents Ia, I
b and Id are added by an operational amplifier and current-voltage converted.
That is, V _OUT is as shown in _Expression 5. Further, the changeover switch Sc is turned on to the ground side. However, this circuit assumes the following. (1) The resistance value and the temperature coefficient of the resistance ladder network are relatively well matched so that a specified accuracy can be achieved within a specified temperature range. (2) The ON resistance of the CMOS switch can be ignored.

Actually, when a circuit as shown in FIG. 3 is to be formed on a silicon chip, silicon chromium is usually used as a resistor. Almost everything is completed, +
It falls within -10 ppm / ゜ C. However, the relative accuracy of the resistor is only about + -0.1%. In addition, the on-resistance of the CMOS switch (2) cannot be ignored. Therefore, conventionally, the problems (1) and (2) have been solved by the following method. (1) In order to increase the relative accuracy of the silicon chrome resistor on the silicon chip, a part of the resistor is burned off with a laser beam, thereby finely adjusting the resistance value of the resistor. (2) In order to minimize the influence of the ON resistance of the CMOS switch, the ON resistance of the CMOS switch is weighted twice in accordance with the current flowing therethrough. This equalizes the voltage drop of each CMOS switch. The above is the conventional general technology.

[0007]

However, the prior art as described above has the following disadvantages. (1) When mass-producing a DA converter having a small non-linearity error, for example, ± 0.1% or less, the yield is poor unless fine adjustment of the resistor of the resistor ladder network by a laser beam is performed. Become. That takes a lot of time. Also, the equipment for this is expensive. Therefore, the unit price inevitably increases. Even if the resistor of the resistance ladder network is finely adjusted by the laser beam, the fine adjustment becomes difficult if a DA converter having a small nonlinearity error is to be manufactured. Therefore, it takes time and is not suitable for mass production. (2) Even if the resistance of the resistor ladder network is finely adjusted by a laser or some other method as in the above (1) to make the relative accuracy of the resistors uniform, the current technology does not provide the resistance ladder network. The relative temperature coefficient between the resistors is about 10 ppm / ° C. Due to the unevenness of the temperature coefficient, for example, the resistance between the resistors of the resistor ladder network is changed while the temperature changes to 10 ° C or 20 ° C. Relative accuracy cannot be maintained within the specified range. Therefore, when the ambient temperature changes, the non-linearity error increases, and the specified accuracy cannot be maintained. For this reason, this further reduces the yield. This phenomenon is particularly problematic in 12-bit or more DA converters. (3) The fine adjustment by the laser beam is performed before the chip is packaged in the final stage of the completion of the chip. At this stage, the protective film of the silicon oxide film is already formed on the surface of the silicon chip. ing.
In that state, a part of the resistor on the silicon chip is burned off by a laser beam for fine adjustment, but at the same time, the protective film on it is burned off together with the resistor. Will be lost. Of course, the silicon chip is sealed and shipped as a DA converter, but if any impurities such as moisture remain in the sealed space during manufacturing, the element is energized and destroyed during use. Corrosion starts to progress from the place of the protected protective film. As a result, the resistance value changes and the specified relative accuracy cannot be maintained. In other words, there are many cases where the accuracy becomes poor while some DA converters are used.

Further, in a plastic package element, moisture easily reaches a silicon chip through a lead wire or the like. However, if the protective film is perfect,
It is known that normal operation is performed for a considerably long time even if moisture reaches a silicon chip. However, it is clear that if the protective film is torn, corrosion will easily start there.

On the other hand, other types of DA converters also finely adjust a resistor or the like with a laser beam or the like in order to weight current or voltage. The above is the current technology and problems.

The present invention has been devised in order to solve these problems. In addition, by solving the above-mentioned problems, an inexpensive and reliable high-precision DA converter, and an inexpensive and reliable high-precision A / D converter manufactured using the same. This implements a -D converter.

[0011]

Now, the principle and technique of the present invention, which is means for solving the above-mentioned problems, will be described below. As can be understood from the above discussion, the biggest problem in realizing a high-precision DA converter is how to accurately realize the weighting of an analog amount corresponding to each digital input. . Also, depending on how accurately the weighting can be realized within the operating temperature range of the element, the DA converter or A
Whether the non-linearity error, which is an important definition item of the error of the D converter, or the differential non-linearity error is determined. However, it is already known that a given voltage can be accurately divided equally using switched capacitor technology. The circuit diagrams are shown in FIGS. 4a and 4b.

The symbols in FIGS. 4A and 4B are described below. E _REF ··· Reference voltage sources S ₁ , S ₂ ··· Changeover switches C ₁ and C ₂ ··· Capacitors a to f ··· Terminals of changeover switches S ₁ and S ₂ V _OUT. ... Output terminals

Here, the reference voltage source E _REF is _equally divided. The procedure will be described with reference to FIGS. 4A and 4B. First, it is assumed that the circuit state is as shown in FIG. 4A as an initial state, and the electric charge of each of the capacitors C ₁ and C ₂ is zero. Then the capacitor _C 1 as in Figure 4b,
Connected in series with C ₂ between the reference voltage source _{E REF} and ground. Then, when the capacitors C ₁ and C ₂ are fully charged, as shown in FIG. 4A, the capacitors C ₁ and C _2
Is disconnected from the reference voltage source E _REF and the capacitor C ₁
The high potential side to each other of each of C _2, or by connecting the terminal on the low potential side to each other and connected in parallel with. Thereafter, when it is considered that the charge transfer of the capacitors C ₁ and C ₂ is sufficiently settled, the operation returns to FIG. 4B again and the same operation is repeated. That is, the operation in which the capacitors C ₁ and C ₂ are connected in series and connected between the reference voltage source E _REF and ground and the reference voltage source E
_The operation of disconnecting the capacitors C ₁ and C ₂ from _REF and connecting them in parallel is alternately repeated.

Next, the above operation will be described in more detail.
First, to describe the operation of the switch S ₁ and S ₂ switch is as follows. 1. The changeover switches S ₁ and S ₂ are assumed to be break-before-make switches. That is, at the changeover switch S _1, at any time, terminals a and c shall never simultaneously connected. Also,
Similarly, at the changeover switch S _2, at any time, it is assumed never terminal d and a terminal f are simultaneously connected. 2. The changeover switches S ₁ and S ₂ are simultaneously switched, and when the changeover switch S ₁ is connected to the terminal a,
Switch S ₂ switch is in principle that it is connected to the terminal d. Switch S ₂ switch when the switch S ₁ is connected to the terminal c side switching similarly in principle that it is connected to the terminal f side. 3. Also in the any instant, the switch S ₁ switch is connected to the terminal a, the switch S ₂ switch is assumed never connected to the terminal f side. Similarly, switch S ₁ switch even in a any instant is connected to the terminal c side, the switch S ₂ switch is assumed never connected to the terminal d side.

Under the above conditions, the changeover switches S ₁ and S ₂ are repeatedly switched as follows. 1. Switch connects the switch S ₁ to the terminal a, the switching to connect the switch S ₂ to the terminal d. In this state, the capacitor C ₁ and C ₂ are connected in series, moreover its ends is connected to the ground and a reference voltage source E _REF. And
Charge and discharge are performed. 2. When the charge and discharge of the charges have settled down sufficiently,
The switch _{S 1} to the terminal c side switching, the switch _{S 2}
Is switched to the terminal f side. Then, the capacitors C ₁ and C ₂ are disconnected from the reference voltage source E _REF , the terminals of the capacitors C ₁ and C ₂ having high potentials are connected, and the terminals of low potentials are connected. . Procedure 2. Condenser _C 1, _{C 2} becomes parallel connected by, charges accumulated in capacitors _{C 1} and _{C 2} are redistributed among the capacitors _C 1, _{C 2.} Once the redistribution of the charge has settled sufficiently, once again in procedure 1. Return to and then And 2. Repeat the above steps.

Now, it is known that the potential seen from the ground level of the output terminal _{VOUT in} FIG. 4A or FIG. 4B gradually converges to E _REF / 2 by the above method. I would like to explain the reason using mathematical formulas below. First, the switch S ₁ switch as in Figure 4a is connected to the terminal c, consider a state in which the switch S ₂ switch is connected to the terminal f. At this time, capacitors C ₁ and C
_Second charge is assumed to both be zero. However, here, factors such as the on-resistance of the changeover switch, the off-leakage current, and the leakage current of the substrate are not considered. That is, the circuit is considered in an idealized form.

[0017] Next, the switch _{S 1} to the terminal a side switching,
It switches the switch S ₂ to the terminal d side switching, the circuit of Figure 4b. Thereafter, it is assumed that charge and discharge are performed, and the charge transfer is sufficiently settled. The charge of the capacitor _{C 1} in this case _{Q 11,} the charge of capacitor _{C 2} and _{Q 21.} At this time, Equation 6 holds. In _{addition, Q 11} is as shown in the number 7. Next, define the _{Q 1} as the number 8. Then, _{Q 1} is as shown in the number 9. Here, since the capacitors C ₁ and C ₂ are not always equal, the voltage of the capacitor C _{1 and} the voltage of the capacitor C ₂ are not necessarily equal.

Next, the switch _{S 1} to the terminal c side switching,
It switches the switch S ₂ to the terminal f side switching, the circuit of Figure 4a. In this case, so that the voltage of the capacitor _{C 1} and _{C 2} are equal, the charge _{Q 11} of the capacitor _{C 1} and _{C 2}
And Q ₂₁ are redistributed. It is assumed that the redistribution is performed and the charge transfer of the capacitors C ₁ and C ₂ is sufficiently settled. The charge of the capacitor C ₁ at that time is Q ₁₁ ′,
The charge of the capacitor _{C 2} and _{Q 21} '. Q ₁₁ ′ and Q ₂₁ ′ are as shown in Equations 10 and 11. At this time, since the capacitors C ₁ and C ₂ are not always equal, the voltage across the capacitor C ₁ or C ₂ is set to E.
'When, 2 · _{E 1' 1} is not necessarily equal to _{E REF.}

Next, the switch _{S 1} switch again to the terminal a side, 4 switches the switch _{S 2} to the terminal d side switching FIGS b
Circuit. Then, at this time, the capacitors C ₁ and C
Since the _second series voltage 2 · _{E 1} 'it is not necessarily equal to _{E REF,} to be equal to _{E REF,} charging or a capacitor _{C 1} and _{C 2,} the discharge is performed. Since the capacitors C ₁ and C ₂ are connected in series, the amount of movement of the charge at this time is limited by the capacitors C ₁ and C 2.
Both become equal in ₂ . The amount of charge movement at this time is defined as ΔQ ₂ . However, the polarity of ΔQ ₂ is positive when the capacitor C ₁ or C ₂ is charged.
E _REF is expressed as in Equation 12. Solving this for ΔQ ₂ gives Equation 13. Here, ΔQ ₂ is as shown in Expression 14 from Expressions 10 and 11. When the sum of the charge of the capacitor C ₁ and capacitor C ₂ when the movement of the charge is settled sufficiently and Q _2, Q ₂ is as shown in Equation 15. In addition, Q ₂ is given by Expression 16 from Expression 14.

In the same manner, the changeover switch S _{1 is} again operated.
To c side, at the same time switching the switch S ₂ to the f side switching,
The switch S ₁ again switched at the movement of charges is sufficiently settled on a side, it switches simultaneously switch S ₂ to the d side switching. When the sum of the charges of the capacitors C ₁ and C ₂ at the time when the movement of the charges has sufficiently settled is Q ₃ , Q
₃ becomes as shown in Expression 17. Here, α is defined as in Expression 18. Also, in the same manner as in the procedure 1. And procedure 2. A repeating n-th to the changeover switch S ₁ is the terminal a, the switch S ₂ switch is switched to the terminal d, the sum of the charge of the capacitor C ₁ and C ₂ when the movement of charges settled enough to Qn, Qn is Similarly, Equation 19 is obtained. Here, since the value of α is 0 ≦ α <1, if the charge Qn when n → ∞ is changed from Qn → ∞, Qn becomes as shown in Expression 20. Therefore, when the output voltage V _{OUT changes} from n → ∞, E
Converges to _REF / 2.

Thus, by using the circuit as shown in FIG. 4 and by repeatedly switching the changeover switches S ₁ and S ₂ , the reference voltage source E
It can be seen that _REF is exactly _equally divided. Now, it can be seen that the method using the circuit of FIG. 4 has the following features. 1. Regardless of the value of the capacitors C ₁ and C ₂ , the reference voltage source E _REF can be accurately divided equally. Therefore, unlike the case where the current value is weighted using a resistor, there is no need to perform fine adjustment using a laser beam or the like in order to make the resistor values uniform. 2. Regardless of the values of the capacitors C ₁ and C ₂ , the fact that the reference voltage source E _REF can be _equally divided accurately means that if the capacitance values of the capacitors C ₁ and C ₂ change with temperature. Nevertheless, this means that the reference voltage source E _REF is nevertheless exactly _equally divided. In other words, this means that the reference voltage source can always be accurately and equally divided without being affected by the temperature change. 3. The reference voltage source E _REF is accurately divided _equally and the output terminal V
_It takes a certain amount of time for _OUT to converge to E _REF / 2. 4. Until the voltage at the output terminal V _OUT converges to E _REF / 2, a current required for charging and discharging the capacitors C ₁ and C ₂ flows in the circuit of FIG. However, once the voltage of the output terminal V _OUT converges to E _REF / 2, only a small current such as an off-leak current of the changeover switch, a leak current of the capacitor, and a leak current of the substrate flows unless there is any disturbance factor. These currents are less than a few nanoamps, and it can be considered that substantially no current flows.

Thus, by using the circuit as shown in FIG. 4, it can be seen that the reference voltage source E _REF is exactly bisected even if the capacitors C ₁ and C ₂ are not equal. Therefore, using a circuit as shown in FIG.
It can be seen that the following advantages are obtained by weighting the analog amount corresponding to each bit of the digital input of the DA converter. 1. There is no need to make fine adjustments to the resistor or the like, unlike the case where a DA converter is manufactured using a resistor or the like as in the prior art. Therefore, the following advantages arise. 1) The trouble of fine adjustment by a laser beam or the like is omitted, and the time required for manufacturing is shortened. 2) If an attempt is made to realize a highly accurate DA converter, it is difficult to make fine adjustments to this resistor, and the yield will be poor. However, using this method does not require fine adjustment, and the yield is determined by the management of the semiconductor manufacturing process and the design of the mask pattern. Therefore, the yield is greatly improved. 3) Since it is not necessary to burn out the resistor for fine adjustment of the resistor, the protection film made of the silicon oxide film on the resistor is not broken. Therefore, reliability is improved. 2. In the conventional technology, the relative value of a resistor or the like changes due to a temperature change, which affects a nonlinearity error or a differential nonlinearity error.However, by using the circuit of the present invention, the nonlinearity error due to temperature, Alternatively, the influence on the differential nonlinearity error is eliminated. 3. The reference voltage source E _REF can be accurately divided equally. Further, there are the following disadvantages. 1. When trying to take the load current from the output terminal V _OUT ,
The reference voltage source E _REF will not be _equally divided. The present invention intends to configure a DA converter using these features.

By the above discussion, it has been found that the use of the circuit shown in FIG. 4 enables accurate weighting of the analog voltage corresponding to each digital bit of the DA converter. Therefore, next, the analog voltage corresponding to the place where 1 stands must be added in accordance with the digital input code. However, one thing to notice here is that most of the conventional DA converters are of the current addition type. Therefore, as shown in FIG. 3, it is difficult to add the current using an operational amplifier. I can do it. However, in the circuit of FIG. 4 according to the present invention, "current" is not weighted, but "voltage" is weighted. Therefore, in a manner different from the method of the conventional DA converter, it is necessary to add an analog quantity corresponding to each position of the digital input corresponding to the digital input code. Of course, using a resistor to convert the "analog" voltage corresponding to each digit of the digital into a current and summing it with an operational amplifier has no meaning. This is because, in that case, matching between the resistors still becomes a problem. Therefore, it is understood that a special contrivance is required in configuring the DA converter using the circuit of FIG. Therefore, the following method was devised. FIG. 5 shows the principle. For simplicity, an example of a 2-bit DA converter is shown.

First, three types of voltages can be generated by using one circuit of FIG. That is, the reference voltage is E _REF , E _REF / 2, and 0 [V]. If a 1-bit DA converter is to be realized, 0 [V] and E _REF / 2 [V] may be used. Now, in order to realize a 2-bit DA converter, it is necessary to generate the following voltages. 3.E
_REF / 4 [V], _EREF / 2 [V]. E _REF / 4
[V], 0 [V] First, E _REF / 2 [V] and 0 [V]
Can be realized if there is one circuit in FIG. Further, E
_{In order to generate} a voltage of _REF / 4 [V], another circuit shown in FIG. 4 is brought and used as a second circuit. The voltage E _REF / 2 [V] between the ground output from the first circuit and the output terminal V _{OUT1 is equally} divided by the second circuit. Therefore, the voltage of the output terminal V _OUT2 of the second circuit is
E _REF / 4 [V]. Furthermore, 3 ・ E _REF / 4
In order to obtain the voltage [V], the ground of the second circuit is connected to the output terminal V _OUT1 of the first circuit, and E _REF / 2
Shift to [V]. Then, the potential difference between E _REF / 2 [V] and the reference voltage E _REF [V] is equally divided. By doing so, a voltage of 3 · E _REF / 4 [V] is obtained.

[0025]

FIG. 5 shows that the changeover switches K ₁ and K ₂ correspond to the most significant bits of the digital input, the changeover switch K ₁ is connected to the terminal m, and the changeover switch K ₂ is connected to the terminal m. The state connected to the p side corresponds to the state where the digital input of the most significant bit is 1. The state where the switch K ₁ and K ₂ switch is connected to the opposite terminal is a digital input of the most significant bit corresponds to the state of 0.
The switch K ₁ and K ₂ switch has a mechanism that switches in conjunction. Similarly, the switch _{K 3} switching,
Corresponds to the least significant bit, the state in which the changeover switch K ₃ is connected to the terminal s side, the digital input of the least significant bit corresponds to one state. In addition, the change-over switch _{K 3}
The state where is connected to the terminal u corresponds to the state where the digital input of the least significant bit is 0. Here, the switches S ₁ switch to S _4, a switch for the weighting of the analog voltage, periodically switched conjunction with. Further, the from _{S 1} to _{S 4,} from _{K 1} to _{K 3} is a changeover switch Blake Bifoa-make.

Thus, a 2-bit DA converter can be realized. Similarly, by connecting the circuits of FIG.
It is also possible to realize an -A converter.

[0027]

FIG. 1 shows an example of an actual circuit of a 4-bit DA converter. FIG. 1 is described below. E _REF ····· Reference voltage source A ₁ ····· Op amp C ₁ to C ₈ ··· 1 [μF] capacitor S ₁ to S ₈ ··· Voltage equalization circuit ... break Bifoa-make switching switches from the switch K ₁ switching Blake Bifoa-make up K ₇ use, corresponds to each position digital input bits. Here, the S ₁ to S ₈ are changeover switch for voltage equal division circuit, periodically switched conjunction with. Also,
K ₁ and _K 2, _{K 3} and _K 4, _{K 5} and _{K 6} are switched in conjunction with each other.

[0028] Next, the following correspondence between the changeover switch and the digital input bits from K ₁ to K _{7. K 1,} K 2 ···· bit1 (uppermost _{bit) K 3, K 4 ····} bit2 K 5, K 6 ···· bit3 K 7 ······· bit4 ( lowest bit) These changeover switches can be constituted by a reed relay, a semiconductor switch, or the like, but it is considered appropriate to realize them by FETs.

A DA converter as shown in FIG.
It was confirmed that DA conversion was basically successfully performed by using a changeover switch. However, it turned out that there was one problem here. That is, a large spike voltage of 1 to 2 V is generated at the output terminal, being superimposed on a DC voltage corresponding to a digital input code. This phenomenon is undesirable, and even if D / A conversion is accurately performed, the spike voltage becomes a kind of large noise. Therefore, it is necessary to devise a technique for minimizing the spike voltage. The reason why such a spike voltage is generated will be considered with a simple model. In this case, an N-channel MOS-FET switch is used as a changeover switch. For simplicity, an example of a 2-bit DA converter will be described. FIG. 5 is a circuit diagram thereof. In this case, however, the actual configuration of each changeover switch is as shown in FIG. In FIG. 7, it is assumed that the condition of the changeover switch described above is satisfied. That is, two MOS-FET in the switching switch, _{F 1} and _{F 2} are simultaneously turned on and becomes possible voltage across each gate and the source of so no V
_GS shall be controlled.

For simplicity, it is now assumed that the digital input code is "00". The circuit state at that time is as shown in FIG. By the way, if the changeover switches S ₁ , S ₂ , S ₃ , S ₄ are perfect, there is no problem. In the case of a MOS-FET, the gate current is on the order of picoamps and can be ignored. Further, the off-state resistance is very large and there is no practical problem. Further, in the circuit shown in FIG. 5, once settled into an equilibrium state as described above, in principle, no current flows through the voltage equalizing capacitors C ₁ , C ₂ , C ₃ , and C ₄ . Therefore, at this point, the voltage drop due to the on-resistance has no significant effect. However, there is a big problem here. It is FET
The gate-source capacitance _{C GS,} the gate-drain capacitance _{C GD,} a further drain-source capacitance _{C DS.}

Now, in order to turn on or off the FET, the gate-source voltage V _GS must be changed. However, by doing so, the source side through the gate-source capacitance C _GS, and the current flows to the drain side through the gate-drain capacitance C _GD.
This current produces a spike voltage at the output terminal. This will be described below. First, _{assuming that} the change in the gate-source voltage V _GS is ΔV _GS , the amount of charge that moves to the source side through the gate-source capacitance C _{GS due} to the change in V _GS is ΔQ _G s, and Assuming that the amount of charge moving to the drain side through the drain-to-drain capacitance C _GD is ΔQ _GD , ΔQ _GS is as shown in Expression 21. ΔQ _GD is as shown in Expression 22. Here, ΔV _DG
Is a variation of the drain-gate voltage that varies with changes in V _GS. Further, the gate-source capacitance C _GS
The current flowing from the gate to the source of the FET through I
_CGS, and the current flowing from the gate to the drain of the FET through the gate-drain capacitance C _GD is I
_{Assuming CGD} , I _CGS is as shown in _Equation 23, and I _CGD is as shown in _Equation 24. However, for simplicity, it is assumed that the capacitance of the FET is constant without depending on the gate voltage or the like.

[0032] Here, we consider the FET to turn on or off between the terminals b and the terminal c of the switch _{S 1} switch of FIG. Here, it is assumed that the drain of the FET is connected to the terminal b and the source is connected to the terminal _C. Now, consider the effect of the current _ICGS flowing from the gate to the source on the circuit. And flowing all the charge transferred to the source side to the capacitor C ₂ by the current, it changes in the voltage across the capacitor C ₂ caused by the Δ
If V _C2 , ΔV _C2 is as shown in Expression 25. Well, here, the capacitor C ₂ is an condenser used to accurately bisects the original voltage is that voltage bisecting circuit ideally should be the original ends of the capacitor C ₂ at that time When the voltage and _{V C2, V C2} and ΔV
The ratio ΔV _C2 / _{V C2} of _C2 is in as number 26. Now, assuming that C _{GS <<} C ₂ and that the absolute values of ΔV _GS and V _C2 are not so different, ΔV _C2 / V
_C2 is as shown in Expression 27, and the effect on V _C2 through C _GS due to the change in the gate-source voltage V _GS can be substantially ignored. Therefore, for the sake of simplicity, the first equal division circuit is simplified here and is considered as a constant voltage source. FIG. 6 shows the circuit.

By the way, similarly to the above-mentioned discussion, the influence of the change in the gate-source voltage of the FET on the voltage across the capacitors C ₃ and C ₄ can be ignored. However, in this circuit, there are resistors R _K1 and R _K2 corresponding to the on-resistances of the changeover switches K ₁ and K ₂ corresponding to the most significant bit of the digital input. The above-mentioned _ICGS or _ICGD flows into these resistors. This causes a voltage drop. Moreover, this voltage drop is
It occurs while the gate-source voltage of the ET is changing, that is, when the FET switch is switched, and is observed as a spike voltage.

Further, the drain and the source are provided between the drain and the source.
Source-to-source capacitance _CDS exists. By switching the changeover switch, the voltage between the drain and the source changes. At this time, the _CDS is charged and discharged. Current flows to the drain side or the source side by the charging and discharging of this charge, which causes these currents to generate a flow spike voltage in such R _K1 or R _K2. For example, now, consider the switch _{S 3} switching. Fig. 5
If it is and so on, h of the changeover switch S _3, i
After the changeover switches S ₁ , S ₂ , S ₃ , and S ₄ are switched many times and the circuit has settled in an equilibrium state, the voltage between the _two switches is 0.
[V]. That is, FET between h and i
0 [V] voltage is applied between the drain and the source. However, here, the changeover switches S ₁ , S ₂ , S ₃ ,
When S ₄ is switched to the opposite side of the terminal, h, the voltage between the i becomes _{E REF} / 4 [V]. Accordingly, the drain-source voltage of the FET between h and i is changed from 0 [V] to E
_REF / 4 [V]. The actual operation of the changeover switch _{S 3} First, the off-h, and FET between i,
Subsequently, the FET between g and h is turned on. FE between g and h
At the moment when T is turned on, a voltage is applied between h and i, and the charge _CDS between the drain and source of the FET between h and i is charged. For this reason, a current flows instantaneously to the drain or source side of the FET between h and i, which causes a spike voltage. The same applies when the FET is turned on. However, in this case, the charge charged in the drain-source capacitance of the FET is discharged. In addition, at the time of the discharge, the current flows between the drain and the source of the FET which is turned on, which causes a spike voltage. The same applies when the FET is turned on. However, in this case, the charge charged in the drain-source capacitance of the FET is discharged. Also, during the discharge,
Discharge is also generated through the drain-source of the FET that is turned on.

In order to keep the spike voltage as low as possible, the following method can be considered according to the above discussion. 1. Capacitance between the gate and source of the FET _{C GS,} the gate-drain capacitance _{C GD,} to minimize the value of the drain-source capacitance _{C DS.} 2. Minimize the on-resistance of the FET. 3. ΔV _GS is made as small as possible. That is, the FET is designed so that the absolute value of the difference between the gate-source voltage at which the FET is turned on and the gate-source voltage at which the FET is turned off is as small as possible. 4. When switching the FET switch, the changing speed of the gate-source voltage is made as slow as possible. That is, FET
Reduce the switching speed of the switch as much as possible. The above 1.2.3. Is a problem in the design of the FET. In the case of a MOS-FET, the gate-source capacitance C _GS and the gate-drain capacitance C _GD become smaller as the gate area becomes smaller. Therefore, the smaller the size of the FET, the better. Also, by doing so, the capacitor in the voltage equal divider circuit (C in the circuit of FIG.
₁ , C ₂ , C ₃ , C ₄ ) can be reduced. Next, 2. It is known that the on-resistance of the FET is determined by the aspect ratio of the gate. Therefore, when designing the FET, it is necessary to pay attention to the above three items. On the other hand, 4. Too late for
The off-leak current of the FET, the leak current of the substrate, and the leak current of the capacitor cause a large voltage drop due to the discharge of the capacitor, which causes a ripple voltage to be generated at the output. Therefore, the rate of change of the gate-source voltage of the FET must be reduced within a range where the ripple voltage does not matter.

The DA converter manufactured this time is a commercially available MO converter.
After purchasing an S-FET, a resistor, a capacitor, a FET, a transistor, an operational amplifier, a reference voltage source, a CMOS digital IC, and the like were mounted on an epoxy substrate and wired.
Since a commercially available MOS-FET was purchased and manufactured, the above-mentioned 1.2.3. Is predetermined. Accordingly, 4. The gate of the MOS-FET
The rate of change of the source-to-source voltage V _GS is made as slow as possible to reduce the generation of spike voltage at the output.

Now, taking the above into account, the actual 4
A bit DA converter was fabricated. The circuit configuration is basically the same as that of FIG. In order to satisfy the method of
Switching from the _{K 1} from the switch _{S 1} to _{S 8} to _{K 7} has the following configuration. The actual configuration in FIG. 1 from in S ₁ of the selector switch from the K ₁ to S ₈ to K ₇ is adapted to as FIG. In FIG. 7, the FET,
For F ₁ , F ₂ , F ₃ , and F ₄ , a depletion type N-channel MOS-FET was used this time. The reason for using a MOS-FET is that in the case of a junction type FET, the gate-source voltage is changed in order to turn the FET on or off. This is because, when biased, a large gate current flows into the drain or source side of the FET, affecting the equal-divided circuit, preventing the voltage from being accurately divided equally or causing a spike voltage to appear at the output.

[0038] Now, In FIG. 7, FET, the switch is constituted switched by _{F 1} and _{F 2.} That is, F
ET, _{F 2} is turned off, then, FET, _{by F 1} is turned on, the terminal b, is connected to the terminal a.
In addition, FET, _{F 1} is turned off, then, FET, F
_When terminal ₂ is turned on, terminal b is connected to terminal c. The FETs, F ₃ and F ₄ are for sensing the source potentials of the FETs, F ₁ and F ₂ . FET, F ₁ ,
To the F ₂ ON or OFF, it must change the gate voltage relative to the source potential of the FET, F ₁ or F _2. However, FET, F ₁ , F ₂
The source potential of, FET, either by _{F 1} and _{F 2} are turned on, or be changed by the terminal a, b, the potential of c is changed. Normally, as a method of driving the gate terminal of a depletion type N-channel MOS-FET, when turning on the FET, the gate
When the source-to-source voltage is set to zero [V] and turned off, a method of setting the lowest value of the power supply used in the circuit is often used. This method is relatively simple. However, on the other hand, there is a disadvantage that the voltage change between the gate and the source is large. Therefore, the condition of 3. Not satisfied. Therefore, the FET, F ₁ or F _1
It is necessary to sense the source potential of No. ₂ and drive the gate voltage based on the sensed source potential.
This eliminates the need to change the gate-source voltage more than necessary.

Now, the gate-source voltage of the FET is set to 0
The drain current at the time of [V] is called _IDSS . Conversely, when a current corresponding to _IDSS flows to the drain of the FET by the constant current source, the gate-source voltage becomes zero. By utilizing this can sense the source potential of the FET, _{F 1} and _{F 2.} FET, the source potential of the _{F 1} are connected FET, FET sensed by the gate of _{F 3,} through a resistor _{R 1} connected to a source of _{F 3} FET, the gate of the _{F 1.} Reason for the resistance R ₁ is inserted, FET used this time is also a depletion type, the value of I _DSS is the number [mA]. It is necessary to use several tens of them, and if they are used as they are, current consumption becomes too large. Thus, FET, but not must reduce the drain current of the _{F 3,} FET, reducing the drain current of the _{F 3} FET, becomes higher in the source potential to the gate potential of the _{F 3.} Therefore, FET, the source terminal of the _{F 3,} when'll connect a resistor _{R 1,} the gate and the resistance of the resistor _{R 1} of the FET due to a voltage drop, even if the drain current of the _{F 3} is less than _{I DSS} FET, _{F 3 R 1} Can be set to zero. FET, the source of _{F 3,} the resistor _{R 1} is connected the other terminal of the resistor _{R 1,} a current source _{I 1} is connected, whereby the FE
T, the source current of the F ₃ are being driven. In this case, since the gate current is negligibly small, the drain current and the source current are considered to be equal. As the current of the current source I ₁ is changed, the gate-source voltage V _GS becomes F
Along the _I D _{-V GS} characteristic of ET will change. Therefore, the resistance R _{1 based} on the gate potentials of the FET and F _3.
When the voltage of the current source side terminal and _{V R1, V R1} is as shown in Equation 28. However _{I S} used in number 28, FE
T, which is the source current of the _{F 3.} V _GS varies with the drain current as described above. Therefore, FET, by changing the drain current of the _{F 3} FET, it is possible to change the gate-source voltage of the _{F 1.}

That is, in FIG. 7, by changing the current value of the current source I ₁ , the gates of the FET and F ₁ are changed.
FET by varying the source voltage, to control the on and off F _1. Such a circuit arrangement, FET, the source potential of the _{F 1} is sensed FET, the gate of _{F 3,} FET, a current source even if the source potential of the _{F 1} changes _{I 1}
The constant gate-source voltage corresponding to the current value of
T, has a mechanism that is supplied to the F _1. FET, F
₂ likewise FET, FET by _{F 4,} the source potential of _{F 2} is sensed, the current source _{I 2} of the FET by varying a current value, and controls the gate-source voltage _{V GS} of the _{F 2} FET, F ₂ is turned on and off. Current waveform of each switching in the switch current source _{I 1} and _{I 2} are different in from the switch _{S 1} switches from the _{K 1} to _{S 8} to _{K 7.} This is shown in FIGS. 8 and 9. FIG. 8 will be described. This represents the output waveform of the current source I ₁ and the current source I ₂ in each of the switches S ₁ switch to S ₈ switches. These changeover switches from the switch S ₁ switch are used for dividing voltage, etc. to S ₈ periodically switched in conjunction with each other. Of course, switching may be performed according to individual timing. However, it was designed to be switched in conjunction with this time, because switching in conjunction will make it easier in terms of circuitry.

Now, condition 4 described above. Therefore, the switching speed of the switch must be designed to be as low as possible. To realize this, a triangular waveform current is output from the current source, and the frequency is set as slow as possible. This time is 50
0 [Hz]. 180 ° phase difference is provided in the output current waveform of the current source I ₁ and the current source I _2. On the other hand, the current value of the intersection point of the output waveform of the current source I ₁ and the current source I ₂ I
_Assuming that _TH , when the output currents of the current sources I ₁ and I ₂ take this value, I _TH is equal to the gate-source voltage V _{GS (OFF) at} which both the FETs F ₁ and F ₂ are turned off. Designed to be or slightly smaller. (Greater in absolute value.) By doing so, FET, _{F 1} and _{F 2} are not turned on simultaneously.

Next, FIG. 9 will be described. This shows the timing of the current source I ₁ or the current source I ₂ in each of the switch K ₁ switching to K ₇ switch. From selector switch K ₁ to K ₇ is a switch corresponding to each position digital input bit, the difference switching speed from the switch S ₁ switch these switches to S ₈ are important. A spike voltage is generated when the changeover switch is instantaneously and quickly changed. But this is only temporary. The above condition, C _{GS <<} C ₂ , and
The voltage across the capacitor of the absolute value of C ₁ than assumed and the number 26 and is not differ too greatly to C ₈ of [Delta] V _GS and V _C2 may be considered unchanged. The change in the gate-source voltage of the FET in the changeover switch is instantaneous in this case, so that the spike voltage stops as soon as the change stops, and has substantially no effect thereafter.
In FIG. 9, and off the FET of those who F ₁ and F ₂ is in the first on so as not to be turned on at the same time, to turn on the FET of those who had been turned off after a short time Control. On the other hand, in the circuit of FIG. 1, a buffer amplifier is configured using an operational amplifier in an output stage so that a load current can be obtained, and an output is provided.

Now, let us describe a DA converter using a circuit for doubling the voltage. FIG. 10 is a circuit for doubling the voltage using switched capacitor technology. Switches _{S W1} and Sw ₂ switching Pleiku -
It switches in conjunction with the before make switch. The operation principle will be described below. First the state of the changeover switch _{S W1} and _{S W2} first states such as shown in FIG. 10. First, the capacitor Ca is connected to the reference voltage source E _REF
At the point where the movement of the electric charge is enough,
This time is for twice the voltage and change-over switch _{S W1} and _{S W2} switching reference voltage source _{E REF} and the condenser Ca and the series connection. Then, the capacitor Cb is charged with the doubled voltage. Switch S _W1 then again switched at the movement of the charge was calm enough
And _SW2 are switched to a state as shown in FIG. Then, the above procedure is repeated again and again. By such a method, the voltage between both ends of the capacitor Cb is increased by 2.E _REF [V].
It is assumed that.

By using the voltage doubling circuit, a DA converter can be manufactured. The principle is based on the D fabricated by using the voltage equalization circuit described above.
Same as -A converter. Therefore, here, I want to omit the detailed explanation. FIG. 11 shows an example of a 2-bit DA converter manufactured using a voltage doubling circuit. Also,
This circuit is the same as the circuit of FIG. 5 _except that the reference voltage source E _REF and the capacitor C ₄ are replaced. From when the same changeover switch S ₁ in FIG. 5 to S ₄ is periodically switched in conjunction a switch to double the voltage. Further, a changeover switch from K ₁ to K ₃ is corresponding to the digital input. K ₁ and _{K 2} are switched in conjunction, corresponding to the most significant bit of the digital input bit. Also, _{K 3} corresponds to the lowest bit of the digital input bit.

Next, FIG. 12 shows an 8-bit DA of the present invention.
Two converters are used and one of these DA converters has 1 /
256 weights are added and added to the other DA converter. By doing so, the 16-bit D
Realization of -A converter is possible. Here, the voltage of each DA converter is added by an operational amplifier using a resistor. At this time, the accuracy of the resistor is about 0.1%, which is realized without fine adjustment by a laser. It is possible to

FIG. 13 shows a case where a successive approximation type AD converter is realized using the DA converter of the present invention. FIG. 14 shows an example of a serial / parallel type AD converter manufactured using the DA converter of the present invention.

[0047]

FIG. 1 shows a configuration using a changeover switch as shown in FIG.
A D / A converter having the following circuit configuration was manufactured, and its accuracy was measured for all input codes. As a result, the non-linearity error was a maximum of 0.0005% with respect to 10 [V] full scale. It was confirmed that. Further, the temperature coefficient of the nonlinearity error was so small that it could not be measured. The capacitor used at this time was a 1 [μF] multilayer ceramic capacitor. This condenser is accurate,
The temperature stability is very poor, and the error is 50% or more. Nevertheless, the fact that such high-precision and high-temperature stability has been achieved demonstrates the superiority of the present invention. The output switching noise is 75 [μV
There in the _P-P]. This was also a very small value. Next, the time required to settle to an accuracy within + -150 [μV], that is, the settling time was 10 [mS]. As described above, the D-A having high precision and high temperature stability without performing any fine adjustment of the resistor and the like aimed at by the present invention.
It has been confirmed that the converter is realized by the method according to the present invention.

[Brief description of the drawings]

FIG. 1 is an example of a 4-bit digital-to-analog converter of the present invention.

FIG. 2 is an operation principle diagram of a conventional 4-bit digital / analog converter.

FIG. 3 is an actual circuit diagram of a conventional 4-bit digital-to-analog converter using an R-2 · R resistance ladder network circuit.

FIG. 4 is a voltage equal division circuit using switched capacitor technology.

FIG. 5 is an example of a 2-bit digital-to-analog converter manufactured using the principle of the voltage equalization circuit of FIG. 4;

[6] a first voltage equal division circuit of the circuit of FIG. 5 E _REF
2 is a circuit diagram equivalently replaced with a constant voltage circuit of / 2.

FIG. 7 is a changeover switch designed to reduce switching noise of the changeover switch used in the digital-to-analog converter of the present invention.

8 is a in the current source I ₁ and I ₂ of the current waveform in FIG. 8 shows a current waveform when the circuit of FIG. 7 is used as a changeover switch used in an analog voltage weighting circuit. (In FIG. 1, S ₁ , S ₂ , S ₃ , S ₄ ,
S ₅ , S ₆ , S ₇ , and S ₈ are switches for weighting the analog voltage. )

9 is a in the current source I ₁ and I ₂ of the current waveform in FIG. 8 shows a current waveform in a case where the circuit of FIG. 7 is used as a changeover switch for adding a voltage of a weighting circuit of an analog voltage in accordance with a digital input code.
(In FIG. 1, K ₁ , K ₂ , K ₃ , K ₄ , K ₅ , K
_6, K ₇ is a changeover switch for addition the voltage of the weighting circuit of the analog voltage. )

FIG. 10: Voltage 2 using switched capacitor technology
It is a double circuit.

11 is an example of a 2-bit DA converter manufactured using the principle of the voltage doubler circuit of FIG. 10;

FIG. 12 shows a 16-bit digital-to-analog converter which uses two 8-bit digital-to-analog converters, weights the output of the two digital-to-analog converters by 1/256, and performs addition. This is an application example that realizes the above.

FIG. 13 shows a successive approximation type analog-to-digital converter.

FIG. 14 shows a serial-parallel type analog-digital converter.

[Explanation of symbols]

First operational amplifier second current adder 3 current - voltage converter fourth current source I ₂ of the current waveform shown in the circuit of FIG.
7 shows a waveform when the changeover switch having the configuration of FIG. 7 is used in an analog voltage weighting circuit. 5 circuit to the indicated current source I ₁ of the current waveform in FIG.
7 shows a current waveform when the changeover switch having the configuration of FIG. 7 is used in an analog voltage weighting circuit. 6 current source I ₁ of the current waveform shown in the circuit of FIG.
7 shows a current waveform when the changeover switch having the configuration of FIG. 7 is used to add the voltage of the analog voltage weighting circuit in accordance with a digital input code. 7 current source I ₂ of the current waveform shown in the circuit of FIG.
7 shows a current waveform in the case where the switching switch having the configuration shown in FIG. 7 is used to add the voltage of the analog voltage weighting circuit in accordance with the digital input code. 8 Digital-to-analog converter 9 Attenuator, attenuated by 1/256. Reference Signs List 10 adder 11 gain 1 amplifier 12 successive approximation register 13 clock 14 analog comparator 15 subtractor 16 variable gain amplifier 17 analog-to-digital converter 18 data bus 19 gain control signal 20 controller and data decoder 21 conversion end signal 22 Id current Sa from the conversion start signal C _{1 C 8} condenser Ca and Cb condenser from K ₁ from _{K 7} changeover switch S _{1 S 8} changeover switch S _W1 and _{S W2} changeover switch E _REF reference voltage source A ₁ operational amplifier Ia Sd switch V _OUT output R resistor 2 · R 2 times the resistance Iin current from the on-resistance of the on-resistance R _K2 changeover switch _{K 2} terminal R _K1 changeover switch _{K 1} of u changeover switch from the branch point a E _REF of R 2 reference voltage source, a reference voltage source _{E REF} 1 /
It has a voltage of 2. + V positive power supply -V negative supply R ₁ and _{R 2} resistor F ₁ from _F 4 FET _{I 1} and _{I 2} the current source I current source _{I 1} or _{I 2} of the current I _TH Figure 7 FET, _{F 1} and _{F 2} I ₁ to turn off
And the current value of _{I 2.} Io _N I ₁ which turns on the FETs, F ₁ and F ₂ of FIG.
And the current value of _{I 2.} I _OFF I, which turns off the FETs, F ₁ and F ₂ in FIG.
Current value of ₁ and _{I 2.} T time B1 to B16 input bit of DA converter, B1 is D
B9 is the most significant bit of the A / A converter 1 and B9 is the D / A converter 2
Is the most significant bit of β attenuator, attenuated by 1/256. A ₂ gain 1 amplifier A _IN analog input A _OUT analog output A ₃ analog comparator CLK clock SAR successive approximation register A ₄ variable gain amplifier

(Equation 1)

(Equation 2)

(Equation 3)

(Equation 4)

(Equation 5)

(Equation 6)

(Equation 7)

(Equation 8)

(Equation 9)

(Equation 10)

[Equation 11]

(Equation 12)

(Equation 13)

[Equation 14]

(Equation 15)

(Equation 16)

[Equation 17]

(Equation 18)

[Equation 19]

(Equation 20)

(Equation 21)

(Equation 22)

(Equation 23)

(Equation 24)

(Equation 25)

(Equation 26)

[Equation 27]

[Equation 28]

Claims (2)

(57) [Claims] An analog voltage corresponding to each digital input is weighted by using a switched capacitor technique that repeatedly performs an operation of connecting a plurality of capacitors in parallel and an operation of connecting a plurality of capacitors in series. A digital / analog transformer having a structure in which a plurality of weighting circuits are connected by further weighting the voltage of a certain weighting circuit selected by a changeover switch that changes according to a code by another weighting circuit. 2. A capacitor 1 as a weighting circuit.
A capacitor A; a terminal A; a terminal B connected to the terminal 2 of the capacitor 2; a terminal C connected to the terminal 1 of the capacitor 2; a terminal D connected to the terminal 2 of the capacitor 2; A switch 1 that is connected to the terminal 1 of the capacitor 1 so that the connection of the terminal 1 of the capacitor 1 can be switched to the terminal 1 and the terminal A of the capacitor 2 and the connection is repeatedly switched;
Is connected to the terminal 2 of the capacitor 1 so that the connection is switched between the terminal 1 of the capacitor 2 and the terminal 2 of the capacitor 2, and is switched in conjunction with the changeover switch 1. The changeover switch 1 is connected to the terminal 1 of the capacitor 2. And a changeover switch 2 connected to the terminal 2 of the capacitor 2, and the connection between the weighting circuits is switched corresponding to a certain number of 0s and 1s of the digital input code. The connection between the switch 3 connected to the terminal A of the weighting circuit 1 and the terminal B of the weighting circuit 1 is such that the connection of the terminal A is switched to the terminal A of the weighting circuit 2 and the terminal C of the weighting circuit 2. Terminal C of weighting circuit 2
Is connected to the terminal B of the weighting circuit 1 so as to be switched to the terminal D of the weighting circuit 2, and is switched in conjunction with the changeover switch 3.
Is connected to the terminal A of the weighting circuit 2
2. A digital-to-analog converter according to claim 1, further comprising a change-over switch connected to the first, second, and third weighting circuits, and a plurality of weighting circuits connected in series.