JP3227337B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a successive approximation type A / D converter built in a data processing LSI such as a microcomputer for improving accuracy and operation speed at low voltage operation. It is about effective technology.

[0002]

2. Description of the Related Art A successive approximation A / D converter built in a data processing LSI such as a microcomputer includes:
A resistance voltage division type circuit using a ladder resistor and a charge redistribution type circuit using a capacitor array are often used.

The basic operation principle of the charge redistribution type A / D converter will be described with reference to FIG. FIG. 2 is a schematic diagram of an 8-bit charge redistribution A / D converter, and includes capacitors C0 to C0.
Capacitor array composed of C8 and comparator C
P, and analog switches S0 to S8, SA, and SB. In addition, the analog switches S0 to S8, S
The operations of A and SB are controlled by the control logic CL. N for analog switches S0 to S8, SA and SB
It is a transfer gate composed of a MOS transistor and a PMOS transistor. SA switches the input of the analog switches S0 to S8 to the measurement voltage SIN or the analog reference potential VR, and SB short-circuits the input and output of the comparator CP. The capacitances of the capacitors C0 to C8 are weighted in binary, and the ratios of the respective capacitances are as shown in Table 1 below.

[0004]

[Table 1]

It is assumed that the control logic CL operates in synchronization with the reference clock CK. In the initial state, the analog switch SB is ON, and the analog switch SA is on the SIN side.
Connected to IN side. Therefore, one electrode of the capacitor array is charged to the equilibrium voltage V0 determined by the beta ratio of the comparator, and the other electrodes are all charged to the measurement voltage SIN. This initial charging time is assumed to be one clock of the reference clock CK.

After the end of the initial charging period, the analog switch SB is turned off, SA is switched from SIN to VR, and S0 to S7 are kept at VR while S8 is kept at VR for one subsequent clock period of CK. All are switched to the GND side. At this time, the potential of one electrode of the capacitor C8 is V
R, and the potential of one electrode of the capacitors C0 to C7 becomes GND. Further, since the input node of the comparator CP is in a floating state, the potential changes according to the amount of charge initially charged due to the redistribution of charge.
Assuming that there is no electric charge leakage in the transition from the initial state to the first comparison period, the first comparison ends up comparing the measured voltage SIN with VR / 2, and the comparator operates as SIN. If> VR / 2, "1" is output, and if SIN <VR / 2, "0" is output. In this way, the data of the most significant bit is determined.

Next, if the first conversion result is "1", S8 is left on the VR side, and if "0", S8 is set to GN.
Switching to D side, S7 is switched to VR side. Also,
All other analog switches (S0 to S6) are G
It remains on the ND side. It is also assumed that this second comparison period is also equivalent to one clock of CK. The potential of the input node of the comparator fluctuates due to the redistribution of the charge accompanying the state transition from the first comparison period to the second comparison period,
The comparator outputs corresponding data. Thus, the data of the second bit is determined. Thereafter, the same operation is repeated for 8 bits, whereby data of all bits is determined. The converted data is sequentially stored in a register called a successive approximation register in the control logic. Therefore, at least nine clocks are required for one bit of the initial charging period and eight clocks of the comparison period from the first to the eighth times until the data of all the bits are determined. If the number of A / D conversion bits is further increased, the conversion time will be (number of bits + 1) clocks.

[0008] With the low voltage of the microcomputer,
When operating the above-mentioned A / D converter at a low voltage, the operation speed becomes a problem. In particular, the one that most affects the operation speed is the on-resistance of the analog switch. Since the analog switch is composed of an NMOS transistor and a PMOS transistor, if the measured voltage is close to the analog reference potential VR or the ground potential GND, the on-resistance does not matter so much even if the measured voltage is low, but the measured voltage is just between VR and GND. Since the potential difference between the source and the gate is close to the threshold voltage of the transistor in the vicinity of the middle, the on-resistance is extremely large at a low voltage. Therefore, it takes a long time to charge the capacitor array, and if the charging time is insufficient, the accuracy is greatly reduced. Further, when the input impedance of the analog input signal increases, the input current decreases, and the same problem occurs. This problem becomes more pronounced at lower voltages.

In order to solve the above problems, the following methods have conventionally been used.

A first method is to make the W / L ratio of the analog switch sufficiently large. However, this method causes an increase in chip area, and when the drain capacitance of the analog switch becomes too large to be neglected as compared with the capacitance of the capacitor array, a decrease in accuracy due to parasitic capacitance becomes a problem.

A second method is to reduce the total capacitance of the capacitor array. Although the charging time can be shortened by this method, the influence of the parasitic capacitance can not be neglected relatively, and the influence of the variation at the time of manufacturing is more likely to occur, so that the accuracy is reduced.

A third method is to lower the frequency of the clock to increase the overall conversion time. Any condition can be met by lowering the clock frequency so that the required initial charging time can be secured depending on the use conditions of the A / D converter. As an application example of this method, for example,
In 159814, by providing a clock frequency dividing circuit and a clock selecting circuit for taking out the output from each clock frequency dividing stage and selecting them inside the A / D converter, sufficient charging is performed according to the use condition of the A / D converter. It claims that the user can select the appropriate clock frequency to get the time to meet any usage conditions.

A fourth method is to provide a booster circuit and raise the gate voltage of the NMOS transistor of the analog switch to a power supply voltage or higher. With this method, the on-resistance of the analog switch can be sufficiently reduced even at a low voltage. However, when the input impedance is large, this method alone cannot cope with it, and inevitably lowers the clock frequency.

As described above, the charge redistribution type A / D converter using the capacitor array as shown in FIG. 2 is based on the premise that there is no leakage of charge with the transition between the states. However, the fact that charge leakage can occur in a special case will be described below with reference to FIG. Since the analog switch SB for short-circuiting the comparator is ON during the initial charging period, the input node of the comparator is kept at a balanced voltage determined by the beta ratio of the PMOS transistor and the NMOS transistor. Assuming that this balanced voltage is V0, it is usually designed so that V0 = VR / 2. However, when the threshold voltage of the transistor fluctuates due to manufacturing variations and operating temperatures, V0 also fluctuates up and down from VR / 2.
Here, as a special case, as shown in FIG.
Consider the case where V0 is greater than VR / 2 and the measured voltage SIN is GND. At this time, during the initial charging period, the electrode on the comparator side of the capacitor array is charged to V0,
The opposite electrodes are all charged to GND. Therefore, the capacitor array is charged with the potential difference of V0. Then, in the first comparison period, the electrode on the comparator side of the capacitor array is in a floating state, and the electrode on the opposite side is VR only for C8 and GND for all others.
In this state, the input node potential of the comparator is V1
Then, C8 is １ ／ of the capacitance of the entire capacitor array.
V1 is raised from V0 by VR / 2, and V1 = V0 + VR / 2. Now V0>
Since the case of VR / 2 is considered, eventually V1> VR. As the analog reference potential VR, a voltage equal to or lower than the power supply potential VDD is normally used. Here, if VR = VDD for simplification, V1 exceeds the power supply potential. When such a situation occurs, there is a possibility that electric charge leaks from the PMOS transistor of the analog switch SB connected to the input side of the comparator. This is clear from the cross-sectional view of the PMOS transistor in FIG. That is, it can be seen that the back gate is fixed at the power supply potential, and the source is higher than the power supply potential, so that charge leaks through the pn junction. A similar problem also occurs when V0 is smaller than VR / 2 and SIN is equal to VR, as shown in FIG. In this case, on the contrary, V1 becomes lower than the ground potential, and leakage to the p substrate may occur in the NMOS transistor of the analog switch SB. But in practice, p
Since the forward breakdown voltage of the n-junction exists, even if V1 becomes higher than the power supply potential or lower than the ground potential to some extent, no leak occurs. Therefore, no special measures have been taken in this regard in the past.

As a countermeasure against this, for example, Japanese Patent Laid-Open No. 6-622
In No. 3, the back gate potential of the Pch transistor is fixed to the analog reference potential VR instead of the power supply potential VDD, so that even when VR is higher than VDD, pn
Current is prevented from flowing through the junction. In this case, the Pch transistor cannot be completely turned off depending on the potential difference between VR and VDD. Therefore, a level shift circuit for setting the level of the control signal on the Pch side of the analog switch to the same potential as VR is required. In this method, VR is VD
This is an effective technique only with respect to the fact that it may be higher than D. When the threshold voltage of the transistor fluctuates, the above-described charge leakage also occurs, which is not a fundamental solution.

[0016]

As means for solving the problem of an increase in the charging time due to the lowering of the voltage, the first and second methods are not preferable because they essentially lower the accuracy. Therefore, the present invention has been studied mainly on the third method. In the method of Japanese Patent Application Laid-Open No. 2-159814, the charging time is expanded or contracted by selectively changing the clock frequency. The above patent is directed to a successive approximation type A / D converter in which a comparison reference potential is generated for each bit by an internal D / A converter, a sampling capacitor is charged, and a comparison is made with a measured voltage. Therefore,
At the time of comparison for each bit, an arbitrary intermediate potential between the analog reference potential VR and the ground potential GND is always generated, so that the ON resistance of the analog switch increases, the clock frequency is reduced, and the charge for each bit is reduced. Prolonging the time was effective. However, in a charge redistribution successive approximation A / D converter such as the one to which the present invention is directed, the measured voltage is first charged only once to the capacitor, and then the charge is transferred by the binary weighted capacitor array. Since the voltage comparison is performed using the redistribution, the ON resistance of the analog switch becomes a problem only during the first charging. Since the analog switch is always used only for switching between VR and GND during periods other than the initial charging period, the on-resistance does not cause any particular problem. In the method of lowering the clock frequency, since the on-resistance is extended to a period where no particular problem occurs, the entire conversion time is significantly increased. A
This tendency becomes more remarkable as the number of bits of the / D conversion increases. In addition, since the clock frequency division is usually performed by one half or one half of an integer, the method of selecting a clock has a problem that the conversion time is greatly increased by a factor of two or an integer multiple.

In addition, regarding the charge leakage as described above, V0 greatly deviates from VR / 2 beyond the range of the forward breakdown voltage of the pn junction due to manufacturing variations and operating temperatures, or noise or other causes. If the VR instantaneously fluctuates beyond the power supply potential, there is a possibility that a leak may occur, which causes a drastic reduction in conversion accuracy.

[0018]

An A / D converter according to the present invention comprises a capacitor array, a comparator, and an analog switch.
And a charge redistribution type A / D converter
Analog measurement on sampling capacitors
Means for setting an initial value of a voltage initial charging time;
Means for generating an analog voltage, and A / D conversion of the analog voltage.
Comparison that compares the output value with the expected value and outputs the error
Means until the output of the comparing means is within a predetermined range.
The initial charging time is changed sequentially, independent of the comparison period.
Means for making the value of the predetermined analog voltage
Is 1/2 of the analog reference voltage .

Further, the A / D converter of the present invention has the above-mentioned A / D converter.
In the D converter , the capacitor array
PM of analog switch connected to the data side node
When the back gate potential of the OS transistor is
It is characterized in that means for setting a predetermined voltage is provided.

[0020]

[0021]

[0022]

According to the present invention, the user can set the optimum initial charging time according to external conditions such as the power supply voltage and the input impedance, and can always obtain a constant accuracy regardless of these external conditions. The A / D converter can have versatility. Further, since the clock frequency is not changed, sufficient accuracy can be obtained even at a low voltage without significantly increasing the overall conversion time.

Further, since there is no need for the user to reset the initial charging time even when the use condition of the A / D converter changes, the burden on software is reduced.

Further, according to the present invention, even if the threshold voltage of the transistor fluctuates significantly due to variations during manufacturing or the operating temperature, or if the analog reference potential fluctuates due to noise or the like, leakage of electric charge from the analog switch is prevented. Prevention and a decrease in accuracy can be prevented.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on embodiments.

(Embodiment 1) An embodiment of the present invention will be described below with respect to a successive approximation type A / D converter as shown in FIG. Note that the present invention is not limited to the present embodiment. For example, the number of bits for A / D conversion, the length of the initial charging time, and the like may be arbitrary.

FIG. 1 is a block diagram of an A / D converter according to the present invention. The analog block AB in the figure is exactly the same as the analog part AP of the 8-bit A / D converter shown in FIG. Analog block A consisting of a capacitor array with A / D converter, comparator and analog switch
B, data register DR, control register C
R, address decoder AD, successive approximation register CMR,
It comprises a counter CT. The data register temporarily holds the converted data for output to the data bus 8
Bit register, control register is A / D
It is a register for receiving an instruction relating to the operation of the converter from the data bus and for returning the state of the A / D converter to the data bus. The control register includes a bit for setting an initial charging time. The address decoder is a circuit for exchanging data between a data bus, a data register, and a control register when an input address is for an A / D converter. The successive approximation register operates in synchronization with the reference clock CK, and is a circuit for controlling the operation of the analog switch based on data output from the comparator of the address block.
The main part of. The converted data is sequentially stored in a register inside the circuit. The counter is a circuit for holding the initial charging time for the number of clocks set in the control register. The counter directly counts the reference clock CK and waits for the successive approximation register. The number of bits of the counter need only be the number of clocks corresponding to the maximum initial charging time to be set. If an arbitrary output of the counter is taken out, an arbitrary wait can be applied in units of one clock, so that any initial charge time can be set as long as it is less than the maximum count of the counter.

FIG. 5 is an operation timing chart of the A / D converter according to the present invention. In this figure, the initial charging / charging period is two clocks, but of course, this may be any number of clocks.

Configuration of Control Register FIG. 9 is a circuit diagram of one bit of the control register. Here, DLTR is a D latch circuit with a reset terminal, and G and GB are clock signals. When the WRITE signal goes high, the data on the data bus is latched and output to Q. This state is WRITE again
Retained unless a signal is input or reset.
The data output to Q is used as an internal control signal of the A / D converter. As a control signal, for example, AD indicating that the A / D converter is in an active state.
E signal and the like. What is necessary is just to prepare a control register of the necessary number of bits according to the number of control signals. In addition, the data written in the register during the period when the READ signal is at the high level is output on the data bus. The RESET signal is used to clear the contents of all registers to 0 at the time of system reset.

Structure of successive approximation register FIG. 10 shows the structure of the successive approximation register. Where DFF
R is a D flip-flop circuit with a reset terminal triggered by the rising edge of CK. The successive approximation register is generally constituted by a shift register in which DFER flip-flop circuits are connected in multiple stages in series. These registers are all reset to 0 at the time of system reset and immediately after A / D conversion is completed.
The D terminal of the first-stage D flip-flop circuit is connected to the power supply potential VD.
D, and the output Q becomes high level at the moment when the START signal rises. The START signal is a trigger for starting the operation of the A / D converter, and is generally an AD signal indicating that the A / D converter is an active signal.
The E signal is used. The D terminal of the second and subsequent D flip-flop circuits is connected to the Q terminal of the preceding stage, and the CK terminal is connected to the A terminal.
It is connected to an AND of DE and CK.
Therefore, each time a clock is input, the output Q is transmitted one by one to the next stage.

The signal B is a signal for controlling the analog switches SA and SB in FIG. 1. When B is at a low level, SA is connected to the SIN side, and SB is defined to be turned on. That is, when B is at a low level, the initial charging is performed. B is the NAN of the ADE signal and the output QB of the D flip-flop circuit at an arbitrary stage
D was taken, and at the moment ADE started, B
Goes low, and the output QB of the D flip-flop circuit
Becomes 0 again when B becomes 0. Therefore, the number of clocks in the initial charging period is determined by the number of stages of the shift register.

The signals D0, D1,...
0, S1,..., And when these signals are at a low level, one electrode of the capacitor is defined to be connected to VR, and when these signals are at a high level, it is defined to be connected to GND. Note that the order is reversed, with D0 controlling the most significant bit analog switch. That is, in the example of the 8-bit A / D converter in FIG. 2, D0 controls the analog switch S8. Generally, there are as many control signals as there are analog switches connected to the capacitors. Control signals D0, D
The portion generating 1,... Is composed of a combination of two D flip-flop circuits and an AND circuit and a NOR circuit. In the initial state, the output Q of the D flip-flop circuit connected to one input of the NOR is 0,
Since the output of D is also 0, D0 is at a high level.
When the initial charging period of an arbitrary number of clocks ends and the signal B goes high again, the output of AND goes to 1 so that D0 goes low. When the next clock is further input, the output Q of one D flip-flop circuit becomes 1, and
Conversion data DAT from the analog block is latched by the other D flip-flop circuit. At this time, AN
Since the output of D is 0, the output D0 of NOR is the inverse of the latched data. That is, if the data is 0, D0 is at a high level, and if the data is 1, D0 is at a low level. In this way, the next state of D0 is determined by the conversion result of the most significant bit, and the control signal D1 of the second-bit analog switch changes to low level. Hereinafter, the same operation is repeated to perform conversion one clock at a time, and the result is stored in the sequential D flip-flop circuit. FIG. 11 shows these states. Here, it is assumed that the conversion results are all zero.

Circuit for setting initial charging time As an example of a circuit for setting the initial charging time, FIG.
An example using a bit octal counter is shown. Where TF
FR is a T flip-flop circuit with a reset terminal, which is reset at the time of system reset and immediately after A / D conversion ends. FIG. 12 shows a general asynchronous octal UP counter. Since the input clock is connected to a signal obtained by ANDing ADE and CK, the number of clocks after A / D conversion starts is changed from 0 to 7. And outputs it to Q1, Q2, and Q3. Since the analog switch control signal B goes low at the same time as the rising edge of ADE, the value of this counter is detected and the value of S
If a trigger is applied to the TART signal, the rise of the signal B can be arbitrarily delayed. The initial charging time is stored in an initial charging time setting bit in the control register. In this example, since the counter is 3 bits, a maximum of 8 settings can be made. In general, if the number of bits of the counter is N, a maximum of 2 ^N settings can be made. The bit number of the initial charging time setting bit in the control register may be equal to or smaller than the bit number of the counter. The relationship between the value of the initial charge time setting bit and the actual number of clocks may be arbitrary. For example, if the number of bits of the counter and the number of bits of the initial charging time setting bit are the same, the value of the initial charging time setting bit may correspond to the number of clocks as it is, or the number of bits of the initial charging time setting bit may be larger. If it is small, an appropriate number of clocks may be assigned within the range of the maximum count of the counter. In this way, the value of the initial charging time setting bit is made to correspond to an arbitrary number of clocks, and decode signals are generated by the number of possible combinations. Generally, if the number of bits is n, there are 2 ⁿ decode signals, and only one of the decode signals is set to a high level.
Then, as shown in FIG. 12, the inputs of the three-input AND circuit are connected so that the set number of clocks can be detected. That is, the connections are made such that the output of the AND becomes 1 when the output of the counter reaches the set number of clocks. Thus, in all combinations, the three-input AND
If the input of the circuit is connected and one is selected by the decode signal, the START signal becomes high when the number of clocks specified by the initial charge time setting bit has elapsed, and the successive approximation register can be triggered. . For reference, a circuit configuration of a control logic of an A / D converter according to the related art is shown in FIG. As shown in FIG.
It simply has no counter for applying a wait to the successive approximation register as compared with the present invention. That is, a normal A / D active signal ADE is used as a trigger signal of the successive approximation register instead of using a circuit as shown in FIG.

Hereinafter, the operation of the A / D converter will be described with reference to FIGS. 1, 2 and 5. First, a conversion start flag included in a control register and an initial charging time required according to external conditions such as a power supply voltage and an input impedance are set on a data bus, and a control register of the A / D converter is allocated. The input address is input to the address line, and the WRITE signal is input, whereby data is written to the control register and A / D conversion starts.

When the A / D conversion starts, the successive approximation register turns on SB for the analog block,
Is switched to the SIN side, and a timing signal is output so that S0 to S8 are all switched to the SIN side. This initial charging period continues for the number of clocks set in the control register.

When the initial charging period of the set number of clocks ends, the successive approximation register turns off SB for the analog block, switches SA to the VR side, and sets S8 to V
A timing signal is output to the R side to switch S0 to S7 to the GND side. Due to this state transition, redistribution of charges occurs, the potential of the input node of the comparator changes, and the comparator outputs data to the successive approximation register. At the next rising edge of CK, the successive approximation register latches the data from the comparator and stores the data in the internal register. If the data is "1", S8
Is switched to the VR side, and if "0", S8 is switched to the GND side, and S0 to S6 are all set to the GND side.
7 is switched to the VR side. Thus, the first comparison is completed, and at the same time, the second comparison starts.

In the same manner, data is latched at the rising edge of each clock, and the successive approximation register determines the next state from the data and outputs a timing signal to the analog block. That is, if the latched data is “1”, the analog switch of the capacitor corresponding to the bit is switched to the VR side, and if the latched data is “0”, G is switched to G.
Switch to ND side. Then, the analog switch of the capacitor corresponding to the one lower bit is switched to the VR side, and all capacitors corresponding to the lower bits are left at the GND side. By repeating this operation up to the least significant bit, data of all bits is sequentially stored in the successive approximation register.

When the data of all the bits are determined, the conversion start flag in the control register is reset, indicating that the conversion has been completed. The address assigned to the control register side of the A / D converter is inputted to the address line, and the contents of the control register can be read out to the data bus by inputting the READ signal. The conversion start flag is reset. Then, by inputting the address of the data register to the address line and inputting the READ signal, the converted data can be read out on the data bus.

As described above, one A / D conversion is completed, and the conversion time becomes (the number of bits + the number of clocks in the initial charging period) clocks. As described above, the initial charging time may be set to a time necessary for sufficient charging according to external conditions such as the power supply voltage and the input impedance. If the initial charging time is equal to or longer than the conversion time for the number of bits, it is desirable to lower the frequency of the clock itself.

(Embodiment 2) An embodiment of claim 4 will be described below using an A / D converter as shown in FIG. Here, the charge redistribution type A according to the first embodiment except that a booster circuit is built in
The operation method is exactly the same as that of the / D converter. FIG. 6 shows an example of a simple booster circuit. CK is a clock input. When CK is at a high level, the electrode A of the capacitor C is charged to the ground potential GND, and the electrode B is charged to the power supply potential VDD. Next, when CK goes from a high level to a low level, the electrode B is in a floating state, and the potential of the electrode A is GND while the potential difference between the electrodes AB is kept at VDD.
From VDD to VDD, the potential of the node HV ideally rises to twice the VDD. However, since a load capacitance such as a gate capacitance or an n-well capacitance is actually connected to the node HV, the voltage is lower than twice VDD, and the degree depends on the capacitance of the capacitor C. Therefore, the larger the load capacitance to be boosted, the more the capacitor C
Capacity needs to be increased. Further, since the sources of the PMOS transistors Tr1 and Tr2 are boosted, the back gate also needs to be boosted. Since this booster circuit alone can boost only during the period when CK is at a low level, in order to boost continuously, two circuits are used to connect CK to two-phase clocks whose high levels do not overlap each other, and What is necessary is just to repeat charging / boosting alternately by the boosting circuit.

The above-described booster circuit is connected to the charge redistribution type A /
The back gate of the PMOS transistor of the analog switch SB built in the D converter and connected to the input side of the comparator is constantly boosted to the power supply voltage or more. However, this method alone cannot cope with the case where a leak occurs on the NMOS transistor side as shown in FIG. 4B. To prevent this, even if V1 becomes the smallest, V1
V0 is set to VR /
It may be designed to be higher than 2. Of course, in this case, needless to say, it is necessary to set the capacitance of the capacitor C of the booster circuit so that the potential of the back gate is always higher than V1 even when V1 becomes the largest.

According to this method, even if V0 fluctuates extremely due to manufacturing variations or use temperature, or if the analog reference potential fluctuates instantaneously due to external noise, it is possible to prevent charge leakage in the analog switch SB. , Accuracy can be maintained.

In this embodiment, a simple double boosting circuit as shown in FIG. 6 is used, but it is a matter of course that any kind of boosting circuit can be used. The circuit becomes complicated,
If a booster circuit capable of boosting the voltage by a factor of two or more is used, the operating margin can be further increased.

(Third Embodiment) As an application of the first embodiment, the second and third embodiments of the present invention will be described with reference to FIG. FIG. 7 is a block diagram of the A / D converter of this embodiment. The A / D converter shown in FIG.
/ 2 input terminal. The determination circuit is a circuit for determining the result of the A / D conversion obtained in the data register and rewriting the contents of the control register. The VR / 2 input terminal is connected to a voltage of 1/2 of the analog reference potential VR generated by resistance division, and the analog signal input terminals SIN and VR / 2 are switched by an analog switch. Input V
The reason for setting R / 2 is that the ON resistance of the analog switch is the largest, and the accuracy is most significantly reduced.

In this A / D converter, a self-adjustment function start flag for the initial charging time is provided in the control register, and the self-adjustment function is started by setting this flag. When the self-adjustment function starts, the determination circuit first sets the initial charge time setting bit in the control register to the minimum of one clock, sets the A / D conversion start flag, and sets the analog input voltage to VR / 2 as in the first embodiment. Similarly, A / D conversion is performed, and the result is stored in the data register. Since the input voltage is VR / 2, the expected conversion result should be that only the most significant bit is "1" and all lower bits are "0". The determination circuit calculates the difference between the converted result and the expected value. If the difference is within a preset error range, the self-adjustment function start flag is reset to indicate that the self-adjustment function is completed. If the error is out of the range of the error, the determination circuit adds one initial charging time setting bit in the control register, sets an A / D conversion start flag, and starts A / D conversion again. In this way, the determination circuit repeats the A / D conversion while increasing the initial charging time by one clock until the obtained conversion result falls within the range of a preset error, and resets the self-adjustment function start flag. To indicate that the self-adjustment function has been completed. The initial charge time setting bit set in this way is maintained as long as it is not changed, and once set, the A / D conversion start flag can be set by simply setting the A / D conversion start flag.
/ D conversion can be performed. Therefore, the user does not need to reset the initial charging time every time the use condition of the A / D converter changes, so that the application range is further expanded.
In addition, a bit for setting the allowable range of the error may be provided in the control register so that the user can arbitrarily select the allowable range of the error.

Configuration of Judgment Circuit As shown in FIG. 14, the judgment circuit calculates the difference between the conversion result stored in the data register and 10... 0 (ie, the ideal A / D conversion value of VR / 2). Subtractor SUB, comparator CMP for comparing the result with a preset allowable value, internal counter IC for setting initial charging time
T, a control register, an internal counter, and a timing circuit TC for controlling the analog input selector. The A / D converter used here is an A / D converter having an initial charging time changing function as described in the first embodiment.
It is a converter that can operate alone by writing a predetermined value to the control register. That is, the determination circuit can be considered as an external circuit of the A / D converter.

This A / D converter has an A / D conversion start flag ADST, initial charge time setting bits PT0 to PT2, and a self-adjustment operation start flag ST in a control register. When the ST flag is set to 1, the timing circuit resets the internal counter to 0 and writes the data to the control registers PT0 to PT2.
The flag is set to 1 to start A / D conversion.
At the same time, it outputs a control signal to switch the analog input selector to the VR / 2 side. When the A / D conversion is completed, the converter outputs an END signal for a certain period. The timing circuit latches the output of the comparator at the timing when the END signal becomes high level, and resets the ST flag if the output of the comparator is true (that is, the error is equal to or less than the allowable value), thereby completing the self-adjustment operation. At the same time, the analog input selector is switched to the SIN side. If the output of the comparator is false (that is, the error is equal to or more than the allowable value), the internal counter is incremented by one and written into PT0 to PT2 of the control register, the ADST flag is set to 1, and the A / D conversion is started again. Let it. In this manner, the value of the internal counter is incremented by one until the error becomes equal to or less than the allowable value.
Repeat D conversion.

(Embodiment 4) An embodiment in which two analog signal input terminals are provided and a magnitude comparison function of two analog signals is added will be described below.

FIG. 8 is a block diagram of the A / D converter of this embodiment. The control circuit CC and the selector ST are added to the A / D converter of FIG.
1, SIN2. The selector is a switching circuit for selectively giving an analog switch control signal generated by the successive approximation register and data stored in the data register to the analog block. The control circuit controls the operation of the selector, and Is a circuit for rewriting the contents of The two analog signal input terminals SIN1 and SIN2 are switched by analog switches.

In the present A / D converter, a two-terminal comparison mode start flag for starting the two-terminal comparison mode and a mode switching flag for switching between the A / D conversion mode and the comparison mode are provided in the control register. ing. The A / D conversion mode is a mode for performing a normal A / D conversion, and the comparison mode is a mode for comparing the magnitude of a digital value previously set in a data register with an analog input voltage value. When the mode switching flag is “0”, the A / D conversion mode is set, and when the mode switching flag is “1”, the comparison mode is set.

When the two-terminal comparison mode start flag is set, the control circuit sets the analog signal input terminal to SIN1.
, The mode switching flag is set to “0”, and A /
A / D conversion is started by setting a D conversion start flag. At this time, the selector is in a state of transmitting the analog switch control signal generated by the successive approximation register to the analog block as it is. A / D conversion is performed in the same manner as in the first embodiment, and the conversion result of the input SIN1 is stored in the data register.

Next, the control circuit sets the analog signal input terminal to S
The mode is switched to IN2, the mode switching flag is set to "1", the A / D conversion start flag is set, and the comparison mode is started. At this time, the selector is in a state of transmitting the data set in the data register (ie, the conversion result of SIN1) directly to the analog block. In the comparison mode, the first charging is performed in the same manner as in the A / D conversion mode, and when the initial charging time has ended, the analog switch SB is turned off, and the SA is switched to the VR side. The bit whose data set in the data register is “1” during the next one clock period switches the analog switch of the corresponding capacitor to the VR side, and the bit “0” activates the analog switch of the corresponding capacitor. Switch to GND side. As a result, the magnitude of the initially charged measured voltage is compared with the digital voltage value set in the data register. If the measured value is larger than the set value, the comparator outputs “1” and the measured value is set. If the value is smaller than the value, the comparator outputs “0”. Here, the data set in the data register is the conversion result of SIN1, and the voltage to be compared is SIN2. Therefore, this results in two analog voltage values SIN1 and SIN2.
And the two-terminal comparison mode start flag is reset to indicate that the comparison has been completed. The comparison result may be stored by providing a read-only flag in the control register. . Configuration of Control Circuit As shown in FIG. 15, the control circuit CC includes a ternary counter 3CT for counting an END signal from the A / D converter, a control register, and a timing circuit for controlling an analog input selector. The A / D converter used here is an A / D converter having two functions of an A / D conversion mode and a digital-analog comparison mode.
By writing a predetermined value to the control register, it can operate independently. That is, the control circuit can be considered as an external circuit of the A / D converter.

This A / D converter has flags ADM and A / D for switching operation modes in a control register.
It has a D conversion start flag ADST, a binary comparison mode start flag COMP, and a read-only flag DAT for storing the result. When ADM is 0, the A / D conversion mode is set. When ADM is 1, the digital-analog comparison mode is set. The ADM also has a data selector as shown in FIG. 16. When ADM is 0, the analog switch control signals DD0, D0 from the successive approximation register are provided.
Are output to the analog block, and when ADM is 1, data Q0,
Q1,... Are output to the analog block.

When the COMP flag is set, the timing circuit resets the ternary counter, sets the ADM flag of the control register to 0, and sets the ADST flag to 1
To start the A / D conversion mode. At the same time, the analog input selector is switched to the SIN1 side.
When the END signal indicating that the A / D conversion has been completed is input, the conversion result of the analog input SIN1 is stored in the data register. At this time, the value of the ternary counter is 1. The timing circuit sets the COMP flag to 1
If the value of the ternary counter is 1, the analog input selector is switched to the SIN2 side and the ADM flag is set to 1
To start the digital-analog comparison mode by setting the ADST flag. Then A
Since DM is 1, the value of the data register, that is, the A / D converted value of the analog input SIN1 is transmitted to the analog block. The successive approximation register also operates in the digital-analog comparison mode by the ADM signal. And EN
When the D signal is output, the comparison result is stored in DAT of the control register, and the value of the ternary counter becomes 2. If the COMP flag is 1 and the value of the ternary counter is 2, the timing circuit resets the COMP flag to indicate that the binary comparison mode has ended.

[0055]

According to the present invention, since only the initial charging time can be extended without lowering the clock frequency, sufficient accuracy can be obtained even at a low voltage without significantly increasing the conversion time. It is. Also, the initial charging time can be set arbitrarily according to the external conditions in which the A / D converter is used, so that one A / D converter can have versatility. Further, since it is not necessary to reset the initial charging time every time the use condition of the A / D converter changes, the application range of the A / D converter can be further expanded without increasing the load on software. Further, according to the present invention, it is possible to widen a margin for manufacturing variations, operating temperatures, noises, and the like, so that the operation of the A / D converter can be further stabilized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an A / D converter according to the present invention.

FIG. 2 is a schematic diagram of an 8-bit successive approximation type A / D converter.

FIG. 3 is a diagram showing a change in input node potential of a comparator during a first comparison period.

FIG. 4 is a cross-sectional view of a PMOS transistor.

FIG. 5 is a timing diagram of an A / D converter according to the present invention.

FIG. 6 is a diagram illustrating an example of a booster circuit.

FIG. 7 is a block diagram of an A / D converter according to the present invention.

FIG. 8 is a block diagram of an A / D converter according to the present invention.

FIG. 9 is a configuration diagram of a control register.

FIG. 10 is a configuration diagram of a successive approximation register.

FIG. 11 is an output timing chart of a control signal.

FIG. 12 is a configuration diagram of a circuit for setting an initial charging time.

FIG. 13 is a block diagram of a conventional successive approximation A / D converter.

FIG. 14 is a configuration diagram of a determination circuit.

FIG. 15 is a configuration diagram of a control circuit.

FIG. 16 is a circuit configuration diagram of a selector.

[Explanation of symbols]

C0-C8 Capacitors SA, SB, S0-S8 Analog switch (CMOS
Transfer gate) CP comparator CL control logic AB analog block DR data register CR control register AD address decoder CMR successive approximation register CT counter HC judgment circuit

Continuation of the front page (56) References JP-A-4-290310 (JP, A) JP-A-2-200010 (JP, A) JP-A-3-278717 (JP, A) JP-A-6-6223 (JP) JP-A-60-182220 (JP, A) JP-A-4-93774 (JP, A) JP-A-7-46133 (JP, A) JP-A-2-159814 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 1/00-1/88 G11C 27/02

Claims (2)

(57) [Claims] A capacitor array, a comparator and an analog circuit.
Charge redistribution type A /
In the D converter, the
Means for setting the initial value of the initial charge time of the analog measurement voltage;
Means for generating a constant analog voltage;
Compare the A / D conversion output value of
A comparing means to output a value within a predetermined range.
Until the initial charge time, the initial charge time is
Next changing means, and the predetermined analog
The voltage value is 1/2 of the analog reference voltage
A / D converter characterized by the above-mentioned. 2. The A / D converter according to claim 1 , wherein the back gate potential of the PMOS transistor of the analog switch connected to the comparator side node of the capacitor array is set to a predetermined voltage equal to or higher than the power supply voltage. A / D converter characterized by comprising means.