JP3222662B2 - Peak or bottom detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak or bottom detecting device for detecting a peak (top) or a bottom (bottom) of an input signal.

[0002]

2. Description of the Related Art This type of peak or bottom detecting device is used, for example, for setting a slice level at the time of burst transfer in optical communication. That is, the slice level is set based on the peak value of the input signal, and the analog input signal is AD-converted based on the slice level. For example, if the analog input signal is higher than the slice level, it is converted to a digital value of “1”, and if it is lower than the slice level, it is converted to a digital value of “0”.

Conventionally, such peak value detection of an input signal has been performed, for example, by a circuit shown in FIG. The detection of the bottom value of the input signal can be performed in the same manner as the detection of the peak value.

[0004] FIG. (A) is, AC (alternating current) is supplied to the capacitor C ₁ the current generated by the peak component of the input signal through the diode D _1, is stored as capacitance a peak value in the capacitor C ₁ circuit It is.

In the circuit shown in FIG. 1B, a transistor Q ₁ and a resistor R ₁ are connected in parallel with a transistor Q ₂ and a resistor R ₂ and a constant current source I ₀ connected in series with the transistor Q ₁ and the resistor R _2. Is configured. A
C input signal is applied to the base of one transistor Q _1, is at the peak of the input signal collector current of the transistor Q ₁ is increased, the collector current of the transistor Q ₂ is reduced. Therefore, the transistor Q ₃ base potential of the transistor Q ₃ rises amplifies the peak component of the input signal, charges corresponding to the peak component is supplied to the capacitor C _2. The amplifier circuit, the transistor Q ₃ and the capacitor C ₂ constitute a voltage follower circuit.
The peak value of the C input signal is accumulated and stored in the capacitor C _2. The output of the peak value detection, charge to the capacitor C ₂ is retained by a specified time that is stored.

[0006]

However, in the conventional peak value detecting device shown in FIG.
There is a disadvantage that the operation speed of the peak value detection is reduced. That is, as the charging voltage due to the accumulated charge of the capacitor C ₁ approaches the peak voltage of the input signal, the current flowing through the diode D ₁ decreases, and the operation speed of the peak value detection decreases.

When a circuit having a peak detecting function like the device shown in FIG. 1B is constituted by a bipolar transistor, in addition to the arrangement by a wide band amplifier shown in FIG. A configuration using a dynamic amplification circuit is conceivable. However, when a differential amplifier circuit having an active load is used, its operation speed is generally slow, and a high-speed peak detection circuit cannot be formed. For this reason, when a high-speed peak detection circuit is configured, the broadband amplifier circuit configuration shown in FIG. 3B is adopted, and the circuit configuration is the above-described voltage follower. However, when a peak value detection device is configured with such a broadband amplifier circuit and the peak value detection output is received by an emitter follower or the like, the peak value detection output cannot be held for a long time. That is, the current required to drive the emitter follower is the capacitor C ₂
To be supplied from, reduces the discharge time constant of the charge stored in the capacitor C _2, decreases also the retention time of the peak value detection output.

[0008]

SUMMARY OF THE INVENTION A peak or bottom detecting device according to the present invention has been made in order to solve such a problem, and detects a peak (or bottom) of an input signal at a predetermined speed. The amount of charge corresponding to the peak value (or the value of the bottom) is stored in the first capacitor, and the amount of charge is held in the first capacitor for a predetermined time, and is stored in the first capacitor. First detection means for outputting a first detection signal corresponding to the charge amount with time, detecting a peak (or bottom) of the input signal at a speed lower than the predetermined speed, and detecting a value of the peak. (Or the value of the bottom) is stored in the second capacitor, and the charge is held in the second capacitor for a time longer than the predetermined time, and is stored in the second capacitor. And outputs a second detection signal corresponding to the charge amount with time. A second detection unit, which inputs the first detection signal and the second detection signal, and outputs a larger (or smaller) of the first detection signal and the second detection signal; Calculating means for outputting the peak value (or bottom value) of the input signal over time. Further, the peak or bottom detecting device of the present invention detects a peak (or bottom) of an input signal at a predetermined speed, and stores a charge amount corresponding to the peak value (or bottom value) in the first capacitor. A first detection unit that holds the charge amount in the first capacitance for a predetermined time and outputs a first detection signal corresponding to the charge amount accumulated in the first capacitance with time; Means for detecting a peak (or bottom) of the first detection signal at a speed lower than the predetermined speed, and storing a charge amount corresponding to the peak value (or bottom value) in the second capacitor Then, the charge amount is held in the second capacitor for a time longer than the predetermined time, and a second detection signal corresponding to the charge amount stored in the second capacitor is output with time. A second detection unit that performs the first detection signal and the second detection signal. Computing means for outputting the larger (or smaller) of the first detection signal and the second detection signal as the peak value (or bottom value) of the input signal over time. It may be characterized in that.

[0009] The present invention is also characterized in that a return circuit is provided for discharging the electric charge accumulated in the capacitor constituting the second detecting means in response to the reset input.

[0010]

The signal corresponding to the peak or bottom of the input signal is promptly transmitted to the calculating means by the first detecting means, and is held and output to the calculating means for a long time by the second detecting means.

Further, by providing a return circuit, a peak or bottom of a signal input from an arbitrary time is detected.

[0012]

FIG. 1 is a block diagram showing a schematic configuration of a peak detector according to one embodiment of the present invention. The first peak detection circuit A performs a high-speed peak detection operation, but has a circuit configuration in which the charge stored in the capacitor C _A (first capacitance) has a short retention time. The second peak detection circuit B has a circuit configuration in which the operation speed is somewhat slow, but the electric charge accumulated in the capacitor C _B (second capacitance) has a long retention time.
These first and second peak detection circuits A and B are connected in series with the input signal. The arithmetic circuit C is configured to take the sum of the detection outputs of the circuits A and B, and selects and outputs a higher output voltage among the detection outputs. Further, the minute current source circuit D includes the capacitors C _A ,
Pull the minute current from the C _B, the capacitor C _A, C _B
To control the discharge time constant of the electric charge accumulated in the memory.

The configuration of the first peak detection circuit A may be a conventional wideband amplification circuit configuration shown in FIG. 6B which is fast but has a short charge retention time. In addition, the circuit that receives the peak detection output in the second peak detection circuit B obtains a long holding time of the peak detection output.
A circuit configuration using an OSFET is suitable.

The circuits shown in FIGS. 2, 3 and 4 are:
This is a peak detection device that further embodies the circuit schematically shown in FIG.

[0015] AC input signal is input to the base of the transistor QI _1. Resistor RI ₂ and transistor QI ₂
Is connected in parallel with the transistor QI _1, and the transistor QI ₁ is connected in series with the transistors QI ₁ and QI _2.
A series circuit consisting of ₃ and a resistor RI ₄ is connected. Transistor QI ₃ is biased to a constant voltage by the transistor QI ₄ and the resistor RI _1, RI _3, transistors QI ₃ and the resistor RI ₄ forms a constant current source, a broadband amplifier circuit configured by the transistors QI ₁ ~QI ₃ Have been. Further, the collector of the transistor QI ₂ are transistors QI ₅ is connected, the transistor QI ₅ controls the supply of electric charge to the capacitor CI ₁ through the resistor RSP. The circuit so far corresponds to the first peak detection circuit A shown in FIG. 1 which is fast and has a short charge holding time, and also corresponds to the conventional circuit shown in FIG. 6B.

Transistors QI ₆ and QI ₇
And a transistor QI ₉ and a resistor RI ₈ connected in series to each of these transistors constitute a differential amplifier circuit. Transistors QPI ₁ , QPI ₂ and QPI ₅ constitute a mirror circuit, and serve as an active load of this differential amplifier circuit. Also, the transistor QI ₈
Is a transistor QI that supplies a constant current to the differential amplifier circuit.
_A constant bias is applied to ₉ and transistors QI ₁₂ and QI ₁₃ to be described later. Also, the transistor QP
I ₄ and QPI ₆ correspond to a transistor QPI ₇ described later.
Giving a constant bias against and QPI _3.
Each of these bias voltages is set to a desired value by a bias input.

One of the transistors constituting the differential amplifier circuit
QI₇Diode QI on the collector side of₁₉Is connected
This diode QI₁₉From resistance RI₆Through
Capacitor CI_TwoIs supplied with the charge. This capacitor
CI_TwoTerminal voltage is the resistance RI ₆Through p-channel MO
MPI which is SFET₁Given to the gate. Tran
Jista MPI₁And transistor QPI₇Series circuit
Has a capacitor CI_TwoCurrent corresponding to the charging voltage
And the transistor QI_FifteenIs driven by this energization
You. Further, the transistor QI_FifteenAnd Transis
QI₁₂The series circuit consisting of constitutes a differential amplifier circuit
One transistor QI₇Negative feedback on the base of
Transistor QI₇Transistor QI₆of
Approach the base potential.

Further, the charging voltage of the capacitor CI ₂ is applied to the gate of the MPI ₂ is a p-channel MOSFET. Transistor MPI ₂ and transistor QPI
The series circuit composed of _3, current flows in accordance with the charging voltage of the capacitor CI _2, the transistor Q by the energization
I ₁₄ is driven. A series circuit consisting of transistors QI ₁₄ and the transistor QI ₁₃ constitute an output buffer, the current output in accordance with the charging voltage of the capacitor CI ₂ is obtained through the transistor QI _14. The circuits from the differential amplifier circuit with the mirror circuit as a load up to this point constitute a second peak detection circuit B shown in FIG. 1 which is somewhat slow but has a long charge retention time.

FIG. 3 is connected to the circuit shown in FIG. 2 via each of the connectors a to d.
1 corresponds to the arithmetic circuit C shown in FIG.

Transistor QI₁₆, QI₁₇And tran
Jista QI₁₈Has a second peak
The output of the detection circuit B is the transistor QI₁₄Given by
You. Transistor QI₂₀, QI_{twenty one}And QI_{twenty two}Consists of
The output of the first peak detection circuit A is connected to the differential amplifier circuit.
Capacitor CI₁Given by In each differential amplifier circuit
Transistor QI forming a constant current source₁₈, QI_{twenty two}To
Is the transistor QI₁₉And resistance RI₁₁, RI₁₈By
Thus, a constant bias is given. Each differential amplifier circuit
, That is, the sum of the outputs of the peak detection circuits A and B
Is the transistor QI_{twenty three}, QI_{twenty four}And QI_{twenty five}Taken by
Is output. The transistor QI ₂₆, QI₂₇
And QI₂₈The differential amplifier circuit consisting of
And the lower limit of the peak detection output is set.
It is not directly related to the peak detection of the embodiment.

The circuit shown in FIG. 4 is connected to the circuit shown in FIG. 2 via a connector e, and corresponds to the minute current source circuit D shown in FIG.

The transistors QX ₁ and QX _{2 form} a Widler circuit, and a constant current determined by the transistor QPX ₁ flows through the transistor QX ₁ . Further, a constant current, which is a constant multiple of the constant current determined by the ratio of the emitter dimensions of transistors QPX ₁ and QPX ₂ , flows through transistor QX ₂ . That is, the transistors QPX ₁ and QPX ₂ constitute a mirror circuit.
Therefore, the base potential of the transistor QX ₂ is a constant current determined by the emitter size ratio of transistors QPX ₁ and QPX ₂ is kept constant potential generated by flow through the resistor RX _1. Thus, the transistor QX ₃ always the constant potential is biased. Further, the base potential of the transistor QPX ₃ is the same as that of the transistor QP
It is set equal to each base potential of X ₁ and QPX ₂ , and the current flowing through this transistor QPX ₃ is determined by its emitter size. This current flows through the resistor RX ₃ ,
Through transistor QX ₃ and resistor RX _2. The transistor QX ₃ is biased to a constant voltage by Uidora circuit, the collector potential becomes the value obtained by subtracting the voltage drop of resistor RX ₃ from the level shift voltage of the transistor QX _4, it is always kept at a constant potential . As a result, the transistor QX ₅ that this constant potential is biased, a constant and a constant current is applied. The value of this constant current is
A desired value can be set by arbitrarily selecting parameters such as the emitter dimensions of the transistors QPX ₁ , QPX ₂ , and QPX ₃ and the resistance value of the resistor RX ₃ .

The charges accumulated in accordance with the peak signal input to the capacitor CI ₂ is withdrawn by the transistor QX ₅ at a predetermined ratio. Thus, the capacitor CI ₂
By pulling a constant current to the transistor QX ₅ from the discharge time constant of the accumulated charge is controlled. That is, the charging voltage of the capacitor CI ₂ is input to and output from the gate of the MPI _2. However, since the input impedance of the gate of the pMOSFET is extremely high, if the minute current source shown in FIG. The discharge time constant of the charge stored in ₂ becomes extremely large. For this reason, the peak detection period of the input signal becomes longer, and as a result, peak detection is performed even for noise having a large peak value, and accurate circuit operation is not performed. That is, the minute current source serves other to set the charge retention time of the capacitor CI _2, to release the extra charge circuitry is generated in the capacitor CI ₂ in the case and the external noise or the like is not stable enough, the detection signal At the stable point, that is, within the range of the peak level of the input signal.

In such a configuration, when the peak component of the input signal is given to the transistor QI ₁ forming the first peak detection circuit A, the collector current of the transistor QI ₂ is increased against the increase of the collector current of the transistor QI _1. There decreased, the base potential of the transistor QI ₅ is increased. Transistor QI ₅ is driven by the rising of the base potential, and supplies the charges corresponding to the peak input signal to the capacitor CI ₁ through the resistor RSP. At this time, since the capacitor CI ₁ and resistor RI ₂ are connected in series,
At high frequency, the impedance viewed from the transistor QI ₅ is reduced is suppressed. Therefore, the capacitor C
The terminal voltage of the I _1, i.e., an excessive increase of the voltage at the node I ₂₃ is suppressed, the voltage of the node I ₂₃ is rapidly and smoothly increased in accordance with the peak signal is input, the voltage increase is an arithmetic circuit C It is transmitted immediately to the transistor QI ₂₀ to.

Further, increase in the voltage of the capacitor CI ₁ is transmitted to the transistor QI ₆ constituting the second peak detection circuit B, increasing the base voltage of the transistor QI _6. Therefore, the collector current of transistor QI ₆ increases, and this increase in current is transmitted to node I ₂₂ by the mirror circuit. On the other hand, the collector current of the transistor QI ₇ is relatively decreased by an increase in the collector current of the transistor QI _6. Therefore, excess current supplied by mirror circuit is output to the capacitor CI ₂ via the diode QI ₁₉ from node I _22. Therefore, the terminal voltage of the capacitor CI ₂ rises in accordance with the peak signal input. The voltage rise of the capacitor CI ₂ is caused by the transistor MP
Through the I ₁ and transistor QI _15, it is fed back to the transistor QI ₇ constituting the differential amplifier circuit. For this reason,
As the base potential of the transistor QI ₆ rises in response to the peak signal input, the base potential of the transistor QI ₇ rises, and the peak of the input signal is detected.

The voltage rise of the capacitor CI ₂ which increases with the peak signal input is transmitted to the transistor QI ₁₆ to an arithmetic circuit C via the high transistor MPI ₂ and the transistor QI ₁₄ input impedance.
The output of the voltage held by the capacitor CI ₂ is output from a differential amplifier circuit composed of transistors QI ₆ and QI ₇ to a PNP circuit.
Since a mirror circuit composed of transistors is used as an active load, the capacitor CI in the first peak detection circuit A
_It takes place somewhat slower than the voltage output of ₁ . However, the movement of the charge stored in the capacitor CI ₂ is caused by the pMOSFET
Since the input resistance of the transistor MPI ₂ is high, it is almost entirely performed by the small current source shown in FIG. 4 connected in parallel with the capacitor CI ₂ . Therefore, the discharge time constant of the accumulated charge capacitor CI ₂ is controlled by a small current source, the peak voltage output is held by an arbitrary time.

The charging voltage of the capacitor CI ₂ in the second peak detecting circuit B is determined by the transistor QI ₇
For stably be rapidly fed back to, being drawn by transistors MPI ₁ via the resistor RI _6. Further, to output the charging voltage of the capacitor CI ₂ fixed time held to, separately from the path for the feedback, the charging voltage of the capacitor CI ₂ is removed from the transistor MPI _2. That is, the terminal voltage of the capacitor CI ₂ is removed from the different points in each transistor MPI _1, MPI ₂ is for individually controlling the peak value detecting operation and the charge retention time.

The transistor Q constituting the arithmetic circuit C
The differential amplifier circuit composed of I ₂₀ and QI ₂₁ is provided with the detection output of the first peak detection circuit A having a high peak detection operation speed but a short charge holding time, and the result of the peak detection is immediately applied to the transistor QI ₂₄ . Output via Further, the differential amplifier circuit composed of the transistors QI ₁₆ and QI ₁₇ receives the detection output of the second peak detection circuit B whose peak detection operation is somewhat slow but has a long charge holding time, and the peak detection result is a transistor. Output for a long time via QI ₂₃ . Since the emitters of the transistors QI ₂₃ and QI ₂₄ are commonly connected, the sum of the detection outputs of the peak detection circuits A and B is obtained at the output terminal. That is, the peak of the AC input signal is detected at high speed, and this peak value is held and output for a long time.

FIG. 5 shows a return circuit for forcibly extracting the charges stored in the capacitors CI ₁ and CI ₂ and resetting the first and second peak detection circuits A and B.

The collector current generated by the input of the reset pulse to the transistor QPR ₆ is differentiated by the capacitor CR ₁ . The differentiated output, the transistor QP whose collector is connected to the capacitor CI ₁
R ₁ and the collector are amplified by the transistor QPR ₂ connected to the capacitor CI ₂ , and each of the capacitors CI ₁ ,
The charge stored in CI ₂ is extracted in a short time. Since the accumulated charge of the capacitor CI ₁ is easy to discharge, the reset of the peak detector is accomplished by pulling the electric charge of the capacitor CI _2.

By providing such a reset circuit in the peak detector, it is possible to detect the maximum input signal level from an arbitrary timing. Therefore, for example, when a peak detection circuit malfunctions due to noise or the like, a new peak detection operation can be performed from an arbitrary timing by giving a reset pulse to the reset circuit.

[0032] In the description of the above embodiment, in order to obtain the output of the long retention time of the capacitor CI _2, it was the current amplified by a source follower circuit using a MOSFET output capacitor CI _2, a too long time Output when there is no need to hold, i.e. by holding time as soon as may be configured to current amplifies the output of the capacitor CI ₂ in a circuit using a bipolar transistor. Also,
Although the second peak detection circuit B has been described as a differential amplifier circuit configuration having an active load, if the peak detection efficiency is sufficient, the second peak detection circuit B may be replaced with a MOSFE.
A wideband amplifier circuit that operates at high speed in a wideband using T may be used. In each of these cases, the same effect as in the above embodiment can be obtained.

In the above embodiment, the case where the first peak detection circuit A and the second peak detection circuit B are connected in series with the input signal has been described. However, the connection form of each of the peak detection circuits A and B does not need to be limited to the connection form of the above embodiment. For example, each of the peak detection circuits A and B
May be connected in parallel to the input signal, and the detection outputs of the detection circuits A and B may be connected to the arithmetic circuit C.
Further, in the above-described embodiment, the case where the apparatus is configured using one detection circuit A and one detection circuit B is described. However, the apparatus may be configured using one or more circuits A and B. For example, a first peak detection circuit A and a second peak detection circuit B
A configuration in which the first peak detection circuit A is further connected in series with respect to the series connection with. By selecting any of these various connection types, it is possible to achieve a trade-off between the peak detection speed and the charge retention time according to the application.

In the above embodiment, the case where the peak value of the input signal is detected has been described. However, the present invention can be similarly applied to the case where the bottom value of the input signal is detected. Similar effects are achieved.

[0035]

As described above, according to the present invention, the signal corresponding to the peak or bottom of the input signal is immediately transmitted to the calculating means by the first detecting means, and is transmitted by the second detecting means. It is held and output to the arithmetic means for a long time. For this reason, a signal corresponding to the peak or bottom of the input signal is output at high speed from the arithmetic means and is output for a long time.

Further, by providing a return circuit, a peak or bottom of a signal input from an arbitrary time is detected. Therefore, even if the device malfunctions,
A new peak or bottom can be detected quickly.

Therefore, such a peak or bottom detecting apparatus according to the present invention is particularly effective when applied to a slice level setting at the time of burst transfer in optical communication.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a peak detection device according to one embodiment of the present invention.

FIG. 2 is a circuit diagram further embodying the circuits A and B shown in FIG.

FIG. 3 is a circuit diagram further embodying the circuit C shown in FIG.

FIG. 4 is a circuit diagram further embodying the circuit D shown in FIG. 1;

FIG. 5 is a return circuit diagram for resetting the electric charge accumulated in the peak detection device.

FIG. 6 is a circuit diagram showing a conventional peak detection device.

[Explanation of symbols]

Circuit A: a first peak detection circuit that detects an input signal at high speed but has a short charge holding time; circuit B: a second peak detection circuit and a circuit that detects input signals at a somewhat low speed but has a long charge holding time C ... arithmetic circuit that takes the sum of the detection output of the circuit a and circuit B, C _a, C _B ... storage capacity for accumulating charges corresponding to the peak or bottom of the input signal, the constant current from the circuit D ... storage capacity A small current source circuit that adjusts the discharge time constant by pulling.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mikio Keimasu 1126 Nomachi, Hamamatsu-shi, Shizuoka Prefecture Inside Hamamatsu Photonics Co., Ltd. (72) Inventor Kiyoshi Yamashita 216 Totsukacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. (72) Inventor Atsushi Hasegawa 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi, Ltd. (72) Inventor Yutaka Hasegawa 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi, Ltd. (72) Inventor Hamagishi Takahiro 180 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa

Claims (10)

(57) [Claims] 1. A method for detecting a peak of an input signal at a predetermined speed, storing a charge corresponding to a value of the peak in a first capacitor, and holding the charge in the first capacitor for a predetermined time. A first detection unit that outputs a first detection signal corresponding to the amount of electric charge stored in the first capacitor with time, and a speed at which the peak of the input signal is lower than the predetermined speed. And accumulates the charge amount corresponding to the peak value in the second capacitor, holds the charge amount in the second capacitor for a time longer than the predetermined time, and stores the charge amount in the second capacitor. A second detection unit that outputs a second detection signal corresponding to the accumulated charge amount with time, and inputs the first detection signal and the second detection signal,
A peak detecting apparatus comprising: a calculating unit that outputs a larger one of the first detection signal and the second detection signal as a peak value of the input signal with time. 2. A peak of an input signal is detected at a predetermined speed, a charge corresponding to the value of the peak is stored in a first capacitor, and the charge is held in the first capacitor for a predetermined time. A first detection unit that outputs a first detection signal corresponding to the amount of the electric charge accumulated in the first capacitor with time, a peak of the first detection signal is calculated based on the predetermined speed. Detecting at a slower speed, accumulating a charge amount corresponding to the peak value in the second capacitor, holding the charge amount in the second capacitor for a time longer than the predetermined time, and A second detection unit that outputs a second detection signal corresponding to the amount of charge accumulated in the capacitor with time, and the first detection signal and the second detection signal,
A peak detecting apparatus comprising: a calculating unit that outputs a larger one of the first detection signal and the second detection signal as a peak value of the input signal with time. 3. A minute current which is connected in parallel to the second capacitance of the second detecting means and controls a discharge time constant of the second capacitance by drawing a constant current from the second capacitance. 3. The peak detection device according to claim 1, further comprising a source. 4. The apparatus according to claim 1, further comprising a resistor connected in series to said first capacitor of said first detection means and controlling said predetermined speed for detecting a peak of said input signal. 3. The peak detection device according to 1 or 2. 5. A circuit according to claim 1, further comprising a return circuit for discharging the electric charge stored in said second capacitance of said second detecting means in response to a reset input.
2. The peak detection device according to 1. 6. A bottom of an input signal is detected at a predetermined speed, a charge corresponding to a value of the bottom is stored in a first capacitor, and the charge is held in the first capacitor for a predetermined time. A first detection unit that outputs a first detection signal corresponding to the amount of electric charge accumulated in the first capacitor with time, and a bottom speed of the input signal that is lower than the predetermined speed. And the amount of charge corresponding to the value of the bottom is stored in the second capacitor, and the amount of charge is held in the second capacitor for a time longer than the predetermined time. A second detection unit that outputs a second detection signal corresponding to the accumulated charge amount with time, and inputs the first detection signal and the second detection signal,
A bottom detecting device comprising: a calculating unit that outputs a smaller one of the first detection signal and the second detection signal as a bottom value of the input signal with time. 7. A bottom of an input signal is detected at a predetermined speed, a charge corresponding to a value of the bottom is stored in a first capacitor, and the charge is held in the first capacitor for a predetermined time. A first detection unit that outputs a first detection signal corresponding to the amount of the electric charge accumulated in the first capacitor with time, and a bottom of the first detection signal is detected from the predetermined speed. Detecting at a slower speed, accumulating an amount of charge corresponding to the value of the bottom in the second capacitor, holding the amount of charge in the second capacitor for a time longer than the predetermined time, and A second detection unit that outputs a second detection signal corresponding to the amount of charge accumulated in the capacitor with time, and the first detection signal and the second detection signal,
A bottom detecting device comprising: a calculating unit that outputs a smaller one of the first detection signal and the second detection signal as a bottom value of the input signal with time. 8. A minute current which is connected in parallel to said second capacitance of said second detection means and controls a discharge time constant of said second capacitance by drawing a constant current from said second capacitance. The bottom detecting device according to claim 6, further comprising a source. 9. The apparatus according to claim 1, further comprising a resistor connected in series with said first capacitor of said first detecting means, said resistor controlling said predetermined speed for detecting a bottom of said input signal. 8. The peak detection device according to 6 or 7. 10. The peak according to claim 6, further comprising a return circuit for discharging the electric charge stored in said second capacitance of said second detecting means in response to a reset input. Detection device.