JP3221929B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a built-in circuit for lowering an external power supply voltage and guaranteeing its operation in a wide range of the power supply voltage. 2. Description of the Related Art In recent years, along with the demand for miniaturization of processing dimensions of constituent elements and reduction in power consumption due to high integration of semiconductor devices, lowering of power supply voltage (for example, from the mainstream current 5 V to 3.0 V or 3.3 V). Migration) is required. On the other hand, since it is necessary to use conventional semiconductor devices and other components in a mixed manner, not only operation at a low voltage but also operation at a normal power supply voltage as a whole device is performed. It is desired to guarantee.

[0002]

2. Description of the Related Art In a conventionally known technique, an existing semiconductor device is forcibly used at a low voltage without special measures. Therefore, when used at a low voltage, the characteristics of the transistor constituting the semiconductor device are degraded because the transistors included in the semiconductor device are not sufficiently optimized (for example, the gate oxide film is made thinner and the channel length is made shorter) for the low voltage. Was remarkable.

For this reason, a conventional semiconductor device employs a method of stepping down an external power supply voltage (usually 5 V) to an appropriate low voltage inside the device (that is, a method of simply stepping down the power supply voltage). Therefore, the transistor is optimized for the step-down voltage to ensure the characteristics of the semiconductor device.

[0004]

In a conventional semiconductor device using a technique of merely stepping down a power supply voltage, there are various problems as described below, that is, (1) problems of a step-down circuit itself, and (2) And (3) a problem with the output stage circuit. (1) Problems of the step-down circuit itself FIG. 7 shows an example of a voltage step-down circuit in a conventional semiconductor device, and FIG. 8 shows its operation characteristic waveform.

In FIG. 7, Vcc indicates an external power supply voltage (line), Vss indicates a reference power supply voltage (line) of the semiconductor device, and Vci indicates a reduced internal voltage. The circuit shown in the figure has a constant current source IS connected to a power supply line Vcc, and an n connected in series between the output terminal of the constant current source and the power supply line Vss and each gate connected to a respective drain.
Channel transistors QT1 to QTn and power supply line V
and an n-channel transistor Q30 connected between cc and an internal voltage (Vci) generation node and responsive to a signal at the drain end of the transistor QT1.

[0006] In this circuit configuration, as shown in operation characteristic diagram of FIG. 8, since the external voltage Vcc is to be kept constant inside voltage Vci to the level of V ₂ is greater than or equal to the level of V _1, ideal voltage step-down There is an advantage that can be performed. However, on the other hand, the gate potential (reference voltage) of transistor Q30 for converting external voltage Vcc to step-down voltage Vci is determined based on each voltage drop (that is, threshold level) of transistors QT1 to QTn. A problem arises when the power supply voltage or the power supply voltage fluctuates. That is, since the voltage drop amount of each of the transistors QT1 to QTn fluctuates and the gate potential of the transistor Q30 fluctuates accordingly, the operation of the transistor Q30 becomes unstable, and thus the step-down voltage Vci can be output stably. There is a drawback that you can not.

Further, since a voltage drop is generated in each of the transistors QT1 to QTn using the constant current source IS, there is a disadvantage that current is always consumed. (2) Problem of input stage circuit FIG. 9 shows an example of an address input circuit in a conventional semiconductor device. The illustrated circuit is driven by the step-down voltage Vci generated by the voltage step-down circuit shown in FIG. 7, for example.
A p-channel transistor Q31 having a source connected to the step-down voltage Vci line and responding to the potential of Vss, and a CMOS inverter (p) connected between the drain of the transistor and the power supply line Vss and responding to the address input signal.
Channel transistor Q32 and n-channel transistor Q33), and n-channel transistor Q3 connected in parallel with transistor Q33 and responding to the potential of Vss.
4 and a CMOS inverter (p-channel transistor Q35 and n-channel transistor Q36) connected between the power supply lines Vci and Vss and responsive to the outputs of the inverters (Q32, Q33).

In this circuit configuration, since the internal power supply is driven by the internal step-down voltage Vci, the normal power supply voltage V
There is a problem that the input threshold level of the input circuit is lower than that in the case of driving with cc, and the input circuit is weak against noise. For example, a transistor may malfunction due to noise or the like generated internally. When the address input signal is V
When the amplitude is changed at a level of cc to Vss, there is a disadvantage that a noise (coupling noise) component based on capacitive coupling with an external signal wiring increases.

(3) Problem of output stage circuit FIG. 10 shows an example of a data output circuit in a conventional semiconductor device. The circuit shown is similar to the circuit of FIG.
For example, a CMOS inverter (p-channel transistor) driven by the step-down voltage Vci generated by the voltage step-down circuit shown in FIG. Q37 and an n-channel transistor Q38).

In this circuit configuration, the data signal from the internal circuit is driven by the internal step-down voltage Vci.
When the amplitude changes with the amplitude of Vss, the output signal also changes accordingly.
It changes with the amplitude of ci to Vss. Therefore, a circuit connected to the output stage of the data output circuit operates at a normal power supply voltage (5 V
System), there is a problem that the matching with the elements used in the circuit is not good. In some cases, there may be a disadvantage that a signal of a predetermined logic level cannot be transmitted stably.

FIG. 11 shows another example of a conventional data output circuit. The circuit shown is an external power supply voltage V
It is constituted by a CMOS inverter (p-channel transistor Q39 and n-channel transistor Q40) which is driven by cc, is connected between the power supply lines Vcc and Vss, and responds to a data signal from an internal circuit.

In this circuit configuration, since it is driven by the power supply voltage Vcc, there is no problem in matching with external elements driven by the same 5 V system voltage. However, when the data signal from the internal circuit changes with the amplitude of Vci to Vss, when the input level is Vss, only the p-channel transistor Q39 is turned on and the n-channel transistor Q40 is cut off. Input level is V
At the time of ci, since the p-channel transistor Q39 is also turned on depending on the level difference between the power supply voltage Vcc and the step-down voltage Vci, a problem arises that a through current flows from the power supply line Vcc to Vss through the transistors Q39 and Q40. In some cases, the transistor element may be destroyed, which is disadvantageous.

The present invention has been made in view of the problems in the prior art, and has as its object to provide a semiconductor device capable of reducing current consumption and stably supplying an external power supply voltage. And Another object of the present invention is to maintain good matching with each element including an external element even when an external voltage and an internal step-down voltage are used in combination, and eliminate the influence of noise to improve the operation reliability. An object of the present invention is to provide a semiconductor device which contributes to improvement of the semiconductor device.

[0014]

According to the present invention, a first power supply voltage and a second power supply voltage are supplied from outside , and a drain is provided.
Is connected to the first power supply voltage and the source is
Depletion type transformer connected to the
A transistor, a nonvolatile storage element, and a nonvolatile storage element.
The gate of the depletion type transistor according to the contents
The first power supply voltage or the second power supply voltage
And a circuit of the depletion type transistor.
When the first power supply voltage is applied to the gate,
The first power supply voltage is output from the external voltage generation node;
The second power supply is connected to the gate of the depression type transistor.
When a voltage is applied, from the internal voltage generation node
A predetermined voltage between the first power supply voltage and the second power supply voltage.
A semiconductor device is provided which outputs a pressure .

[0015]

[0016]

According to the above-described structure, a transistor is used as a means for reducing an external power supply voltage to a predetermined internal voltage, and the transistor is driven by applying a stable predetermined reference voltage to the gate of the transistor. Therefore, a stable internal step-down voltage can be obtained without causing unnecessary current consumption as in the conventional type (see FIG. 7).

When a smoothing capacitor is provided at the internal voltage generation node, the level of the internal step-down voltage output to the node can be further stabilized. The details of other structural features and operations of the present invention will be described with reference to the accompanying drawings and embodiments described below.

[0018]

FIG. 1 shows an example of the configuration of a voltage step-down circuit in a semiconductor device according to the present invention. In this embodiment, a depletion type n is used as an element for converting an external power supply voltage Vcc into a reduced internal voltage Vci for an internal circuit.
The channel transistor Q is used. The gate of the transistor Q is connected to a reference power supply line Vss (that is, a stable ground level = 0 V reference voltage) of the device, the drain thereof is connected to a high-potential power supply line (that is, an external voltage Vcc), and the source is connected. Is connected to the generation node N of the internal voltage Vci. The threshold level of the depletion type transistor Q is set to Vth = -Vci. A smoothing capacitor C is connected between the internal voltage generation node N and the low potential power supply line Vss.

According to the configuration of this embodiment, the gate of the transistor Q for converting the external power supply voltage Vcc to the reduced internal voltage Vci is connected to the stable and stable level reference voltage line Vss. In addition, since there is no inconvenience that a current always flows as seen in the configuration of FIG. 7, a stable internal step-down voltage Vci can be obtained.

Since the smoothing capacitor C is provided at the internal voltage generation node N, the level of the internal step-down voltage Vci output to the node N can be further stabilized. In the present embodiment, the configuration is such that only the stepped-down internal voltage Vci is extracted from the internal voltage generation node N.
The internal voltage (Vci) can be easily switched to the normal power supply voltage (Vcc) and output.
An example of the circuit is shown in FIG.

The circuit shown in FIG. 2 has an internal step-down voltage Vci.
Alternatively, a nonvolatile memory cell QM such as an EPROM is provided as an element for determining which of the external voltage Vcc is output. This nonvolatile memory cell QM is connected between a reference power supply line Vss and an internal node P, and its control gate is connected to a power supply line of an external voltage Vcc. The nonvolatile memory cell QM allows a current to flow or does not flow a current according to the stored contents. Therefore, the potential of the internal node P exhibits the “L” level when the memory cell QM flows a current, and the “H” level when the memory cell QM does not flow a current.

A p-channel transistor Q1 is connected between the high potential power supply line Vcc and the internal node P.
A CMOS inverter (p-channel transistor Q2 and n-channel transistor Q3) is connected between the power supply line Vcc and the low-potential power supply line Vss, and both gates of the transistors are connected to the internal node P. The drains are both connected to the gate of the p-channel transistor Q1. Similarly, power supply lines Vcc and V
Between ss, another CMOS inverter (p-channel transistor Q4 and n-channel transistor Q5)
Are connected, the gates of the transistors are both connected to the output terminals of the inverters (Q2, Q3), and the drains are both connected to the gate of the transistor Q (see FIG. 1).

That is, in the embodiment of FIG. 2, the power supply voltage Vcc
Is converted to an internal voltage Vci (or Vcc), the gate of the transistor Q is not a fixed reference potential Vss as in the embodiment of FIG. 1, but a potential determined depending on the contents of the nonvolatile memory cell QM. (Ie, “H” level or “L” level appearing at the internal node P).

Therefore, when a current flows through nonvolatile memory cell QM, internal node P attains an "L" level.
An "L" level signal is applied to the gate of transistor Q via the inverter at the stage, and the transistor is cut off. As a result, the reduced internal voltage Vci is output to the internal voltage generation node N. On the other hand, when no current flows through nonvolatile memory cell QM, internal node P attains an "H" level. Contrary to the above operation, when internal transistor P is turned on, internal voltage generating node N receives external power supply voltage. Vcc is output.

FIG. 3 shows a configuration example of an input stage circuit of a semiconductor device to which the above-mentioned voltage step-down circuit is applied. In the illustrated input stage circuit, at least a part of the circuit has an internal step-down voltage Vci.
An input signal Si (for example, an address signal in the case of a semiconductor memory) is transmitted to an internal circuit (not shown) driven by an external power supply voltage V.
It has a circuit section driven by cc and a circuit section driven by the reduced internal voltage Vci.

The circuit section driven by the external power supply voltage Vcc has a source connected to the power supply line Vcc and responsive to the potential of Vss, a p-channel transistor Q11 connected between the drain of the transistor and the power supply line Vss, and CMOS inverter (p-channel transistor Q12 and n-channel transistor Q12) responding to input signal Si
13) and VQ connected in parallel with transistor Q13.
an n-channel transistor Q14 responsive to the potential of ss;
It has a CMOS inverter (p-channel transistor Q15 and n-channel transistor Q16) connected between the power supply lines Vcc and Vss and responsive to the output of the inverter (Q12, Q13). Transistor Q1
5, Q16 are amplitudes Vcc to V output from the preceding circuit.
It has the function of stabilizing the level of the ss signal and transmitting it to the subsequent stage.

On the other hand, the circuit section driven by the internal step-down voltage Vci includes a line of the internal step-down voltage Vci and a power supply line Vss.
A CMOS inverter (p-channel transistor Q17 and n-channel transistor Q18) connected between the inverters and responsive to the output of the inverter (Q15, Q16);
It also has a CMOS inverter (p-channel transistor Q19 and n-channel transistor Q20) connected between power supply lines Vci and Vss and responsive to the output of inverters (Q17, Q18).

According to the circuit configuration of FIG. 3, since the circuit portion directly receiving the input signal Si is driven by the external power supply voltage Vcc, the input threshold level is lower than that of the conventional configuration (see FIG. 9). Can be higher. Therefore, the configuration is advantageous for the noise of the external input signal (that is, the noise margin is improved), and the possibility of the transistor malfunctioning can be eliminated. This contributes to improvement of operation reliability.

Since the gate signals of the first stage (transistors Q17 and Q18) of the buffer circuit section, as well as the circuit section receiving the input signal Si, change with the logic amplitude of Vcc to Vss, they are driven by the internal step-down voltage Vci. The gate breakdown voltage of each transistor used in the circuit section to be formed must be selected to be relatively high. In connection with this, it is preferable to increase the drain withstand voltage of each transistor used in the circuit section driven by the external power supply voltage Vcc.

FIG. 4 shows an example of the configuration of an output stage circuit of a semiconductor device to which the above-mentioned voltage step-down circuit is applied. In the illustrated output stage circuit, at least a part of the circuit has an internal step-down voltage Vci.
A data signal from an internal circuit (not shown) driven by the internal circuit is output to the outside as a data output So, a circuit section driven by the reduced internal voltage Vci, and an external power supply And a circuit section driven by the voltage Vcc.

The circuit section driven by the internal step-down voltage Vci is a CMOS inverter (p-channel transistor Q21 and n-channel transistor Q22) connected between the line of the internal step-down voltage Vci and the power supply line Vss and responding to the data signal. And an n-channel transistor Q23 whose source is connected to the output terminal of the inverter and whose gate is connected to the line of the internal step-down voltage Vci.

On the other hand, a circuit section driven by the external power supply voltage Vcc is connected between the drain of the transistor Q23 and the power supply line Vcc and has a CMOS inverter Q2 to be described later.
5, a p-channel transistor Q24 responsive to the output signal of Q26, and a CM connected between the power supply lines Vcc and Vss and responsive to a signal at the drain end of the transistor Q24.
An OS inverter (p-channel transistor Q25 and n-channel transistor Q26), also connected between power supply lines Vcc and Vss and inverters (Q25, Q25)
26) CM that generates data output So in response to the output of 26)
OS inverter (p-channel transistor Q27 and n-channel transistor Q28).

In the configuration of FIG. 4, after converting the data signal from the internal circuit to the level of the external power supply voltage Vcc using the level conversion means (transistors Q23 and Q24),
It is output to the outside as a data output So having an amplitude of Vss. Therefore, when a circuit connected to this output stage is driven by a normal power supply voltage (5 V system), good matching with elements used in the circuit can be maintained. That is, a signal of a predetermined logic level can be transmitted stably.

The data signal from the internal circuit is Vci ~
Even if the amplitude changes with the amplitude of Vss, a signal having an amplitude of Vcc to Vss is input to the gates of the transistors Q25 and Q26 by the action of the level converting means, so that both transistors do not turn on. Therefore, the inconvenience that a through current flows from the power supply line Vcc to Vss via the transistor can be solved.

As in the case of FIG. 3, the gate breakdown voltage of each transistor used in the circuit section driven by the internal step-down voltage Vci is selected to be relatively high, and is driven by the external power supply voltage Vcc. It is preferable that the drain withstand voltage of each transistor used in the circuit unit is selected to be relatively high. FIG. 5 shows a configuration of a semiconductor memory device to which the circuit of FIG. 2 is applied.

In FIG. 1, reference numeral 10 denotes a step-down circuit, which comprises a write / erase circuit for nonvolatile memory cells (see FIG. 6) included in the step-down circuit and the voltage step-down circuit of FIG. The step-down circuit 10 is provided with a normal power supply voltage Vcc and a high voltage Vcc for writing / erasing a nonvolatile memory cell.
It operates by receiving pp. Reference numeral 20 denotes a circuit section which operates by receiving an internal step-down voltage appearing at the output terminal (node N) of the step-down circuit 10, and has an address buffer, a decoder, a memory cell array, and a sense amplifier. Reference numeral 30 denotes a first-stage address buffer that receives supply of the power supply voltage Vcc and buffers address inputs, and reference numeral 40 denotes an output buffer that similarly receives the supply of the power supply voltage Vcc and sends out data output.

FIG. 6 shows an example of the configuration of a write / erase circuit for nonvolatile memory cells in the step-down circuit 10.
In the figure, the non-volatile circuit for controlling writing of the memory cell QM has a source p-channel transistor and a gate connected to the pad P ₁ is connected to the drain Q4
1, a CMOS inverter (p-channel transistor Q42 and n-channel transistor Q43) connected between the drain of the transistor and power supply line Vss and responsive to power supply voltage Vcc, and an inverter connected between power supply lines Vcc and Vss A CMOS inverter (p-channel transistor Q44 and n-channel transistor Q45) for generating a write signal WX in response to the outputs of Q42 and Q43. Similarly, the circuit for controlling the erasing of the nonvolatile memory cell QM has a source and a p-channel transistor Q46 that and gate connected to the pad P ₂ is connected to the drain, connected between the drain and the power supply line Vss of the transistor And a CMOS inverter (p-channel transistor Q47 and n-channel transistor Q48) connected between power supply lines Vcc and Vss and responsive to power supply voltage Vcc.
47 and a CMOS inverter (p-channel transistor Q49 and n-channel transistor Q50) for generating an erase signal EX in response to the outputs of Q48.

In the write / erase circuit portion of the nonvolatile memory cell QM, the drain is connected to the power supply line Vcc and the n-channel transistor Q51 responding to the write signal WX, and the drain is connected to the high voltage power supply line Vpp. And an n-channel transistor Q52 responsive to the potential of the node, and drains of transistors Q51 and Q5.
An n-channel transistor Q53 connected to each source and a gate connected to the source (node); an n-channel transistor Q54 connected between the node and the power supply line Vss and responsive to the potential of the node;
N-channel transistor Q55 connected between the output terminal of erase signal EX and the node and responsive to power supply voltage Vcc
A p-channel transistor Q56 connected between the high-voltage power supply line Vpp and the node and responding to the potential of the node; an inverter IV1 connected in the forward direction between the node and the high-voltage power supply line Vpp; A p-channel transistor Q57 connected between the nodes and responsive to the potential of the node, an inverter IV2 connected between the nodes in a forward direction, and a power supply voltage connected between the node and the output end of write signal WX An n-channel transistor Q58 responsive to Vcc; an n-channel transistor Q59 having a drain connected to the high-voltage power supply line Vpp and responsive to the potential of the node; and an n-channel transistor Q59 connected between the source and the node of the transistor and connected to the potential of the node. Responsive nonvolatile memory cell QM
And an n-channel transistor Q60 connected between the source of transistor Q59 and internal node P and responsive to power supply voltage Vcc.

The operation of the write / erase circuit shown in FIG. 6 will be described below. (1) In the case where the write signal WX is at the “L” level and the erase signal EX is at the “H” level In this case, since the transistor Q51 is off and the transistor Q58 is on, the node is at the “L” level,
Since the node goes to “H” level through inverter IV2, transistor Q52 is on. By turning on the transistor Q52, the nonvolatile memory cell QM
Is applied with the potential of the node (almost Vpp level). Further, since the node is at the "H" level, the transistor Q59 is turned on, and the level of approximately Vpp is applied to the drain of the nonvolatile memory cell QM. On the other hand, due to the “H” level of the erase signal EX, the node becomes “H” level through the transistor Q55,
Since the node goes to "L" level through inverter IV1, the source of nonvolatile memory cell transistor QM goes to "L" level. Thereby, the transistor Q
Electrons are injected into the floating gate of M to perform writing. As a result, the transistor QM is turned off, and the potential of the internal node P exhibits the “H” level. In this case, referring to the configuration of FIG.
Is supplied with an external power supply voltage Vcc.

(2) When Write Signal WX is at "H" Level and Erase Signal EX is at "L" Level In this case, the transistor Q51 is on and the transistor Q58 is off, so that the node is at "H" level. Becomes
Therefore, the node goes to "L" level, and the transistor Q59 is off. On the other hand, the "L" level of the erase signal EX
Depending on the level, the node goes to "L" level, and therefore the node goes to "H" level.
4 turns on. As a result, the node attains the "L" level, and the "L" level (almost Vss level) is applied to the control gate of the nonvolatile memory cell QM.
At this time, since the node is at the "L" level, electrons are discharged from the floating gate of the transistor QM to perform erasing. As a result, the transistor QM is turned on, and the potential of the internal node P becomes the "L" level. . In this case, referring to the configuration of FIG. 2, a reduced internal voltage Vci is output to internal voltage generating node N.

In the above configuration, the pads P ₁ , P ₂
When a voltage of power supply voltage Vcc + Vth (where Vth is a threshold level of p-channel transistors Q41 and Q46) is applied, both write signal WX and erase signal EX attain "L" level.

[0042]

As described above, according to the present invention, in a semiconductor device having a circuit for stepping down an external power supply voltage, current consumption can be reduced and an internal step-down voltage can be stably supplied. In addition, even when the external voltage and the internal step-down voltage are used together, it is possible to maintain good matching with each element including the external element, and to improve the operational reliability by eliminating the influence of noise. It becomes possible to plan.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a voltage step-down circuit in a semiconductor device of the present invention.

FIG. 2 is a circuit diagram showing another example of the voltage step-down circuit in the semiconductor device of the present invention.

FIG. 3 is a circuit diagram showing a configuration example of an input stage circuit of a semiconductor device to which the circuit of FIG. 1 or 2 is applied;

FIG. 4 is a circuit diagram showing a configuration example of an output stage circuit of a semiconductor device to which the circuit shown in FIG. 1 or 2 is applied;

FIG. 5 is a block diagram schematically showing a configuration of a semiconductor memory device to which the circuit of FIG. 2 is applied;

6 is a circuit diagram showing a configuration example of a nonvolatile memory cell write / erase circuit in the step-down circuit of FIG. 5;

FIG. 7 is a circuit diagram illustrating an example of a voltage step-down circuit in a conventional semiconductor device.

FIG. 8 is an operation characteristic diagram of the circuit of FIG. 7;

FIG. 9 is a circuit diagram showing an example of an address input circuit in a conventional semiconductor device.

FIG. 10 is a circuit diagram showing an example of a data output circuit in a conventional semiconductor device.

FIG. 11 is a circuit diagram showing another example of a data output circuit in a conventional semiconductor device.

[Explanation of symbols]

C: Smoothing capacitor N: Internal voltage generation node Q: Depletion type n-channel transistor QM: Non-volatile memory cell Q1-Q5: Circuit for determining gate potential of transistor Q Q11-Q20: Input stage circuit of semiconductor device Q21- Q28: output stage circuit of semiconductor device Si: input signal So: data output Vci: step-down voltage (internal voltage) Vcc: high-potential power supply line (external voltage) Vss: low-potential power supply line (reference voltage)

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G11C 16/00-16/34 G11C 11/34 G05F 1/00-1/10

Claims (4)

(57) [Claims] A first power supply voltage and a second power supply supplied from outside;
Voltage is supplied, the drain is connected to the first power supply voltage, and the
Depletion type with the voltage connected to the internal voltage generation node
Transistor, nonvolatile storage element, and nonvolatile storage
Depending on the content of the element,
The first power supply voltage or the second power supply voltage is imprinted on a gate.
And a gate for the depletion type transistor.
When the power supply voltage is applied, the internal voltage generation node
Output the first power supply voltage from the depletion type
The second power supply voltage is applied to the gate of the transistor
In the case, the first power supply voltage is supplied from the internal voltage generation node.
A predetermined voltage between the first power supply voltage and the second power supply voltage is output . 2. The method according to claim 1, wherein at least a part of the circuit includes the internal voltage generator.
An input stage circuit for transmitting an input signal to an internal circuit driven by the voltage of the raw node , wherein the input stage circuit is driven by the first power supply voltage and directly receives the input signal to change its level. And a circuit for transmitting the level-stabilized signal driven by the voltage of the internal voltage generation node to the internal circuit. The semiconductor device according to claim 1. 3. The circuit according to claim 1 , wherein at least a first stage of the circuit section driven by the voltage of the internal voltage generation node is formed of a transistor having a relatively high gate withstand voltage.
The semiconductor device according to claim 2, characterized in that the drain breakdown voltage the circuit section which is driven by pressure is constituted by relatively high transistor. 4. At least a part of the circuit is configured to generate the internal voltage.
An output stage circuit for outputting a data signal from an internal circuit driven by the voltage of the raw node to the outside as a data output, wherein the output stage circuit is configured by the voltage of the internal voltage generation node and the first power supply voltage A circuit section that is driven and converts the voltage level of the data signal to the level of the power supply voltage;
2. The semiconductor device according to claim 1, further comprising: a circuit unit driven by the first power supply voltage and outputting the level-converted signal as the data output. 3.