JP3221475B2 - Video signal processing method and its processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus suitable for a video camera or a special effect device mounted on a monitor.

[0002]

2. Description of the Related Art For example, in a VTR-integrated video camera, if the display surface of a monitor mounted on the video camera is directed toward a subject, the photographed content can be viewed from the subject side. So-called face-to-face shooting can be performed.

[0003]

However, when the direction of the monitor is changed in order to perform this face-to-face photographing, there is no problem if the monitor can be rotated by 180 ° about the vertical axis. However, due to the structure of the camera. However, when the display image can only be rotated by 180 ° about the horizontal axis, the displayed image is inverted vertically and horizontally.

Therefore, in such a case, it is necessary to perform signal processing on the video signal supplied to the monitor so that the displayed image is inverted up and down and left and right.

[0005] Further, in an editing apparatus or the like, it may be necessary to invert the image vertically or horizontally as a special effect.

[0006] Then, for the video signal,
To flip the image up and down (or left and right), use 2
Two field memories (or line memories) are prepared, and video signals are alternately written into these field memories for one field period (or one line), and the video signals are read from the unwritten field memories. What should I do?

However, this method requires two field memories, which increases the cost.

The present invention solves such a problem and considers processing particularly in a vertical blanking period.

[0009]

For this reason, in the present invention, if the reference numerals of the respective parts correspond to the embodiments described later, a memory 1 having a capacity for a predetermined period,
A write address controller 2 for giving a write address when writing a video signal to the memory 1; and a read address controller 3 for giving a read address when reading a video signal from the memory 1 to the memory 1. The data is written continuously to the memory 1 and the direction of change of the write address at the time of this writing is reversed every predetermined period, and the video signal written to the memory 1 is read during the period of the writing. In the scanning period of the next cycle, the writing is performed before the writing performed in the scanning period, and the direction of change of the read address at the time of reading is made equal to the direction of change of the write address.

[0010]

Since the address change direction when writing a video signal to the memory 1 and the address direction when reading it out are reversed, a video signal of an inverted image is taken out. Then, at this time, since reading is performed immediately before writing, the inversion processing is realized with one memory 1.

[0011]

In the following example, it is assumed that a video signal to be processed is a signal of the NTSC system. For the sake of simplicity, for example, as shown in FIG. 2A, it is assumed that the period TBLK of the first 12.5 lines in one field period is a vertical blanking period, and the period TSCN of the subsequent 250 lines is a vertical scanning period.

In FIG. 1, reference numeral 1 denotes a field memory. In this example, the field memory 1 has a capacity slightly larger than one field of a video signal to be inverted, for example, a capacity of 305 lines. Having. The field memory 1 has an input port PIN for writing and an output port POUT for reading, and is capable of independently specifying a write address and a read address.

The video signal to be inverted is
For example, one sample is an 8-bit parallel digital signal, and this signal is the input port P of the field memory 1.
A video signal supplied to IN and subjected to inversion processing is taken out from an output port POUT.

Reference numeral 2 denotes an address controller for a write address (line address). Reference numeral 3 denotes an address controller for a read address (line address). In these address controllers 2, 3, the write address signal WADS and the read address signal RA are used.
DS is formed, and these address signals WADS and RADS are supplied to the field memory 1.

In this case, each of the address controllers 2 and 3 has a line counter (not shown). By controlling the count direction to up-count or down-count, the address signal WAD is adjusted.
The line addresses indicated by S and RADS can be changed in an increasing direction or a decreasing direction.

Reference numeral 4 denotes a microcomputer;
The microcomputer 4 controls the system of the apparatus provided with the image processing circuit, and also controls the address signal WAD output from the address controllers 2 and 3.
The initial values of S and RADS (start addresses for each field period) are output. Since the initial value is different between the odd field period and the even field period as described later, the initial value is supplied to the address controllers 2 and 3 through the switch circuits 5 and 6.

Further, for example, as shown in FIG. 2B, a pulse WVD of a field cycle which rises every time the vertical blanking period TBLK starts is supplied to the toggle circuit 7,
As shown in FIG. 2D, a signal WVALT that is inverted every field period is formed. And this signal WVALT is
The control signal is supplied to the switch circuit 5 as a control signal, and is also supplied to the address controller 2 as a control signal for increasing / decreasing the address signal WADS. When WVALT = “H”, the increasing direction, and when WVALT = “L”, the decreasing direction. Is done.

The pulse WVD is supplied to the delay circuit 8, and as shown in FIG. 2C, the pulse WVD is delayed by a period slightly shorter than one field period, and
A pulse RVD having a field cycle located immediately before VD is supplied to the toggle circuit 9, and the pulse RVD is supplied to the toggle circuit 9 in FIG.
As shown in the figure, a signal R inverted every one field period
VALT is formed. The signal RVALT is supplied to the switch circuit 6 as a control signal thereof, and is also supplied to the address controller 3 as a control signal for increasing / decreasing the address signal RADS. When RVALT = “L”, the increasing direction, WVALT = “ In the case of H ", the direction is decreasing.

The writing and reading to and from the field memory 1 and their addresses are controlled as described below, and the image displayed by the video signal output from the field memory 1 is inverted upside down.

[Vertical Inversion Mode] This is a case where a video signal is processed so that an image is inverted upside down. In this case, the write address and the read address of the field memory 1 are controlled as shown by the solid and broken lines in FIG. 2A.

That is, first, in writing, during the (N + 1) -th field period T (N + 1), the solid line W (N +
As shown in 1), the write address is incremented by one line every one horizontal period from address 0, for example, and a video signal is written to that address by one line.

In the (N + 2) -th field period T (N + 2), as shown by a solid line W (N + 2), the write address is set at the end of the field period T (N + 1). The address is reduced by one line every one horizontal period, and a video signal is written to the address by one line.

Then, similarly, the write address is controlled so as to repeatedly increase and decrease every one field period, and the write address includes
Video signals are written one line at a time.

On the other hand, for reading, the (N + 1) th
In the vertical scanning period TSCN of the field period T (N + 1),
As indicated by the broken line R (N), the read address is increased by one line every one horizontal period, and the video signal is read from the address by one line.

Next, in the vertical scanning period TSCN of the (N + 2) -th field period T (N + 2), as shown by a broken line R (N + 1), the read address is changed by one line every one horizontal period. The video signal is read from the address one line at a time.

In the same manner, the read address is controlled so as to repeatedly increase and decrease every one field period in the same direction as the write address, and the video signal is read one line at a time from the read address. Will be done.

In this manner, the writing of the video signal to the field memory 1 is performed continuously, and the reading is performed continuously for the next vertical scanning period TSCN, so that valid video signals can be continuously obtained. You can do it.

In this case, the field period T (N +
In (1), a video signal is written in the direction in which the write address increases, and in the next field period T (N + 2), the period T (N +
Since the video signal written in 1) is read in the direction in which the read address decreases, the field period T (N +
When an image is displayed by the video signal read in 2), the image is upside down.

Similarly, in the field period T (N + 2), the video signal is written in the direction of decreasing the write address, and in the next field period T (N + 3), the video signal is written in the period T (N + 2). Since the video signal is read in the direction in which the read address increases, when an image is displayed by the video signal read in the field period T (N + 3), the image is turned upside down. Become.

In the subsequent field period, the processing of the periods T (N + 1) and T (N + 2) is repeated. What is the direction of address increase / decrease?
It has been reversed. Therefore, when an image is displayed by the read video signal, the image is upside down, that is, the video signal of the image displayed upside down is output from the field memory 1. Will be.

Here, the write address and the read address in FIG. 2A are considered as follows.

That is, first, which field period T
Even in (n) (n is an arbitrary field number), it is necessary to read the video signal of the immediately preceding field period T (n-1) before writing the video signal in that field period T (n). Therefore, in any field period T (n), the broken line indicating the read address must be located on the faster time side, that is, on the left side in the figure, than the solid line indicating the write address.

Since reading and writing cannot be performed simultaneously with respect to the same address in the field memory 1, it is necessary to perform reading at least one horizontal period faster than writing.

However, if reading in one field period T (n) is performed at a time much earlier than writing, vertical synchronization between the video signal input to the field memory 1 and the output video signal occurs. Becomes larger and the reading is performed in the vertical blanking period TBL.
It is not preferable because it greatly enters K.

Therefore, the time between reading and writing to the same address, that is, the time difference between the pulse WVD and the signal RVALT and the time between the pulse RVD and the signal RVALT,
It is about 1.5 horizontal periods.

Second, the change range of the read address in the field period T (n + 1) is the field period T (n).
In the vertical scanning period TSCN.

Therefore, when the write address change range W (N + 1) in the field period T (N + 1) is shifted to the lower address side from the position in the figure (the solid line is moved downward in parallel), The first address in the scanning period TSCN must not be smaller than the lower limit of the address of the field memory 1. Further, when the write address change range W (N + 2) in the field period T (N + 2) is shifted to the upper address side from the position shown in the figure (the solid line is moved upward in parallel), the vertical scanning period TSCN The first address must not exceed the upper limit of the field memory 1 address.

As described above, the initial values of the write address and the read address for the field memory 1 (start address for each field period) are set as follows.

WADS (n): Write start address of memory 1 RADS (n): Read start address of memory 1 VMAX: Number of video signal lines to be written to memory 1 VBLK: Vertical blanking of video signal to be written to memory 1 When the number of lines in the period TBLK is set, the write start address WADS (n) in the field period T (n) is as follows when WVALT = “H”: WADS (n) = WADS (n−1) − (VMAX + VBLK) WVALT = When "L", WADS (n) = WADS (n-1) + (VMAX + VBLK).

The read start address RADS (n) in the field period T (n) is as follows: RVALT = “H”, RADS (n) = WADS (n) + VMAX RVALT = “L”, RADS (n) = WADS (n) -VMAX.

The start addresses WADS (n), RAD
S (n) is output from the microcomputer 4 as the above-described initial value, and is loaded into the memory 1 through the switch circuits 5 and 6.

Thus, according to the image processing circuit of FIG.
By controlling writing and reading to and from the field memory 1, a video signal of an image displayed upside down can be obtained with only one field memory 1.

Further, as is clear from FIG. 2, writing and reading are performed to and from the field memory 1 for all the fields of the original video signal, and since the solid line and the broken line do not intersect, that is, the field memory 1 Since writing and reading are not performed simultaneously with respect to the same address, even if the target video signal is a video signal of a moving image, the vertical inversion processing can be performed without causing a field loss. .

[Enlarged Vertical Inversion Mode] This is a case where a video signal is processed such that a part of an image is vertically enlarged and the enlarged portion is vertically inverted.
In this case, the write address and the read address of the field memory 1 are controlled as shown by the solid line and the broken line in FIG. 3A.

FIG. 3 shows a case where the central portion of the original image is doubled vertically. In addition, the enlargement method is based on the assumption that the write address has a change speed (1
This is realized by setting the change speed of the read address to の of the change speed of the write address.

That is, first, in writing, during the (N + 1) -th field period T (N + 1), the solid line W (N +
As shown in 1), the write address is incremented by one line every one horizontal period from address 0, for example, and a video signal is written to that address by one line.

In the (N + 2) -th field period T (N + 2), as shown by the solid line W (N + 2), the write address is shifted by one line every one horizontal period from the predetermined start address. And the video signal is written to that address one line at a time. In FIG. 3A, during the vertical blanking period TBLK, since the write address exceeds the maximum value of the line address of the memory 1, the write address is as shown by a solid line W (N + 2) ". Is reflected in the lower address.

Then, similarly, the write address is controlled so as to repeat increase and decrease every one field period, and the write address includes
Video signals are written one line at a time.

On the other hand, for reading, the (N + 1) th
In the vertical scanning period TSCN of the field period T (N + 1),
As indicated by the broken line R (N), the read address is increased by one line every two horizontal periods, and the video signal is read from the address by one line every one horizontal period. In this case, since the central portion of the original image is enlarged, the change range of the read address is as follows.
It looks like the figure.

Next, in the vertical scanning period TSCN of the (N + 2) -th field period T (N + 2), as shown by the broken line R (N + 1), the read address is changed by one line every two horizontal periods. The video signal is read from the address one line at a time in one horizontal period.

Then, similarly, the read address is controlled so as to repeatedly increase and decrease every two field periods in the same direction as the write address, and the video signal is read one line at a time from the read address. Will be done.

Therefore, from the field memory 1,
An image in which the center of the original image is enlarged twice,
The video signal of the image displayed upside down is output.

Also in this case, the field memory 1
Are the same as in the case of [vertical inversion mode]. Therefore, the initial value of the write address (the initial value for each field period) is set as follows.

That is, MMAX: maximum number of lines in memory 1 (maximum value of line address) MEMS: start line position of enlargement processing MVSIZE: effective number of lines of video signal = VMAX-VBLK ΔY: enlargement ratio WVALT = When “H” WADS (n + 1) = WADS (n) − {VMAX + VBLK + MVSIZE− (MEMS + MVSIZE × ΔY)} = WADS (n) −2 · VMAX + (MEMS + MVSIZE × ΔY) When WVALT = “L” WADS (n +1) = WADS (n) + {VMAX + VBLK + MVSIZE− (MEMS + MVSIZE × ΔY)} = WADS (n) + 2 · VMAX− (MEMS + MVSIZE × ΔY)

In this way, by controlling writing and reading to and from the field memory 1, a part is expanded by only one field memory 1, and
A video signal of an image displayed upside down can be obtained.

[Reduced Up / Down Inverting Mode] This is a case where a video signal is processed so that an image is reduced in the vertical direction and the reduced portion is inverted upside down. In this case, the write address and the read address of the field memory 1 are controlled as shown by the solid line and the broken line in FIG. 4A.

FIG. 4 shows that the original image is
/ 2 and the reduced image is displayed at the center of the screen. In addition, the reduction method is such that the write address is changed to half of the normal speed, the video signal is thinned out at a rate of one line for every two lines and written to the memory 1, and the change speed of the read address is changed to the normal change speed. Is realized by making it equal to

That is, first, in the writing, during the vertical scanning period TSCN of the (N + 1) -th field period T (N + 1), as shown by the solid line W (N + 1), the writing address is two horizontal addresses. The video signal is incremented by one line every period, and the video signal is written to the address by thinning out one line every two horizontal periods.

In the vertical scanning period TSCN of the (N + 2) -th field period T (N + 2), as shown by the solid line W (N + 2), the write address corresponds to one line every two horizontal periods. And the video signal is written to the address by thinning out one line every two horizontal periods.

Incidentally, which field period T (N + 1),
Also at T (N + 2), during the vertical blanking period TBLK,
The write address is increased or decreased by one line every one horizontal period, as in the normal case.

Then, similarly, the write address is controlled so as to repeat increase and decrease every one field period, and the write address includes
The video signal is decimated to 1/2 and written.

On the other hand, for reading, the (N + 1) th
In the central period TDSP of the vertical scanning period TSCN of the field period T (N + 1), the read address is increased by one line every one horizontal period, as shown by a broken line R (N). The video signal is read out from the address one line at a time.

Next, the center period TDSP of the vertical scanning period TSCN of the (N + 2) th field period T (N + 2)
The read address is 1 as shown by a broken line R (N + 1).
In each horizontal period, the video signal is reduced by one line and the video signal is read from the address by one line.

Then, similarly, the read address is controlled so as to increase and decrease in the same direction as the write address every one field period, and the video signal is read one line at a time from the read address. Will be done.

Therefore, from the field memory 1,
The original image is reduced to half and displayed at the center of the screen, and the video signal of the image displayed upside down is output.

Also in this case, the field memory 1
Are the same as in the case of [vertical inversion mode]. Therefore, the initial value of the write address (the initial value for each field period) is set as follows.

That is, when WVALT = “H”, WADS (n + 1) ≧ 0 WADS (n + 1) ≦ WADS (n) − (VBLK + MVSIZE × ΔY + VBLK + MVSIZE × ΔY) = WADS (n) −2 (VBLK + MVSIZE × ΔY When WVALT = “L” WADS (n + 1) ≦ MMAX WADS (n + 1) ≧ WADS (n) + (VBLK + MVSIZE × ΔY + VBLK + MVSIZE × ΔY) = WADS (n) +2 (VBLK + MVSIZE × ΔY)

In this way, by controlling writing and reading to and from the field memory 1, the whole is reduced by only one field memory 1, and
A video signal of an image displayed upside down can be obtained.

[Upside down mode with freeze mode]
This is a case in which the above-described "vertical inversion mode" is shifted to the "freeze mode" and then returns to the "vertical inversion mode" again. In this case, the microcomputer 4 executes, for example, a processing routine 10 shown in FIG. 5, and controls the write address and the read address of the field memory 1 as shown by a solid line and a broken line in FIG. 6A.

That is, although the upside down mode is processed as described above, in the state where this processing is performed, the pulse W
It is checked whether VD can be obtained, and if not, step 11 is repeated.

Then, when the pulse WVD is obtained, the process proceeds from step 11 to step 12, and this step 1
In step 2, it is checked whether the freeze switch has been pressed. If not, the process returns to step 11.

Therefore, when the freeze switch is not operated, the upside down mode is continued.

However, if the freeze switch is operated at an arbitrary time point t0 in the period in which the upside down mode is continued, the time point t1 of the first pulse WVD after the time point t0.
Then, the processing of the microcomputer 4 proceeds from step 11 to step 13 through step 12.

Then, in this step 13, writing of the video signal to the field memory 1 is prohibited. Also, the write address increase / decrease direction during the field period T (N + 1) including the time point t1, that is, the signal W
The VALT level is stored in the microcomputer 4.

Further, the field period after the time point t1 is set so that the read address increase / decrease direction is the same as the field period T (N + 1) including the time point t1. In the case of FIG. 6, since the read address (shown by a broken line) changes in the decreasing direction in the field period T (N + 1), in the subsequent field periods, the reading address changes in the decreasing direction in any field period. Is set to change to

Therefore, a video signal of a still image whose upside down is inverted from the time t1 is output from the field memory 1, that is, the up / down inverted freeze mode is set.

Then, the processing of the microcomputer 4 proceeds to step 21 following step 13, in which it is checked whether or not a pulse WVD is obtained. If not, step 21 is repeated.

Then, when the pulse WVD is obtained, the process proceeds from step 21 to step 22, and this step 2
In step 2, it is checked whether the freeze release switch has been operated. If not, the process returns to step 21. Therefore, the freeze mode of upside down is continued until the freeze release switch is operated.

However, if the freeze release switch is operated at an arbitrary time point t2 in the upside-down inversion freeze mode, when the time point t3 at which the pulse WVD is first obtained after the time point t2 is reached, the processing starts from step 21. Proceed to step 23 through step 22. In this step 23, it is determined whether the level of the signal WVALT in the field period including the time point t3, in the case of FIG. 6, is equal to the level of the signal WVALT stored in the step 13 in the field period T (N + 4). Is checked.

In the case of FIG. 6, since the two are not equal, the process returns to step 21 and the freeze mode is continued until the first pulse WVD after the time t3, and the time t
When the number reaches 4, the process proceeds from step 21 to step 23 again from step 21 to step 23 (because it is usual that the freeze release switch is still pressed).

The field period T including the time point t4
In (N + 5), since the level of the signal WVALT is equal to the signal WVALT stored in step 13, the processing is performed in step 23.
Proceeds to step 24, and in this step 24,
Writing of the video signal to the field memory 1 is permitted. Therefore, thereafter, the state of the video signal of the moving image subjected to the upside down process is restarted.

In FIG. 6, when the writing of the video signal to the field memory 1 is permitted from the time point t3, the write address (shown by a dashed line) and the read address cross each other. Until the next time point t4, the freeze mode is continued.

In this way, in this example, the upside down freeze mode can be executed during the upside down mode.

[Reduced Up / Down Inverting Mode with Reduced Freeze Mode] This is a case in which the mode shifts from [Reduced Up / Down Inverting Mode] to [Reduced Freezing Mode] and then returns to [Reduced Up / Down Inverting Mode]. In this case, for example, the processing routine 30 shown in FIG. 7 is executed by the microcomputer 4, and the write address and the read address of the field memory 1 are controlled as shown by a solid line and a broken line in FIG. 8A.

That is, while the reduced upside down mode is processed as described above, in a state where this processing is being performed, it is checked in step 31 of the routine 30 whether or not the pulse WVD is obtained. If not, step 31 is repeated.

When the pulse WVD is obtained, the process proceeds from step 31 to step 32, where
In step 2, it is checked whether the freeze switch has been pressed. If not, the process returns to step 31.

Therefore, when the freeze switch is not operated, the reduced upside down mode is continued.

However, if the freeze switch is operated at an arbitrary time point t0 during the period in which the upside-down mode is continued, the time point t1 of the first pulse WVD after the time point t0.
Then, the process of the microcomputer 4 proceeds from step 31 to step 33 through step 32.

In this step 33, the change of the write address is set so as to change by one line every one horizontal period. In the case of FIG. 6A, WVALT
= "L", so that it is set to decrease by one line every one horizontal period.

Subsequently, the processing of the microcomputer 4 proceeds to step 34, in which it is checked whether or not a pulse WVD is obtained. If not, step 34 is repeated.

Then, at time t2, which is one field period after time t1, a pulse WVD is obtained. Then, the process proceeds from step 34 to step 35, where the video signal of the video signal Writing is prohibited. Further, the read address is set so as to change by one line every two horizontal periods, and thereafter, is set so as to change in the same direction in any field period. Further, the microcomputer 4 stores the direction in which the read address is increased or decreased in the field period T (N + 2) including the time point t2, that is, the level of the signal WVALT.

Accordingly, a video signal of a still image that has been reduced from time t1 and inverted upside down is output from the field memory 1, that is,
The reduced upside down freeze mode is set.

Then, the processing of the microcomputer 4 proceeds to step 41 following step 35. In this step 41, it is checked whether or not the pulse WVD is obtained. If not, step 41 is repeated.

When the pulse WVD is obtained, the process proceeds from step 41 to step 42, where step 4
At 2, it is checked whether or not the freeze release switch has been operated. If not, the process returns to step 41. Therefore, the reduced upside down freeze is continued until the freeze release switch is operated.

However, if the freeze release switch is operated at an arbitrary time point t3 in the reduced vertical inversion freeze mode, a time point t4 at which the pulse WVD is first obtained after the time point t3.
, The process proceeds from step 41 to step 43 through step 42. And this step 43
Is checked whether the level of the signal WVALT in the field period T (N + 4) including the time point t3 is equal to the signal WVALT stored in the step 35.

In the case of FIG. 8, since the two are not equal, the process proceeds from step 43 to step 45,
In this step 45, writing and reading to and from the field memory 1 are performed in the same manner as before time t1. Therefore, thereafter, the state of the video signal of the moving image subjected to the reduced and upside down processing is restarted.

In step 43, both signals WVA
When the levels of LT and WVALT are equal, the process proceeds from step 43 to step 44. In this step 44, the pulse WVD is checked to wait for one field period.
Go to 5.

In this case, the write start addresses WADS (N) and WADS (N + 4) at times t1 and t4 are as follows. That is, as shown in FIG. 8, if M1 = MVSIZE × ΔY M2 = VBLK + MVS M3 = VBLK M4 = MVS × ΔY, then WADS (N) = WADS (N-1) + VBLK + M1 + M2 = WADS (N-1) + VBLK + MVSIZE × ΔY + VBLK + MVS = WADS (N−1) + 2 · VBLK + MVSIZE × ΔY + MVS WADS (N + 4) = WADS (N) −M3 + VBLK + M4 = WADS (N) −VBLK + VBLK + MVS × ΔY = WADS (N) + MVS × ΔY

Thus, in this example, the reduced upside down freeze mode can be executed during the reduced upside down mode.

[Left-Right Inversion Mode] In this case, a line memory is used instead of the field memory 1, the signals WVD, RVD, WVALT, and RVALT of the vertical cycle are used as signals of the horizontal cycle, and the signal of the horizontal cycle is used as a pixel unit. Signal. That is, in this way, inversion, enlargement, reduction, and freeze can be performed in the horizontal direction.
At that time, instead of the line memory, if the horizontal address of the field memory 1 is controlled in the same manner as the line memory, the line memory can be omitted.

Further, in the above, if the writing of the video signal in the vertical blanking period TBL is prohibited,
The line address amount of the field memory 1 can be set to the number of lines MVSIZE in the vertical scanning period TSCN.

[0102]

According to the present invention, a video signal of an image displayed upside down can be obtained with only one field memory 1.

In addition, writing and reading to and from the field memory 1 are performed for all fields of the original video signal, and writing and reading to the same address in the field memory 1 do not occur at the same time. Even if the target video signal is a video signal of a moving image, it is possible to perform the upside-down inversion processing without causing a field loss.
In addition, freeze, enlargement, or reduction can be performed simultaneously with inversion.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an example of the present invention.

FIG. 2 is a timing chart for explaining a first operation.

FIG. 3 is a timing chart for explaining a second operation.

FIG. 4 is a timing chart for explaining a third operation.

FIG. 5 is a flowchart for explaining a fourth operation;

FIG. 6 is a timing chart for explaining a fourth operation;

FIG. 7 is a flowchart for explaining a fifth operation;

FIG. 8 is a timing chart for explaining a fifth operation;

[Explanation of symbols]

 1 field memory 2 address controller (for write address) 3 address controller (for read address) 4 microcomputer 7 toggle circuit 8 delay circuit 9 toggle circuit 10 processing routine (for freeze) 20 processing routine (for reduction freeze)

Claims (5)

(57) [Claims] A video signal is continuously written in a memory, and a change direction of a write address at the time of this writing is set to a reverse direction every field period or horizontal period. In the scanning period, the video signal written in the preceding field period or the scanning period of the horizontal period is read out by changing the video signal in a direction opposite to the address change direction at the time of writing. Signal processing method. 2. A memory having a capacity corresponding to a predetermined period, a write address controller for providing a write address for writing a video signal to the memory to the memory, and a read address for reading the video signal from the memory. A read address controller that gives the video signal to the memory, and continuously writes the video signal to the memory, and changes the write address change direction at the time of this write in the reverse direction at every predetermined cycle. Reading of the video signal written in the memory is performed in a scanning period in a period next to the period in which the writing is performed and before writing performed in the scanning period. The change direction of the read address is determined by the write address. Processing circuit changes direction and equal way video signals. 3. The video signal processing circuit according to claim 2, wherein the period is a field period, and the capacity of the memory is at least one field. 4. The video signal processing circuit according to claim 2 or 3, wherein, when the video signal is frozen, the writing is stopped, and the video signal of a period immediately before the writing is stopped is output.
A video signal processing circuit configured to repeatedly read a read address that changes in the direction opposite to the change direction of the write address in the immediately preceding period. 5. The video signal processing circuit according to claim 2, wherein the cycle is a horizontal cycle, and the capacity of the memory is at least one line. .