JP3220215B2 - Photoelectric negation logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric negation logic circuit.

[0002]

2. Description of the Related Art The operation speed of a current all-electronic computer is mainly limited by a wiring delay time.
In order to overcome this limitation and dramatically increase the calculation speed, optical computers using optical technology are being actively developed. According to this, it is possible to reduce the wiring delay time by taking advantage of the non-inductive property of light by the optical fiber wiring, and at the same time, by utilizing the spatial parallelism of light and using the optical signal itself for logical operation, ultra-high speed It is also possible to realize an arithmetic processing device. In particular, the latter can be applied to an ultra-high-speed (real-time) image processing device or the like, and its importance is great. On the other hand, the greatest weakness of light in this case is that it does not have a negative signal unlike electricity. for that reason,
Negative logic using optical signals is difficult to express negatively, and may complicate the entire system.

[0005] Normally, a periodic pulse signal is output, and this is erased by inputting an optical pulse signal, thereby equivalently performing a NOT logic. This is already known, and a specific example is described in Japanese Patent Application Laid-Open No. 2-256319, which was previously filed by the present inventors. This circuit is shown in FIG.

[0004] This rectifying junction is connected in the opposite direction, substantially two consists semiconductor photodetector 41 _1, 41 ₂ having an electrode structure symmetrical to one electrode terminal of each light-receiving element The bias voltages having opposite polarities are connected to the power supply 412.
₁ , 412 _2, and the other terminal of each light receiving element is connected to the output terminal 43 in common. According to this, one of the light receiving element 41 ₁ are given continuous light also continuous pulse A, the optical pulse signal B is input to the other light receiving element 41 _2, the light receiving elements 41 _1, 41 ₂
The electric signal generated at the electrode terminal of
, A NOT logic is performed.

[0005] The semiconductor light receiving elements 41 ₁ ,
For 41 _2, when the Schottky junction rectifying junction is generally MSM (metal - semiconductor - metal) it becomes what is called a photo detector is capable over several GH _Z Ultrafast response operation, In addition, since the structure is simple and the compatibility with a field-effect transistor (FET) in a manufacturing process is good, it has a feature that it is suitable for integration.

In general, a comb-shaped structure is used in order to form the light receiving portion on a side having a size of several tens to several hundreds of micrometers while keeping the electrode interval at several micrometers. In the prior art, the left-right symmetry, which is another characteristic of this light receiving element, plays a significant role in implementation, while the light receiving element is a rectifying junction, but has a large photovoltaic current. Depends on the magnitude of the bias voltage.

[0007]

In the circuit of the prior art, as shown in FIG. 4, a separate bias voltage source is required for each light receiving element. Therefore, there is a problem that the actual circuit itself becomes large-scale. However, this is not a major problem in itself. However, separately from this, as described above, the magnitude of the photovoltaic current depends on the magnitude of the bias voltage in this light-receiving element. The absolute value of the size had to be set equal.

For this reason, when actually constructing a circuit, it is necessary to precisely set each bias voltage source, and the stability of the power supply directly affects the stability of the operation of the logic circuit. However, there is a problem that the power supply is very susceptible to noise such as ripples generated from a power supply. An object of the present invention is to solve such a problem.

[0009]

SUMMARY OF THE INVENTION A photoelectric NOT logic circuit according to the present invention has a pair of substantially symmetrical Schottky electrodes formed in proximity to each other on a semiconductor to form a planar structure. A first and a second light receiving element each having one terminal commonly connected, a first load element having one end connected to the other terminal of the first light receiving element and the other end grounded; A second load element, one end of which is connected to the common connection point and the other end of which is supplied with a predetermined bias voltage, wherein the other terminal of the first light receiving element is a signal output terminal; The other terminal of the element is grounded, and a first periodic light pulse is incident on the first light receiving element, and a corresponding periodic electric pulse signal is output from the signal output terminal, The second light pulse enters the second light receiving element. Is periodically electrical pulse signal is erased by, characterized in that this negative negative electrical output signal to the second optical pulse by has to be obtained.

Here, the semiconductor is GaAs, InP, I
It is an nGaAs or InGaAsP substrate, and it is possible to integrate the light emitting element for generating the first and second light pulses, the light emitting element and the load element described above, on this substrate.

[0011]

According to the structure of the present invention, as a NOT logic circuit which operates in response to input of an optical signal, a light receiving element substantially the same as the photoelectric conversion element used in the circuit of FIG. A proposal of a novel circuit in which a Schottky junction is formed with a gap of several μm and uses two light receiving elements having a substantially symmetrical planar structure and operates with only one bias voltage source. It is. here,
The response speed of the circuit is the same as that of the conventional circuit (FIG. 4), and an ultra-high speed operation is possible.

[0012]

FIG. 1 shows an embodiment of a photoelectric NOT logic circuit according to the present invention. The two MSM1 _1, 1 ₂ is electrically connected at one end, the DC power source 12 is connected through a load resistor 2 ₂ suitably sized, have a common bias voltage is applied to each. One of MSM1 ₁ of the other end side and the output terminal 3, the terminal 3 through a load resistor 2 ₁ of suitable size, and is grounded other MSM1 ₂ at the other end.

[0013] MSM1 If no input of the optical pulse signal is the _2, when the polarity of the bias voltage applied from the power source 12 and positive, the semiconductor light emitting element 11 ₁ to MSM1 _1, corresponding to the clock cycle light pulses ( When A) is incident, the output terminal 3 outputs a positive periodic electric pulse signal from the MSM ₁₁ .

When an optical pulse signal (B) is input from the semiconductor light emitting element 11 ₂ to the MSM ₁₂ , the circuit on the MSM ₁₂ side having no load resistance short-circuits the circuit on the other MSM ₁₁ side. (Power supply 1 for bias voltage
2 because current is unilaterally flowing MSM1 ₂ side from), the voltage is zero at the output terminal 3. Thus, a photoelectric negation logic circuit that operates by inputting an optical signal can be realized.

[0015] In this case, the load resistor 2 ₁ MSM1 ₁
The purpose is to convert the current signal output from the IC into a voltage signal. Since the obtained voltage amplitude and response speed are in a trade-off relationship, it is necessary to determine the magnitude according to the desired circuit characteristics. . However, MSM1 _{1, 1
2} is a planar structure, so the capacitance between terminals is very small,
Even if a relatively large light receiving portion having a side of 0.2 mm is formed, it is about 0.5 pF.

[0016] This is the main factor that enables the MSM to operate at a very high speed. Thus, the magnitude of the load resistor 2 _1, and slightly than normal 50Ω enhanced, it is also possible to make the voltage amplitude correspondingly. This can also be said to be one characteristic of a case where a logic circuit is formed using MSM. The size of the load resistor 2 ₂ is related to the response characteristic of predominantly MSM1 ₂ side, no problem as the same size as the load resistor 2 _1.

The semiconductor light emitting device 1 used here
11 ₁ and 11 ₂ indicate that the active layer has GaAlAs (0.85 μm band) or InGa according to the wavelength of light to be output.
An LED (light emitting diode) using As (P) (1.3 to 1.55 μm band) or a semiconductor laser. The current pulse source 13 provides a periodic current pulses corresponding to the clock to the semiconductor light emitting element 11 _1.

As described above, a photoelectric negation logic circuit that operates by inputting an optical signal can be realized. Since the MSM as the semiconductor light receiving element used here is formed by a Schottky rectifying junction, a high-speed response is possible as compared with a photoconductive light receiving element formed by ohmic contact, and Since the dark current can be reduced, the dynamic range can be increased accordingly.

Further, as can be seen from the above description,
Since the input gate of this circuit has only one stage as in the circuit shown in the prior art, the operating speed is determined only by the response speed of the MSM terminated with a load resistor. Can be. In particular,
It is possible response of a few to several 10GH _Z.

The semiconductor substrate used for the semiconductor light receiving element is made of Si or G for short wavelength light in the 0.85 μm band.
Ge or InGaAs (P) is used for long-wavelength light having aAs of 1.3 to 1.55 μ band. Of these, as described below, when circuits are integrated on the same semiconductor substrate, Si, GaAs, or InGaAs is used.
(P) is preferable, and particularly when integrated with a semiconductor light emitting element, GaAs or InGaAs is preferable.
(P) is suitable.

Next, FIG. 2 shows an embodiment in which the above-described photoelectric NOT logic circuit is integrated on the same semiconductor substrate. Since the photoelectric negation logic circuit according to the present invention has a very simple configuration and a high degree of freedom, it is very suitable for arranging and integrating light receiving elements at high density.

Here, as the semiconductor substrate 8 of the integrated circuit, Si, GaAs or InP can be used. However, GaAs and InP can be easily separated from each other and can reduce the stray capacitance associated with the wiring. Insulating substrates have been put to practical use and are most suitable as substrates used here.

[0023] MSM1 _1, 1 ₂ is, n-type Si and n-type or directly on a semi-insulating GaAs substrate 8, or on the active layer 9 ₁ anew crystal grown n-type thereon, vacuum depositing a metal thin film It is formed by doing. Semiconductor substrate 8
In the case of using InP is on InGaAs (P) active layer 9 ₁ crystal grown n-type thereon, is formed by vacuum-depositing a metal thin film.

The load resistors 2 ₁ and 2 ₂ can be formed on the surface of the semiconductor substrate 8 to have appropriate sizes by impurity diffusion.
The electrode 3 is an output electrode, the electrode 4 is an electrode for applying an external bias voltage, and the electrode 5 is a ground electrode. The film 7 is an insulating thin film provided between the semiconductor substrate and the wiring electrode or each electrode terminal, and is a thin film of SiN or the like formed by CVD (chemical vapor deposition) or the like.

Next, FIG. 3 shows an embodiment in which the structure of the present invention, including a semiconductor light emitting element for outputting a periodic light pulse, is integrated on the same semiconductor substrate. In this case, in order to integrate the light emitting element on the semiconductor substrate 8 of the integrated circuit, a GaAs substrate is used for a short wavelength, and an InP substrate is used for a long wavelength.

The semiconductor light emitting element 11 _1, GaAlAs and GaAs on a semiconductor substrate 8 or InGaAs,
It is formed by crystal growth of (P) and InP. MSM1 ₁ is formed by providing symmetrical Schottky junction on the light emitting element 11 _1. Here, by providing a periodic current pulses corresponding to the clock to the light emitting element 11 _1, the periodic light pulses (A) is input from the semiconductor inside the light receiving element 1 _1, steady electrical signals from the light receiving element 1 ₁ Is obtained. Here, the electrodes 6 ₁ , 6 ₂
The electrode of the semiconductor light-emitting element for outputting a periodic optical pulses, the layer 9 ₂ An anode layer, the layer 9 ₃ cathode layer, the layer 9 ₄ is an active layer.

From the above description, it can be seen that a photoelectric negation logic circuit using an MSM operated by a single bias voltage source and its integrated circuit can be realized very easily. This makes it possible to reduce the size of the entire circuit including the bias power supply, and eliminates the troublesome work of setting the two bias voltages strictly equal, which is indispensable in the prior art. Can be. Further, since the circuit is free from noise such as ripples superimposed on the bias voltage source, the stability of the circuit is dramatically improved.

In particular, since the MSM has a planar structure suitable for integration and has good alignment with the FET, the impedance conversion is provided at the subsequent stage of the output terminal of the photoelectric NOT logic circuit. It is also suitable for connecting and integrating amplifier circuits such as circuits. The circuit thus obtained can operate at an ultra-high speed, and has the potential to maximize the characteristics of light.

[0029]

According to the present invention, in a NOT logic using an optical signal, a remarkable simplification of a circuit and a drastic improvement in stability of a logic operation can be achieved. Moreover, it has ultra-high speed operation and wide dynamic range characteristics. For this reason,
The versatility of the circuit is high, and it is possible to design the circuit quite freely. This is particularly effective when configuring an integrated circuit. In particular, when high-density integration of photoelectric conversion elements is required as in image processing and the like and the number of data is large, it is very effective and is expected to help real-time image processing.

[Brief description of the drawings]

FIG. 1 is a diagram of a photoelectric negation logic circuit according to an embodiment.

FIG. 2 is a diagram of an embodiment in which the circuit of FIG. 1 is integrated on the same semiconductor substrate.

FIG. 3 is a diagram showing an embodiment in which a semiconductor light emitting element that outputs a periodic light pulse is integrated on the same semiconductor substrate.

FIG. 4 is a diagram showing a photoelectric negation logic circuit according to the prior art.

[Explanation of symbols]

1 ₁ , 1 ₂ ... Semiconductor light receiving element (MSM photodetector) having a substantially symmetrical planar structure in which a pair of Schottky junctions are formed with a gap of several μm, 2
₁ , 2 ₂ ... load resistance, 3 ... output terminal, output electrode, 4 ... electrode for applying external bias, 5 ... ground electrode, 6 ₁ ,
6 ₂ : electrodes of a semiconductor light emitting element for outputting integrated periodic light pulses, 7: insulating thin film (SiN, etc.), 8: semiconductor substrate of integrated circuit (Si, GaAs, InP, etc.), 9 ₁ : M
SM photodetector active layer, 9 ₂ ... Integrated semiconductor light emitting device assault layer, 9 ₃ ... Integrated semiconductor light emitting device cathode layer, 9 ₄ ... Integrated semiconductor light emitting device active layer, 11 ₁ , 11 ₂ ... Semiconductor light emitting device (LED, semiconductor laser), 12 ... Bias voltage (source), 13 ... Semiconductor light emitting device 11
A current pulse source to be supplied to ₁ , A: periodic light pulse. B ...
Optical pulse input signal, 41 ₁ , 41 ₂ ... semiconductor light receiving element having a symmetrical electrode structure in which rectifying junctions are connected in opposite directions, 42 ... load resistance, 43 ... output terminal,
412 ₁ , 412 ₂ ... bias voltage (source).

──────────────────────────────────────────────────続 き Continuing on the front page (72) Takashi Iida, 1126 Nomachi, Ichinomachi, Hamamatsu City, Shizuoka Prefecture Inside (72) Inventor Yoshihisa Hoshina 1126, Nomachi, Ichinomachi, Hamamatsu City, Shizuoka Prefecture Hamamatsu Photonics Co., Ltd. (72) Inventor Kenichi Sugimoto 1126, Nomachi, Ichinomachi, Hamamatsu City, Shizuoka Prefecture Inside (72) Inventor Tomoko Suzuki 1126, Nomachi, Ichinomachi, Hamamatsu City, Shizuoka Prefecture Inside Hamamatsu Photonics Corporation (72) Inventor Hirofumi Suga 1126 Nomachi, Hamamatsu City, Shizuoka Prefecture Hamamatsu Photonics Co., Ltd. (56) References JP-A-2-4014 (JP, A) JP-A-2-256319 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 19/14 H03K 17/78

Claims (2)

(57) [Claims] A first pair of substantially symmetrical Schottky electrodes are formed on a semiconductor in close proximity to each other to form a plane, and one terminal of each is commonly connected. And a second light receiving element; a first load element having one end connected to the other terminal of the first light receiving element and the other end grounded; one end connected to the common connection point; A second load element to which a predetermined bias voltage is supplied, wherein the other terminal of the first light receiving element is a signal output terminal, and the other terminal of the second light receiving element is grounded. When a first periodic light pulse is incident on the first light receiving element, a corresponding periodic electric pulse signal is output from the signal output terminal, and a second periodic light pulse is output to the second light receiving element. 2 light pulses are incident It said periodic electrical pulse signal is erased, whereby the photoelectric negative logical circuit being characterized in that as negative negative electric output signal is obtained for the second optical pulse. 2. The method according to claim 1, wherein the semiconductor is GaAs, InP, InG.
aAs or InGaAsP substrate;
And a second light receiving element, the first and second load elements, and a light emitting element for outputting the first and second light pulses are integrated on the substrate. A photoelectric negation logic circuit as described.