JP3220037B2 - Transistor placement method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CMOS LSI
The present invention relates to a technology for synthesizing the layout of LSI leaf cells, such as standard cells and data path leaf cells, used in an electric circuit such as the one described above, and particularly to a method for determining the arrangement of transistors in a cell region.

[0002]

2. Description of the Related Art In recent years, semiconductor process technology has been progressing at a rapid pace, and technological innovations are being made one after another. If a design and development of a cutting-edge high-performance system is planned in response to process innovation, a new cell library must be developed each time. In addition, since various processes exist at the same time and each process is used for each application, a cell library must be prepared for various processes. Further, in the design of LSI systems, the targets are diversified, such as high-speed operation-oriented and low-power-consumption oriented, and the cell library must cope with such a spread of the targets. That is, in recent years, the development frequency of the cell library has been extremely increased, and there is a reality that an extremely large number of cells must be prepared in one library. And
With the entry into the deep submicron era, the complexity of mask design rules (design rules) has further exacerbated the reality facing the development of cell libraries.

Conventionally, in the development of a standard cell library and the development of a dedicated cell library for a data path, the layout design of a cell has almost exclusively relied on manual labor. This is because the area of the leaf cell directly affects the block area and further the chip area, so it is necessary to design a highly integrated cell. In this case, at least in the near future, it will be clear that human layout design will fall short of development requirements. Therefore, the importance of the cell layout synthesis technology is expected to increase rapidly in the future.

[0004] Cell layout synthesis (cell synthesis) is to generate a transistor-level mask layout from a transistor-level netlist by using design rules. Generally, (1) transistor layout,
(2) Inter-transistor wiring, (3) Compaction 3
It consists of two processes. The cell synthesis method or the transistor-level placement and wiring method has been intensively studied. However, in most of these studies, in order to simplify the computer processing, a large restriction is imposed on the input circuit and the arrangement style of the transistors in most cases.

[0005] An example of the restriction is the use of a one-dimensional arrangement model. The one-dimensional arrangement model is a transistor arrangement form in which P-type transistors and N-type transistors are arranged one row at a time with the gate width direction aligned with the cell height direction, and these two rows are arranged in parallel. In recent years, since a large number of cells must be prepared in one cell library, the sizes of transistors used in the cells have been diversified. In such a situation, when the one-dimensional arrangement model is adopted, the ratio of cells for which an optimal layout cannot be formed with respect to a single cell height determined in the cell library cannot be ignored. Therefore, in developing a practical cell synthesis system from now on, it is necessary to adopt a method which is not restricted by the one-dimensional arrangement model. "T. Uehara and WMvanCleemput," Op
timal Layout of CMOS Logic Cells, "25th ACM / IEEE Tr
ans. Computer Vol.c-30, pp.305-312, May 1981 "proposes that the layout area can be reduced by sharing the diffusion layer between adjacent transistors. Since then, algorithms that maximize the diffusion sharing have been P-type. Transistor and N
Although many proposals have been made, including those relating to the pairing problem with a type transistor, most of these algorithms are based on a one-dimensional arrangement model.

[0006] Although there are a few methods that do not assume a one-dimensional arrangement model, there have been proposed. Although a method has been proposed in which a pair of a P-channel region and an N-channel region is repeated in a plurality of stages in a cell, and a cell whose size is also variable in the height direction can be generated in each channel region using a one-dimensional arrangement. This approach would be more effective for macro cells than standard cells. On the other hand, similarly to the one-dimensional arrangement, the cell is divided into two channel regions of P / N, and in each channel region, a plurality of transistors can be vertically stacked in the height direction of the cell. The method that can be changed is "CJPoirier," Excellerator: Custom CMOS
Leaf Cell Layout Generator, "IEEE Trans.On Computr
Aided Design Vol.8, No.7, pp.744-755, July 1989 ". It seems that this is also effective for standard cells, but there are restrictions such as the need to align transistors and uniform transistor size, and it handles degrees of freedom comparable to manual design It can not be said. "DGBaltus, J. Allen," SOLO: A Gene
rator of Efficient Layouts From Optimized MOS Circ
uit Schematics, "Design Automation Conference, pp.44
5-452, 1988 ", but cell circuits are divided into sub-circuits, and cells are not necessarily optimized as cells because a specific arrangement pattern (gate matrix style) is applied to the sub-circuits. Absent.

[0007] "Chi Yi Hwang, Yung-Ching Hsieh,
Youn-Long Lin, Yu-Chin Hsu, "AnEfficient Layout St
yle for Two-Metal CMOS Leaf Cells and Its Automati
c Synthesis, "IEEE Trans. on Computer-Aided Design
of Integrated Circuits and Systems, Vol. 12, No. 3,
pp. 410-424, March 1993,
It is recognized that the cell height must be reduced as well as the cell width in order to optimize the layout, and the problem of optimizing the wiring in the cell, which is the factor that determines the cell height, is important in transistor placement It is becoming.

A number of methods for optimizing the wiring between elements in the placement problem are known from studies on the problem of optimally arranging standard cells on a block.
Even if these are applied as they are to the transistor arrangement problem, the cell layout cannot be optimized. To optimize cells while considering both cell width and cell height,
Two optimization indexes, that is, optimization of diffusion by minimizing diffusion isolation (maximization of diffusion sharing) and optimization of wiring, must be handled simultaneously. In the conventional transistor arrangement method, instead of simultaneously considering the two optimization indices, the optimization is divided into two stages, the first optimization is performed with one index, and the second optimization is performed with the other index. Was used. As a typical method, a partial circuit is extracted from a circuit of a given cell, and the transistor arrangement in the extracted partial circuit is performed for the purpose of optimizing diffusion, and the arrangement result is set as a group of transistors. Is well known for the purpose of wiring optimization.

Further, in the conventional method, when arranging transistors in a one-dimensional arrangement style, P-type transistors and N-type transistors are arranged on a horizontal grid point row with a constraint that they are aligned vertically, and grid coordinates are set. Is used to evaluate the placement. An example is found in the above-mentioned CYHwang literature.

[0010]

In order to apply the cell synthesis by a computer to the development of an actual cell library, the problem of the cell area, that is, the problem of how to increase the degree of integration of the cells to the level of the layout design by hand, has to be solved. Must be resolved. In order to solve this problem, it is necessary to optimize the cell layout while giving complete two-dimensional degrees of freedom to transistors, which are arrangement elements in the cell. However, as described above, the conventional cell synthesis method imposes great restrictions on input circuits and transistor layout styles for simplifying computer processing, so that a flexible layout similar to that of a human operator is required. It was not enough to realize.

On the other hand, if the transistors are arranged by a computer after giving the transistors complete two-dimensional degrees of freedom, the processing takes an enormous amount of time, which is not practical.

Further, in the conventional transistor arrangement method, the optimization of the diffusion and the optimization of the wiring are separately performed in two stages, so that an optimal transistor arrangement cannot always be obtained comprehensively. In particular, in the method of extracting partial circuits and grouping transistors, when the number of transistors in each group is large, the final transistor arrangement result strongly depends on the selection of the partial circuit. There is a high possibility that the result falls into a local optimal solution, and the processing efficiency is high. However, there is a problem that the degree of optimization varies depending on cells.

In the conventional method, when arranging transistors in a one-dimensional arrangement style, a P-type transistor and an N-type transistor are arranged on a horizontal grid point row with a constraint that they are vertically aligned, and grid coordinates are set. Was used to perform the placement evaluation. However, according to the actual mask design rules, when the adjacent transistors share the diffusion electrode, the distance between the gates differs between when the electrode is contacted and when it is not, so in the layout after compaction The P-type transistor and the N-type transistor are not always aligned vertically. Further, an actual cell may include transistors having different gate lengths. At this time, it is difficult to lay out the P-type transistor and the N-type transistor vertically. That is, in the conventional transistor arrangement, there is a problem that the arrangement evaluation according to the actual layout is not performed.

In view of the above problems, the present invention provides a method for determining the arrangement of transistors in a cell by using a computer, which can realize a cell integration degree equivalent to that of a layout design by hand, and is practical. It is an object to enable processing within a time.

It is another object of the present invention to provide a transistor placement method using a one-dimensional placement form, which performs placement evaluation according to an actual layout, and realizes both diffusion optimization and wiring optimization. And

[0016]

In order to solve the above-mentioned problems, the present invention provides a method for arranging transistors, which involves global optimization by one-dimensional arrangement and then local improvement by two-dimensional arrangement. By doing so, it is possible to achieve a cell integration degree equivalent to a layout design by hand. The present invention also proposes a method of converting a transistor arrangement from a lattice diagram to a mask diagram, and an evaluation index for realizing both optimization of diffusion and optimization of wiring.

[0017] Specifically, a solution taken by the invention of claim 1 is that, for a cell having at least one transistor, the cell is connected based on a netlist describing connection information of the transistor in the cell and size information of each transistor. As a transistor arrangement method for determining the arrangement of transistors in a region, when the height of the cell in the vertical direction is set to a predetermined value and the width of the cell in the horizontal direction is variable, the cell region is divided into a P-channel region and an N-channel. The P-type transistors included in the cell are vertically arranged in the P-channel region according to the netlist in the vertical direction and the gate width direction. And the N-type transistor of the cell is placed vertically in the N-channel region in the horizontal direction of the cell. One-dimensional arranging step of arranging the transistors in one column, and arranging the transistors in a plurality of columns in the left-right direction of the cell in each channel region with respect to the transistor arrangement result of the one-dimensional arranging step, A two-dimensional arrangement step of changing the arrangement of transistors so that the width of the cell can be reduced, in addition to the two-dimensional arrangement step, in which the arrangement can be performed in a horizontal state where the cell is arranged in the width direction.

According to the first aspect of the present invention, in the one-dimensional arrangement step, the transistors included in the cells are arranged in a row in the P-channel region and the N-channel region in a vertically arranged state. In the case of an arrangement type having such a constraint, the arrangement of the transistors can be easily performed by a computer within a practical time, and can be optimized to some extent. In the two-dimensional arrangement step, the constraints in the one-dimensional arrangement step are removed so that the transistors can be arranged in a plurality of columns in the left and right direction of the cell and the transistors can be arranged in the horizontal state in each channel region. Are changed so that the width of the transistor becomes smaller. As a result, the result of the transistor arrangement by the one-dimensional arrangement process is improved, the cell can be made more compact, and the degree of integration of the cell can be realized at the same level as the layout design by hand. In addition, since global optimization has already been performed in the one-dimensional arrangement process, only the local transistor arrangement improvement is performed in the two-dimensional arrangement process. Also, the load on the computer is remarkably reduced, and processing can be performed within a practical time.

According to a second aspect of the present invention, in the transistor arrangement method of the first aspect, transistors of the same conductivity type in which the diffusion electrodes form a serial connection including no branch are extracted from the netlist. A group forming step of grouping the extracted transistors into one group; wherein the one-dimensional arrangement step and the two-dimensional arrangement step include, as a single arrangement element, the transistors arranged in one group in the group formation step, Shall be performed.

According to the second aspect of the present invention, transistors of the same conductivity type in which diffusion electrodes form a serial connection that does not include a branch are grouped into one group. The layout of transistors of the same conductivity type in which the diffusion electrodes form a series connection that does not include a branch becomes one diffusion island, and this layout does not change even when the transistor arrangement of the entire cell is optimized. That is, the transistor arrangement in the group is uniquely determined. Therefore, even if the transistors grouped in one group are treated as a single element, the optimization of the transistor arrangement of the entire cell is not affected. Therefore, by treating the transistors grouped in one group as a single arrangement element, the load on the computer in the transistor arrangement processing can be reduced without hindering the optimization of the transistor arrangement of the entire cell.

According to the third aspect of the present invention, in the first aspect,
One-dimensional arrangement step in the transistor arrangement method of
In the dimension arrangement step, transistors are arranged using an evaluation index based on an estimated value of a wiring length in a cell.

According to a fourth aspect of the present invention, in the transistor arranging method according to the third aspect, the one-dimensional arranging step and the two-dimensional arranging step divide the wiring of each net into a plurality of components based on the positioning in the net. The wiring length is estimated for each of the divided components, and the sum of the estimated wiring length of each component and the weighted value is used as an evaluation index of the transistor arrangement.

According to the fourth aspect of the present invention, it is possible to accurately evaluate a wiring length when a transistor is used as an arrangement element.

According to a fifth aspect of the present invention, in the transistor arranging method according to the fourth aspect, the one-dimensional arrangement step and the two-dimensional arrangement step include a step of assigning a wiring of each net to a polysilicon layer and a step of assigning a wiring to each metal layer. The sum of the estimated values of the wiring lengths of the components allocated to the polysilicon layer and the estimated values of the wiring lengths of the components allocated to the metal layer, which are differently weighted, is used as an evaluation index of the transistor arrangement. .

[0025] In the invention of claim 6, according to claim 1,
Wherein the cell is a MOS logic cell, and based on a netlist, a stage that sets, for each transistor, a stage that is the number of gates on the path from the transistor to a signal output terminal to which the transistor pertains A setting step is provided. In the one-dimensional arrangement step, the transistor arrangement order is determined using the stages of the transistors set in the stage setting step.

According to the sixth aspect of the present invention, one of the transistors
By using the concept of a stage at the time of dimensional arrangement, circuit information can be reflected, so that the processing efficiency of one-dimensional arrangement can be increased.

According to a seventh aspect of the present invention, in the transistor arrangement method according to the first aspect, the wiring density of a horizontal wiring component is determined for each transistor arrangement position in the horizontal direction of the cell based on the transistor arrangement result in the one-dimensional arrangement step. ,
When the layout height, which is the sum of the transistor height at the one transistor arrangement position and the wiring density of the horizontal wiring component, exceeds the set value of the cell height, the transistor arranged at the one transistor arrangement position is divided by gate folding. Then, it is assumed that a transistor folding step for correcting the transistor arrangement result in the one-dimensional arrangement step is provided with the divided transistors as new arrangement elements.

According to the seventh aspect of the present invention, since the transistors are folded in consideration of the wiring density obtained from the transistor arrangement result in the one-dimensional arrangement step, the transistors can be folded in accordance with the actual layout .

[0029] Also, solutions of the invention were taken according to Claim 8, for a cell having at least one transistor, based on the net list describing the connection information of the transistors in the cell, the arrangement of the transistors in the cell area As a transistor placement method to be determined, the wiring of each net is divided into a plurality of components based on the positioning in the net, the wiring length is estimated for each of the divided components, and the weighted value of the estimated wiring length of each component is summed. The arrangement of the transistors is determined by using the result as an evaluation index.

Further, according to the ninth aspect of the present invention, the above-mentioned claim is provided.
8 , the wiring of each net is divided into a component to be allocated to the polysilicon layer and a component to be allocated to the metal layer, and the estimated value of the wiring length of the component to be allocated to the polysilicon layer and the wiring length of the component to be allocated to the metal layer are determined. It is assumed that the arrangement of the transistors is determined by using, as an evaluation index, a sum of values obtained by adding different weights to the estimated value.

According to a tenth aspect of the present invention, in a MOS logic cell having at least one transistor, each MOS transistor in a cell region is based on a netlist describing connection information of the transistor in the cell. As a transistor arrangement method for determining the arrangement, based on a netlist, for each transistor, a stage setting step of setting a stage that is the number of gates on the path from the transistor to the signal output terminal to which the transistor pertains, An arrangement step of arranging the transistors included in the cells in a column in the cell region based on the netlist, wherein the arrangement step determines the arrangement order of the transistors using the stages of the respective transistors set in the stage setting step. Things.

Further, solutions for the invention is taken of claim 11, at least for a cell having a single transistor, based on the mask design rules derived connection information of a transistor in the cell from the netlist, and semiconductor fabrication techniques described As a transistor arrangement method for deciding the arrangement of transistors in the cell region, a plurality of lattice points are arranged in the lateral direction of the cell to set a lattice point array, and a P-channel region and an N
An N-channel region for arranging type transistors is set in parallel to the grid point row, and based on the netlist, P-type transistors included in the cell are arranged one for each grid point position in the P-channel region. A first step of forming a transistor arrangement on a lattice point sequence by arranging N-type transistors of the cell one by one for each lattice point position in the N-channel region; Based on the arrangement, transistors are arranged on the mask diagram so as to satisfy the mask design rule in order from one side in the horizontal direction of the cell to the other side in each channel region, thereby masking the transistor arrangement on the grid point sequence. A second step of forming the transistor arrangement on the figure, and a transistor on the mask diagram formed in the second step; A third step of evaluating the transistor arrangement and, based on the evaluation result, changing the transistor arrangement in the transistor arrangement on the lattice point sequence on which the transistor arrangement on the evaluated mask diagram is based, comprising the steps of: The third step is repeated, and in the second step, at the beginning of the repetition, the transistor arrangement on the mask diagram is formed from the transistor arrangement on the lattice point sequence formed in the first step, while the second and subsequent times Is to form a transistor arrangement on a mask diagram from a transistor arrangement on a lattice point sequence in which the arrangement of transistors is changed in the third step.

According to the eleventh aspect of the present invention, the transistor arrangement on the lattice point sequence is converted into a transistor arrangement on the mask diagram and evaluated, and the transistor arrangement is changed based on the evaluation result. The layout evaluation according to the layout is performed.

[0034] In the invention of claim 12, wherein the billing
The second step in the transistor arrangement method according to item 11 is:
When a transistor is arranged on the mask diagram in the same channel region as the one transistor at a lattice point from one side of the one transistor, the transistor is arranged on the mask diagram. On the other hand, if the transistor is not arranged, the transistor is arranged at the same lattice point position as the one transistor in a channel region different from that of the one transistor, and the transistor is placed on a mask diagram. Is determined based on the arrangement position of this transistor on the mask diagram when the arrangement position has already been determined.

According to the twelfth aspect of the present invention, when a transistor is arranged at each lattice point on one side in the same channel region, the transistor on the mask diagram is determined based on the arrangement position of the transistor on the mask diagram. Determine the placement position of. On the other hand, when the transistor is not arranged, when the transistor is arranged at the same lattice point position in a different channel region and the arrangement position of the transistor on the mask diagram has already been determined, the arrangement of the transistor on the mask diagram is determined. The arrangement position of the transistor on the mask diagram is determined based on the position. Accordingly, compared to a method of simply packing each channel region to one side or a method of aligning the positions of a P-type transistor and an N-type transistor arranged at the same lattice point, a transistor arrangement in a lattice point array is relatively relatively reduced. It can be reflected on the mask diagram in a form conforming to the actual layout.

According to the thirteenth aspect of the present invention, the above-mentioned claim is provided.
The third step in the eleventh transistor arrangement method is to estimate the spread of each net on the mask diagram by dividing the spread into a plurality of pieces based on the electrodes of the transistors constituting the net, and to add the weighted values to the estimated values of each spread. It is assumed that the transistor arrangement on the mask diagram is evaluated using the evaluation result as an evaluation index.

According to the thirteenth aspect of the present invention, the position of the transistor electrode is reflected in the spread of each net as an evaluation index of the transistor arrangement on the mask diagram, and the spread of the diffusion electrode is an index for evaluating the degree of diffusion sharing. Because
The optimization of the wiring and the optimization of the diffusion can be realized at the same time.

Further, in the invention according to claim 14 , the request
A third step in the transistor arrangement method according to item 13 is:
The spread of each net on the mask diagram is estimated by dividing it into four, namely, the spread of the diffusion electrode of the P-type transistor, the spread of the diffusion electrode of the N-type transistor, the spread of the gate electrode, and the spread of all the electrodes. It is assumed that the transistor arrangement on the mask diagram is evaluated using the sum of the weighted values of the estimated values as an evaluation index.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a cell layout synthesizing technique, and more particularly to a proposal of a new method relating to a transistor general layout technique.

FIG. 1 is a flowchart showing the flow of the processing of the cell layout synthesis (cell synthesis) method. As shown in FIG. 1, cell synthesis means a transistor-level mask layout pattern 2 of a cell using a mask design rule from a transistor-level netlist 1 that describes the cell.
In general, the cell synthesizing method includes three steps of a transistor general arrangement ST1, an inter-transistor wiring ST2, and a compaction ST3. The transistor general arrangement ST1 is a process of determining a general arrangement position of a transistor in a cell based on the transistor level netlist 1. Here, the meaning of the general arrangement means that the arrangement position of the transistors in the cell is not finally determined by the general transistor arrangement ST1, but rather is determined by the inter-transistor wiring ST2 based on the general arrangement result by the general transistor arrangement ST1. After finding a wiring path satisfying the connection request, the final layout position of the transistor is determined in the compaction ST3 while determining the mask layout pattern 2 including the wiring according to the mask design rule. The transistor arrangement method according to the present invention is positioned to execute a schematic arrangement of transistors in cell synthesis.

Hereinafter, a transistor arrangement method according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a diagram showing a cell model targeted by the transistor arrangement method of the present invention. In the present invention, a general design style of a standard cell is assumed. As shown in FIG. 2, as for the size of the target cell, the height in the vertical direction is fixed at a given given value, and the width in the horizontal direction is variable. Then, the power supply wiring 4 and the ground wiring 5 are arranged at the upper end and the lower end of the cell, the area between the power supply wiring 4 and the ground wiring 5 is divided into two, and the upper area is a P-type transistor 6 where the P-type transistor 6 is arranged. The channel region 8 and the lower region are an N-channel region 9 where the N-type transistor 7 is arranged. The P channel region 8 and the N channel region 9 are separated by a channel boundary 10.

The case where the gate width direction of the arranged transistor is the same as the vertical direction of the cell is referred to as the vertical placement of the transistor, and the case where the gate width direction of the arranged transistor is the same as the horizontal direction of the cell is the lateral position of the transistor. We call it rest.

Note that the input / output terminal positions of the cell are not set in advance, and the terminal positions (approximate) are set based on the arrangement results of the transistors.

In the system for executing the transistor arrangement method of the present invention, the inputs and outputs are as follows.

[Input] (1) Transistor level net list. The number of transistors arranged in the two channel regions may be different. (2) Mask design rules derived from the applied process technology. Although the transistor arrangement method determines the arrangement of the transistors, it is necessary to numerically evaluate the wiring density and the sharing / separation of diffusion in terms of the mask size when evaluating the arrangement. See

[Output] A schematic arrangement position including the direction of the transistor in the cell.

(First Embodiment) The method for arranging transistors according to the present embodiment seeks to optimize the transistor arrangement by combining one-dimensional arrangement and two-dimensional arrangement.

The one-dimensional transistor arrangement means that P-type transistors are vertically arranged in the P-channel region (with the gate width aligned in the vertical direction) in the form of columns extending left and right, and in the N-channel region. N-type transistors are vertically arranged in rows extending left and right, and are arranged so as to form one transistor row for each channel region.
On the other hand, the two-dimensional transistor arrangement refers to an arrangement in which transistors are given full two-dimensional freedom in each channel region, except for the constraint conditions seen in the one-dimensional arrangement.

In the cell library of standard cells,
Since the cell height is set assuming a one-dimensional arrangement of standard-size transistors, it is necessary to basically use a one-dimensional arrangement style when arranging transistors of standard cells. However, if the result of the one-dimensional transistor arrangement is directly developed into a mask layout, there is a large space in the layout due to an increase in the size of transistors used in one cell library and an increase in variation in the size of transistors used in one cell. Problems such as the formation of an area occur.

In order to solve this problem, the transistor arrangement method according to the present embodiment provides a one-dimensional arrangement by locally correcting, by a two-dimensional arrangement, a transistor arrangement result globally optimized by a one-dimensional arrangement. This is intended to reduce a vacant area that may be generated by only the arrangement result, and realize a mask layout with a higher degree of integration.

FIG. 3 is a flowchart showing the flow of processing of the transistor arrangement method according to the first embodiment of the present invention, and corresponds to the transistor general arrangement ST1 in the cell synthesis method shown in FIG. Hereinafter, the transistor arrangement method according to the present embodiment will be described with reference to FIG.

First, in step ST10, a netlist describing a cell is read, and information on connection requirements between transistors and the size of each transistor is stored. FIG. 4 is a circuit schematic diagram showing an example of a circuit represented by the input netlist. In FIG.
tp12 is a P-type transistor, tn0 to tn12 are N-type transistors, IN1, IN2 are input terminals, OUT1,
OUT2 is an output terminal, 11 is a power supply, 12 is ground, 1
3 is a connection relation. In the netlist, information on the size of each transistor is described in addition to the information on the connection 13 as shown in FIG.

Next, in step ST11, the transistors are grouped (clustered). Transistor grouping is performed in order to hierarchically process the transistor arrangement. A plurality of transistors are grouped into one group on a circuit, and the transistor arrangement problem is divided into a transistor arrangement problem within the group and a group arrangement problem. In this case, the solution of the transistor arrangement problem is efficiently obtained. Step S11 constitutes a group forming step.

Here, attention must be paid to how to determine the group, that is, the conditions for grouping the transistors. This is because, when there are many choices of transistor arrangement in a group, the arrangement of transistors in the group may not be appropriate depending on the arrangement result of the group.

For this reason, in the present embodiment, only transistors connected in a simple series relationship without branching are grouped so that the arrangement of transistors in the group does not include arbitrariness. That is, transistors of the same conductivity type in which diffusion electrodes form a serial connection that does not include a branch are grouped into one group. Transistors that do not form a series connection as described above are considered to constitute a series connection in a broad sense by themselves, and are grouped by a single transistor.

FIG. 5 shows a group formation S for the circuit of FIG.
It is a figure showing the result of having performed T11. In FIG.
The dashed line surrounding a plurality of transistors together is Group 1.
5 is shown. That is, six groups of (tp0, tp1), (tp4, tp5), (tp8, tp9), (tn0, tn1), (tn4, tn5) and (tn8, tn9) are formed. All other transistors are grouped by a single transistor.

When transistors connected by a simple series relationship without branches, that is, transistors of the same conductivity type in which diffusion electrodes form a serial connection without branches, are grouped, all interconnects between transistors in the group are 2 Since the terminals are connected, the transistors belonging to one group can be laid out in one diffusion island without fail, and there is no need to insert a contact between the transistors.

FIGS. 6A and 6B are diagrams for explaining transistor arrangement in a group. FIG. 6A shows transistors belonging to one group according to the present embodiment, that is, transistors connected by a simple series relationship without branch. FIG. 3B shows a layout of transistors belonging to the group shown in FIG. In FIG. 6B, 2
1 is a gate electrode, 22 is a diffusion electrode (drain), 23 is a diffusion electrode (source), and 24 is a ground wiring. FIG.
When the transistors belonging to one group as shown in FIG. 6A are arranged in order so as to follow a series connection of the diffusion electrodes, one diffusion island as shown in FIG. 6B is obtained.

As a layout of transistors connected in a simple series relationship without branching, a form of a diffusion island as shown in FIG. 6B is an optimal solution. Also, in the optimal solution of the transistor arrangement of the entire cell, the transistors connected by a simple series relationship without branching must be used as shown in FIG.
It is considered that the layout is made as a diffusion island as shown in FIG. In other words, in the case of the grouping according to the present embodiment, it can be said that even if the mutual arrangement of the transistors belonging to each group is specified from the beginning, it does not become a minus for the optimization of the transistor arrangement of the entire cell. Therefore, by performing such grouping as pre-processing of the transistor arrangement step, and performing transistor arrangement with transistors arranged in one group as a single arrangement element, the load on the transistor arrangement optimization processing is reduced. can do. The grouping according to the present embodiment is effective as the minimum grouping necessary for optimizing the transistor arrangement of the cell.

Hereinafter, a one-dimensional arrangement process is constituted by steps ST12 and ST13, and step ST14 is performed.
To ST16 constitute a two-dimensional arrangement process.

First, the one-dimensional arrangement step will be described. In the one-dimensional arrangement step according to the present embodiment, first, a one-dimensional lattice space extending left and right is set in a cell, and each transistor constituting the cell is arranged at any one lattice point on the set one-dimensional lattice space. Things. At this time, the transistors are arranged using the wiring length or the wiring density as an evaluation index so that an empty area is generated to the extent that the transistor arrangement can be sufficiently optimized in the subsequent two-dimensional arrangement step.

In step ST12, a one-dimensional lattice space extending left and right is set in the cell. And step S
At T13, the optimal assignment of each transistor constituting the cell to the one-dimensional lattice space is determined, and each transistor is arranged at any one lattice point in the one-dimensional lattice space.

FIG. 7 is a diagram showing a one-dimensional lattice space and a one-dimensional arrangement of transistors, and corresponds to the circuit shown in FIG. As shown in FIG. 7, one P-type transistor and one N-type transistor can be arranged at one lattice point, and each transistor is arranged vertically at each lattice point. The distance between the lattices is set separately in the P-channel region and the N-channel region, and is set differently in the same channel region depending on whether adjacent transistors share diffusion or not.

Next, the two-dimensional arrangement step will be described. The two-dimensional arrangement process according to the present embodiment is positioned as a post-process of the one-dimensional arrangement process so as to be practically optimal including the problem of the processing time. That can be arranged in a plurality of columns and that the transistors can be arranged horizontally, where the horizontal direction of the cell and the gate width direction are the same, and then the local arrangement of transistors is changed so that the cell width is reduced It is. That is, the transistor arrangement method according to the present embodiment is characterized in that global optimization is performed by one-dimensional arrangement, and then two-dimensional arrangement is performed to locally improve the arrangement result.

First, in step ST14, a two-dimensional lattice space is set to prepare for a two-dimensional transistor arrangement. In the two-dimensional lattice space, a transistor as an arrangement element is represented by a directed line segment having a direction and a length based on a gate width. The two-dimensional transistor arrangement is 2
This is performed by allocating the directed line segment representing the transistor to each grid point on the three-dimensional grid space without duplication.

For this purpose, in step ST15, the one-dimensional arrangement result of the transistors in step ST13 is mapped to a two-dimensional lattice space. FIG. 8 is a diagram showing a result of mapping the one-dimensional arrangement of the transistors shown in FIG. 7, that is, the one-dimensional arrangement result of the circuit shown in FIG. 5 into a two-dimensional lattice space. As shown in FIG. 8, a directed line segment representing each transistor is assigned to each lattice point in a two-dimensional lattice space, a P-type transistor is assigned to each lattice point in a P-channel region, and an N-type transistor is assigned to N Each is assigned to each grid point in the channel region.

Using the mapping result as shown in FIG. 8 as the initial arrangement, the two-dimensional transistor arrangement is optimized in step ST16. The optimization of the two-dimensional transistor arrangement is performed by repeatedly changing the arrangement of the transistors while evaluating the arrangement of the transistors on the mask (on the actual layout). The change in the arrangement of the transistors is performed in a group unit, and the transistors left alone at the time of grouping are regarded as a group including only one transistor. Note that when transistors are not grouped, the arrangement may be changed in units of transistors.

The arrangement change is specifically performed as follows. First, a group to be moved (group A) is randomly selected. Next, a destination grid point is randomly selected for the group A. At this time, the selection range of the destination grid point may be limited. Then, it is checked whether the group A does not overlap with another group when the group A is moved to the selected destination grid point. If they do not overlap, the group A is moved to the selected destination grid point. Group A and other groups (Group B)
When they overlap, it is checked whether the group A and the group B can be rearranged. If the arrangement can be exchanged, the exchange is performed. If the arrangement cannot be exchanged, the movement of the group A to this lattice point is stopped.

The evaluation of the arrangement is performed as follows. FIG. 9 is a diagram showing the two-dimensional transistor arrangement in the process of executing the transistor two-dimensional arrangement optimization ST16.
The arrangement is changed with the mapping result shown in (1) as the initial arrangement. First, a wiring route is assumed on the lattice space after the arrangement change. Specifically, one horizontal wiring (main line) is drawn in the channel boundary region for each net (a set of terminals having the same potential), and a vertical wiring is drawn from each terminal of the net toward the main line. For example, as shown in FIG. 9, the diffusion electrodes of the transistors tp7, tp9, tn7, tn9 and the transistors tp10, tp12, tn10, tn12
A trunk line 31 is drawn in the channel boundary region, a vertical wiring 32a is formed from the diffusion electrodes of the transistors tp7 and tp9 toward the main line 31, and a vertical wiring 32b is formed from the diffusion electrodes of the transistors tn7 and tn9.
From the gate electrode of the transistor tp10 to the vertical wiring 32
c is connected to the vertical wiring 3 from the gate electrode of the transistor tp12.
2d, the vertical wiring 32e is drawn from the gate electrode of the transistor tn10, and the vertical wiring 32f is drawn from the gate electrode of the transistor tn12.

Next, the wiring density is registered on the grid side on the wiring path. For each grid side on the wiring path 30, the wiring density 3
3 is registered. Then, the arrangement of the transistors on the mask (on the actual layout) is calculated based on the positional relationship of the transistors in the two-dimensional lattice space and the wiring densities registered on each lattice side. For example, in FIG.
In determining the interval between 1 and tp5, the wiring density in the vertical direction passing between them, that is, the wiring density registered on the horizontal lattice side between the transistors tp1 and tp5 is considered. Then, a wiring length on the actual layout is calculated from the calculated transistor arrangement on the actual layout, and the arrangement is evaluated based on the calculated wiring length. Finally, the layout change is repeated so that the wiring length is reduced.

FIG. 10 is a diagram showing the result of executing the transistor two-dimensional layout optimization ST16 using the mapping result shown in FIG. 8 as the initial layout. From FIG. 10, it can be seen that the transistors are arranged in a plurality of columns in the left-right direction of the cell in each channel region, and some transistors are arranged horizontally, whereby the width of the cell is greatly reduced. .

FIG. 11 is a diagram showing a relationship between a mask pattern and an arrangement in a two-dimensional lattice space. In FIG. 11, (a) shows a mask pattern including transistors trA to trE,
(B) is an arrangement in a two-dimensional lattice space corresponding to the mask pattern shown in (a). In FIG. 11A, 16
Is a gate of the transistor, 17 is a diffusion region of the transistor, and 18 is a diffusion contact. Even in the adjacent transistors sharing the diffusion, the distance between the lattice points is different depending on whether or not the contact 18 is interposed (x3 <x1).

When the transistor size is smaller than the cell height, if a one-dimensional arrangement result is realized in a layout as it is, a large empty area is generated in the cell. In such a case, it is necessary to realize a flexible arrangement style as shown in FIG. However, if the arrangement is determined only by the two-dimensional arrangement in the two-dimensional lattice space, the processing time may be enormous. In the case of standard cells, the cell design rules are often set according to the one-dimensional arrangement of standard-sized transistors. It is considered to be optimal for practical use, including the problem described above. The transistor placement method according to the present invention pays attention to such a point, performs global optimization by one-dimensional transistor placement, and then performs two-dimensional transistor placement to locally improve the placement result.
It has the feature of. Note that transistor 2
For details of the dimension arrangement processing, refer to Japanese Patent Application No. Hei 7-3387.
No. 25 ".

Here, regarding the transistor arrangement method according to the present embodiment, evaluation indices in one-dimensional arrangement and two-dimensional arrangement will be described.

In the standard cell library, 3
In a medium-sized or larger cell including about zero or more transistors, the ratio of wiring in the cell increases. Therefore, when optimizing the transistor arrangement in the cell, the diffusion sharing is maximized. It is considered that the optimization focused on the wiring length is more effective than the optimization described above.

In the one-dimensional arrangement and the two-dimensional arrangement of the transistor arrangement method according to this embodiment, the transistor arrangement is optimized for the purpose of minimizing the wiring length by using an evaluation index based on the estimated value of the wiring length in the cell. Do. As a result, it is possible to keep close cooperation between the optimization processing of the one-dimensional arrangement and the optimization processing of the two-dimensional arrangement.

In the actual layout of the cell, the gate electrode of the transistor requires connection by a polysilicon layer and the diffusion electrode requires connection by a first metal layer. Further, sharing of diffusion between transistors means connection by a diffusion layer, and the distance between transistors changes depending on whether or not a diffusion contact is interposed therebetween. Further, regarding the transistor arrangement in the cell, it is required that the gates having the same potential are aligned between channels as far as possible in the horizontal direction. Such a constraint is a problem that does not appear when considering the minimization of the wiring length in the cell arrangement in which the standard cell is treated as the arrangement element.

In this embodiment, in order to cope with the above problem, the wiring of each net is divided into a plurality of components, the wiring length is estimated for each of the divided components, and the estimated wiring length of each component is calculated. The arrangement of the transistors is determined using the sum of the weighted values as an evaluation index.

FIG. 12 is a diagram showing an example of a typical wiring structure. In MOS logic, wiring between transistors is generally considered to connect a diffusion electrode group and a gate electrode group. Therefore, a wiring is formed by a first component connecting the diffusion electrodes and a second component connecting the diffusion electrode group and the gate electrode group. The component and the third component connecting the gate electrodes are divided into three components, and the wiring length is estimated for each component. For example, in FIG. 12, the diffusion electrode group of the transistors tr3 and tr6 and the transistor tr
For the wiring connecting the gate electrodes of 1, tr2, tr4 and tr5, the wiring length of the first component connecting the diffusion electrodes is estimated by the distance d1 between the diffusion electrodes of the transistors tr3 and tr6, The wiring length of the second component connecting the gate and the gate electrode group
The center of gravity g1 of the diffusion electrode of r6 and the transistors tr1 and tr
Distance d from the center of gravity g2 of the gate electrode of 2, tr4, tr5
2, and the wiring length of the third component connecting the gate electrodes is estimated by the distance d3 between the gate electrodes of the transistors tr1 and tr5.

A first metal layer is allocated to the first component connecting the diffusion electrodes and the second component connecting the diffusion electrode group and the gate electrode group, and the third component connecting the gate electrodes is formed.
Assuming that a polysilicon layer is assigned to the component
For example, in order to make a polysilicon wiring having a larger resistance than a metal wiring shorter, weighting is applied to the estimated value d3 of the third component and the estimated values d1 and d2 of the first and second components.
What is heavier than the sum may be used as an evaluation index for transistor arrangement. As described above, by adjusting the weighting of the estimated value of each component, the wiring shape can be finely controlled, so that it is possible to easily cope with gate alignment and the like.

(Second Embodiment) FIG. 13 is a flowchart showing a flow of processing of a transistor arrangement method according to a second embodiment of the present invention. The transistor arrangement method according to the present embodiment is similar to the first embodiment in the basic processing flow, and additionally uses circuit-like information in one-dimensional transistor arrangement. Is what you do.

The transistor arrangement method according to the present embodiment uses a circuit concept of “stage” in one-dimensional transistor arrangement. In MOS logic, since it is generally considered that a signal is transmitted from the drain of a transistor to the gate of another transistor, a signal path from each transistor to the output terminal of the transistor can be specified from a netlist. The path length from the transistor to the output terminal can be represented by the number of gates on this path.

Here, the number of gates on the path from the transistor to the output terminal is defined as a stage. FIG. 14 is a diagram showing the stages in the circuit shown in FIG. 4, and the numbers surrounded by squares indicate the values of the stages of the respective transistors. In FIG. 14, the stages of each transistor are as follows. Stage = 1: tp11, tp12, tn11, tn12 Stage = 2: tp8, tp9, tp10, tn8, tn9, tn10 Stage = 3: tp2, tp3, tp7, tn2, tn3, tn7 Stage = 4: tp4, tp5, tp6 , Tn4, tn5, tn6 stage = 5: tp0, tp1, tn0, tn1

In the transistor arrangement method according to the present embodiment, the stages shown in FIG. 14 are set for the circuit represented by the netlist input in step ST10 in step ST21. After setting the one-dimensional lattice space in step ST12, the one-dimensional lattice space is set.
The two-dimensional initial arrangement ST22 and the one-dimensional arrangement optimization ST23 using the stage are executed.

Since the stage expresses the distance to the output terminal of the transistor, it can be said that the stage is a useful concept for optimizing the wiring length. That is, if the input terminal of the cell is arranged on the left side and the output terminal is arranged on the right side, the transistor having a larger value stage is arranged closer to the left and the transistor having a smaller value stage is arranged closer to the right side. Are arranged along the signal flow, and as a result, the wiring can be optimized. However, since there are actually many transistors having the same stage, it is not possible to optimize the wiring only by grouping the stages and arranging them in order.

Therefore, in this embodiment, one-dimensional arrangement is performed as follows. First, in step ST22, an initial arrangement of the one-dimensional arrangement is performed. In the one-dimensional initial arrangement in step ST22, as described above, the transistors are arranged in the order of the stages set in step ST21. Then, in step ST23, the one-dimensional arrangement is optimized. At this time, the concept of the stage is used as follows. Taking the case where the input terminal of the cell is arranged on the left side of the cell and the output terminal is arranged on the right side of the cell as an example, in the sequential improvement of the arrangement, for one transistor arbitrarily selected, the stage of this one transistor The position of the leftmost one of the transistors having the stage value larger by 1 is set as the left limit of the movement destination, and the position of the rightmost one of the transistors having the stage value smaller by one than the stage of the one transistor is set. Is the right limit of the destination. By performing the optimization process effectively using the concept of the stage, the processing efficiency of the one-dimensional arrangement can be increased.

In this embodiment, the transistors represented by the input netlist may be grouped in the same manner as in the first embodiment.

(Third Embodiment) FIG. 15 is a flowchart showing a flow of processing of a transistor arrangement method according to a third embodiment of the present invention. The transistor arrangement method according to the present embodiment is different from the transistor arrangement method according to the first embodiment in that steps ST31 and ST3 are performed between the one-dimensional arrangement step and the two-dimensional arrangement step.
2 is obtained by adding a transistor folding step.

The transistor folding step is necessary when handling a transistor having a size larger than the cell height. In the present embodiment, by incorporating a transistor folding step between the one-dimensional arrangement step and the two-dimensional arrangement step, the gate folding processing of the transistor with higher precision than before is realized. In other words, the conventional gate turning process of a transistor is performed only based on a comparison between the cell height and the transistor size. However, in the present embodiment, the gate turning process of the transistor is performed after the one-dimensional arrangement is performed. According to the layout described above, the wiring density of the transistor can be considered. That is, from the transistor arrangement result in the one-dimensional arrangement step, the wiring density of the wiring horizontal component is obtained for each transistor arrangement position in the horizontal direction of the cell, and the sum of the transistor height and the wiring density of the wiring horizontal component at one transistor arrangement position is obtained. When the layout height of the cell exceeds the set value of the cell height, the transistor arranged at one transistor arrangement position is divided by gate folding, and the divided transistor is used as a new arrangement element.
Correct the transistor arrangement result in the dimension arrangement step. Since the wiring density in the one-dimensional arrangement result is considered in the gate turning processing of the transistor, the optimum number of folding steps can be determined according to the wiring density.

FIG. 16 is a view for explaining a transistor folding step according to the present embodiment.
FIG. 7B is a diagram illustrating a one-dimensional arrangement of transistors before the transistor folding process, and FIG. 7B is a diagram illustrating a result of executing a transistor folding process including steps ST31 and ST32 on the one-dimensional transistor configuration illustrated in FIG. FIGS. 16A and 16B show that the transistors trc,
trd, trg, and trh are folded back, respectively.
It can be seen that the entire one-dimensional arrangement of the transistors has been modified accordingly. In step ST31, the transistor is folded back, and in step ST32, the one-dimensional arrangement of the transistors is corrected, and then the two-dimensional arrangement step is performed as in the first embodiment, whereby the transistor arrangement can be optimized. .

(Fourth Embodiment) A fourth embodiment of the present invention relates to a transistor arranging method using a one-dimensional arrangement style, and optimizes diffusion and wiring based on an arrangement evaluation on a mask diagram. Are optimized together to derive an optimal arrangement result.

FIG. 17 is a flowchart showing the flow of processing of the transistor arrangement method according to the fourth embodiment of the present invention. First, in step ST41, a net list is input. More specifically, a netlist is read from a storage device of a computer or the like, and connection requests for transistors and input / output terminals of cells to be arranged described in the netlist and information on the size of each transistor are stored in the system. I do.

Next, in step ST42, transistors are grouped. Here, as in step S11 in the first embodiment, for the transistors in each channel region, when the diffusion electrodes form a simple series connection that does not include a branch, the transistors forming this series connection are Put them together in one group. Transistors that do not belong to any of the series connections are not grouped, and are regarded as independently forming a series connection in a broad sense, and each transistor is grouped by a single transistor.

After step ST43, step S42 is executed.
This is a step of optimizing the arrangement of the group by regarding the group formed in the above as an arrangement element whose internal arrangement is determined.

Step ST43 is a step of setting a one-dimensional grid space, that is, a grid point sequence arranged in the horizontal direction, for the cell. And step ST44 is step ST4
This is a step of initially arranging the transistors on the grid point sequence set in Step 3. FIG. 18 is a diagram showing an example of a transistor arrangement on a grid point sequence. At each lattice point 51, one P-type transistor 52 and one N-type transistor 53 can be arranged vertically, and at each lattice point, one or both of the P-channel region and the N-channel region are empty. It does not matter.

Here, the number of grid points arranged in step ST43 will be described. In general, when processing a placement problem using a grid model, the number of grid points to be prepared is usually set to a minimum necessary according to the number of layout elements. This means that even if the number of grid points is unnecessarily increased, only the solution space to be searched for optimization becomes large,
On the contrary, it was considered that the processing efficiency was lowered. In the case of the transistor arrangement as in the present embodiment,
The necessary minimum number of lattice points is the larger of the P-type transistor and the N-type transistor.

However, when the lattice point sequence is used in the transistor arrangement problem, the number of lattice points is 1 / l of the larger number of the P-type transistor and the N-type transistor.
An experimental result was obtained in which the processing efficiency was improved when the value was set to a value obtained by adding a margin of about three. It is considered that this is because the number of optimal solutions giving the optimal value also increased by increasing the number of lattice points. If the number of lattice points is excessively increased, the processing efficiency may be reduced. However, it is more effective to increase the number of lattice points to a certain extent to increase the processing efficiency.

Steps ST45 to ST50 are arrangement optimization processing for optimizing group arrangement by repetitive processing. The placement optimization processing according to the present invention determines the placement that minimizes the placement evaluation function by performing iterative placement improvement from the initial placement. Here, scheduling by the simulated annealing method (SA method) is implemented. However, other scheduling methods can be used.

Before describing the layout optimizing process, a brief description will be given of the relationship between the transistor layout and the group layout on the lattice point sequence. As described above, the arrangement of the transistors in the group is performed by arranging the transistors in series on the circuit. On the lattice point sequence, the transistor row is expressed by assigning it to continuous lattice points. In this case, for example, the transistors in the group shown in FIG. 19A can be arranged in two ways on the grid point sequence as shown in FIG. Street arrangement becomes possible. This can be considered that the group has a degree of freedom of inversion. In the group arrangement optimization processing, the degree of freedom of inversion of each group is also considered.

Step ST45 is a process of converting the transistor arrangement on the lattice point sequence into a transistor arrangement on a mask diagram satisfying the mask design rule. Ultimately, what we want to optimize is the transistor arrangement on the mask diagram that reflects the mask design rules, so it is necessary to convert the arrangement on the grid point array to the arrangement on the mask diagram in order to effectively evaluate the arrangement. There is.

FIG. 20 is a diagram showing an example of data representing the arrangement on the grid point sequence. In the figure, x is a lattice point, tr na
me is a transistor identification symbol, L mnet is the net number of the diffusion electrode on the left side of the transistor, G mnet is the net number of the gate electrode of the transistor, R mnet
Represents the net number of the diffusion electrode on the right side of the transistor. Mssc represents a group identification number, and transistors belonging to the same group have the same value. Note that * indicates that no transistor is arranged at that lattice point.

It is not obvious how to convert an arrangement on a grid point sequence as shown in FIG. 20 to an arrangement on a mask diagram. The simplest method of converting the arrangement on the grid point sequence into the arrangement on the mask diagram is to pack transistors in order from the left independently in each channel region. That is, this is a method in which the arrangement position of the transistor on the mask diagram is determined based only on the relationship with the transistor on the left of the same channel region. FIG. 21 is a diagram showing an arrangement on a mask diagram obtained by converting the arrangement on the grid point sequence shown in FIG. 20 by such a conversion method. In the figure, the gap 81 indicates that the diffusion islands are separated because the diffusion electrodes facing each other have different potentials. On the other hand, the gap 82 indicates that the diffusion electrodes facing each other have the same potential, but there are other electrodes having the same potential, so that a diffusion contact is made there.
It indicates that it is connected as a diffusion island. A portion 83 having no gap between the transistors represents a series connection of diffusion without branching, and it can be seen that the transistors are arranged as one group. As described above, even with a simple left-justified conversion method, the configuration of the diffusion island of each channel region can be correctly expressed. However, the diversity expressed by the arrangement on the grid point sequence is lost, for example, the interval between the diffusion islands always becomes equal to the minimum rule, and is not suitable as a conversion for the arrangement evaluation.

As another simple conversion method, there is a method in which a P-type transistor and an N-type transistor arranged at the same lattice point are arranged on a mask diagram with their gates being centered. When arranging a transistor in one channel region, if the transistor is not arranged at the same lattice point as the transistor in the other channel region, the arrangement may be determined based on a relationship with an adjacent transistor of the same channel. . Although this method has been widely used in the past, it has a drawback that a diffused island cannot be correctly represented when the diffusion-related mask design rule is complicated. That is, for example, when adjacent transistors share a diffusion electrode, there is actually a rule that the gate interval between the adjacent transistors differs depending on whether or not a diffusion contact is necessary for the shared diffusion electrode. According to this method of aligning and arranging, it is not possible to correctly represent a diffusion island adapted to such a rule.

In the present embodiment, the following conversion method is used in order to arrange the inside of the diffusion island at the minimum size according to the mask design rule and to arrange between the diffusion islands at intervals reflecting the arrangement on the grid point sequence.

FIGS. 22 and 23 are flowcharts showing the processing flow of the method for converting the arrangement on the grid point sequence to the arrangement on the mask diagram according to the present embodiment, and FIG. 22 is a diagram showing the basic processing flow. FIG. 23 is a diagram showing a process (LtoR) of determining a position while tracing a transistor from left to right in one channel region. This method basically determines the position of the transistor in order from left to right.However, the process of determining the position while tracing the transistor from left to right in one channel region is performed in the other channel region. This is a method of stopping halfway in relation to the transistor arrangement state, moving the channel region and performing the same processing, and thereafter repeating this. Of course, the positions of the transistors may be determined from right to left.

Taking the case where the arrangement on the grid point points shown in FIG. 18 is converted to the arrangement on the mask figure as an example, the arrangement on the grid point rows according to the present embodiment is changed to the arrangement on the mask figure according to the flowcharts of FIGS. Will be described. First, in step SA1, the P-type transistor P1 is specified as the leftmost transistor, and in step SA2, the position of the P-type transistor P1 is set to the origin on the mask diagram. In step SA3, the search position is adjusted to the lattice position of the leftmost transistor in both channel regions. That is, the search position is set to grid point 0 in both the P channel region and the N channel region. Next, at step SA4, the leftmost transistor (P-type transistor P1)
Is moved to the next grid point in the channel region of P, that is, the P channel region. As a result, the search position of the P channel region becomes the lattice point 1.

Next, in step SA5, the LtoR process is performed in the channel region of the leftmost transistor (P-type transistor P1), that is, in the P channel region (FIG. 23). First, in step SB1, it is determined whether there is a transistor at the search position. Since there is a P-type transistor P2 at the lattice point 1, the process proceeds to Step SB2. Since the P-type transistor P2 is the first transistor in the present LtoR processing in step SB2,
Proceed to 3. In step SB3, there is no N-type transistor whose position has been determined at the lattice point 1 (N-type transistor N
2 The position on the mask diagram has not been determined yet)
Proceeding to step SB4, the position on the mask diagram of the P-type transistor P2 is determined from the relationship with the rightmost position-determined transistor, regardless of whether it is P-type or N-type. That is, the position of the P-type transistor P2 on the mask diagram is determined based on the position of the P-type transistor P1, which is the only transistor whose position has been determined.

In step SB9, the search position is moved to the next right grid point, ie, grid point 2, and the process returns to step SB1. Since there is no P-type transistor at lattice point 2, the process proceeds to step SB7. In step SB7, since the N-type transistor N3 exists at the lattice point 2, the process proceeds to step SB8. In step SB8, the lattice point 2, which is the search position of the P-channel region, is to the right of the lattice point 0, which is the search position of the N-channel region. Since there is, the LtoR processing ends.

At step SA6, since the positions of all the transistors have not been determined yet, the process proceeds to step SA7, where lattice point 0 is set as a search position in the N-channel region which does not belong to the leftmost transistor (P-type transistor P1). Perform LtoR processing. At the lattice point 0, there is an N-type transistor N1 (step SB
1) Since the N-type transistor N1 is the first transistor in the present LtoR processing (step SB2), the process proceeds to step SB3. Since there is a P-type transistor P1 whose position has been determined at the lattice point 0 in step SB3, the process proceeds to step SB5, where the N-type transistor N1 is set at the position of the P-type transistor P1 (the transistor is located on the left of the N-type transistor N1). No), the process proceeds to step SB9.

In step SB9, the search position is moved to the next grid point, that is, grid point 1, and the process returns to step SB1. There is an N-type transistor N2 at lattice point 1 (step SB1), and since the N-type transistor N2 is not the first transistor in the present LtoR process (step SB2), the process proceeds to step SB6. In step SB6, 1
The position of the N-type transistor N2 is determined based on the position of the transistor whose position is determined immediately before, that is, the N-type transistor N1. Similarly, the position of the N-type transistor N3 is determined based on the position of the N-type transistor N2,
The position of N-type transistor N4 is determined based on the position of N-type transistor N3.

In step SB9, the search position is moved to grid point 4, and the process returns to step SB1. Since there is no N-type transistor at the lattice point 4, the process proceeds to Step SB7. In step SB7, since the lattice point 4 includes the P-type transistor P4 at the lattice point 4, the process proceeds to step SB8. In step SB8, the lattice point 4 which is the search position of the N-channel region is located to the right of the lattice point 2 which is the search position of the P-channel region. Because there is
The LtoR process ends.

In step SA8, since the positions of all the transistors have not been determined yet, the flow returns to step SA5, and the LtoR process is executed with the lattice point 2 as the search position in the P-channel region. Since there is no P-type transistor at lattice point 2 (step SB1) and there is an N-type transistor (step SB7), the process proceeds to step SB8. At step SB8, lattice point 2, which is the search position of the P-channel region, is the search position of the N-channel region. Is not to the right of the grid point 4, the process proceeds to step SB 9, and the search position is set to 1
Move to the next grid point, ie, grid point 3, and go to step SB
Return to 1. There is a P-type transistor P3 at lattice point 3 (step SB1), and the P-type transistor P3 is the first transistor in the present LtoR process (step SB2).
Therefore, the process proceeds to Step SB3. Since the lattice point 3 includes the N-type transistor N4 whose position has been determined (step SB3), the position of the N-type transistor N4 is compared with the position determined from the relationship between the P-type transistor P3 and the P-type transistor P2 in step SB5. And P on the right
The position of the type transistor P3 is determined.

In step SB9, the search position is moved to the next grid point, that is, grid point 4, and the process returns to step SB1. At lattice point 4, there is a P-type transistor P4 (step SB1), and this P-type transistor P4 is not the first transistor in the present LtoR processing (step SB1).
2) Therefore, the process proceeds to Step SB6. In step SB6, the P-type transistor P based on the position of the transistor previously determined, ie, the P-type transistor P3
4 is determined. Hereinafter, similarly, the P-type transistor P
Positions 5 to P9 are determined.

In step SA6, since the positions of all the transistors have not been determined yet, the flow advances to step SA7 to execute LtoR processing with the lattice point 4 as a search position in the N-channel region. In this LtoR processing, N
The position of the type transistor N5 is determined based on the position of the P-type transistor P5 and the position determined from the relationship between the N-type transistor N4 and the N-type transistor N5. Also N
The type transistors N6 to N13 are determined based on the positions of the N-type transistors located on the left side, respectively. Similarly, in the LtoR process executed with the lattice point 10 as a search position in the P-channel region, the P-type transistor P
10 is determined based on the position of the N-type transistor N11 and the position determined from the relationship between the P-type transistor P9 and the P-type transistor P10.
Each of 11 to 13 is determined based on the position of the P-type transistor located on the left side.

As described above, the method of converting the arrangement on the lattice point sequence to the arrangement on the mask diagram according to the present embodiment is based on the diffusion-related minimum while tracing the transistor from left to right in one channel region. In accordance with the rule, when a process of moving from the left to the right in the channel region is newly started, only the first transistor is referred to the position of the transistor in the opposite channel region. In other words, the arrangement position of one transistor on the mask diagram is the mask diagram of this transistor when the transistor is arranged at the lattice point on the left side of the one transistor in the same channel region as the one transistor. On the other hand, when the transistor is determined based on the above arrangement position, but is not arranged, the transistor is arranged at the same lattice point position as the one transistor in a channel region different from the one transistor, and a mask diagram of this transistor When the upper position is already determined, it is determined based on the position of the transistor on the mask diagram. As a result, it is possible to relatively faithfully reflect the arrangement on the lattice point sequence on the mask diagram, and a great effect can be obtained in optimizing the transistor arrangement on the mask diagram.

FIG. 24 shows an example of such a conversion method.
FIG. 9 is a diagram showing an arrangement on a mask diagram obtained by converting an arrangement on a grid point sequence shown in FIG. In FIG. 21, all the diffusion islands in the N-channel region have been shifted to the left. However, in FIG. 24, this point has been corrected, and it can be seen that the interval 101 is larger than the interval based on the mask design rule. .

Step ST46 is a step of evaluating the arrangement on the mask diagram. In order to simultaneously realize the reduction of the cell width and the reduction of the cell height to obtain the optimum cell layout, it is necessary to simultaneously optimize the diffusion island and the wiring. The key to realizing such optimization is a placement evaluation method including the definition of a placement evaluation function.

The arrangement evaluation method according to the present embodiment will be described. First, the placement is evaluated based on the spread of the net. The net to be evaluated satisfies the following two conditions.

A signal net (neither a power supply net nor a ground net). A net extending between groups. In the conventional transistor arrangement method, a net representing the connection between the electrodes of the transistors is defined between the groups. Often re-expressed as a connection. In that case, since the actual electrode position on the mask diagram is not reflected, the wiring shape is not accurately evaluated. The evaluation of the wiring in the present embodiment is to evaluate the wiring on the mask diagram by directly using the positions of the transistor electrodes.

An electrode forming a transistor-level net is a diffusion electrode (source or drain) of the transistor.
And a transistor gate electrode. Transistors are classified into two types, P-type and N-type. Here, the electrodes constituting the net are divided into three electrode groups: a P-type diffusion electrode (a diffusion electrode of a P-type transistor), an N-type diffusion electrode (a diffusion electrode of an N-type transistor), and a gate electrode group. Consider four spreads for each net. That is, (a) the spread of the P-type diffusion electrode group, (b) the spread of the N-type diffusion electrode group, (c) the spread of the gate electrode group, and (d) the spread of the entire electrode group. In the present embodiment, the arrangement of the transistors is considered in a horizontal one-dimensional arrangement style, so that only the horizontal spread is evaluated for the spread of the net. The spread of the P-type diffusion electrode group is estimated by the distance between the leftmost P-type diffusion electrode and the rightmost P-type diffusion electrode in the net, and the N-type is similarly estimated. The spread of the gate electrode group is also estimated by the distance between the leftmost and rightmost gate electrodes in the net, and the spread of the entire electrode group is determined by the distance between the leftmost and rightmost electrodes of the net regardless of the type of electrode. Estimate by FIG. 25 is a diagram showing the spread of four nets. In FIG. 25, reference numeral 113 denotes the spread of the P-type diffusion electrode group;
Reference numeral 4 denotes the extension of the N-type diffusion electrode group, 115 denotes the extension of the gate electrode group, and 116 denotes the extension of the entire electrode group.

Here, an arrangement evaluation function S is defined. The value of the net spread used for the placement evaluation function S is a value calculated from the electrode position based on the transistor position estimation described above. The spread of the P-type diffusion electrode group of each net is A,
When the spread of the N-type diffusion electrode group of each net is B, the spread of the gate electrode group of each net is C, and the spread of all the electrode groups of each net is D, S = Ｓ _net (w1 * A + w2 * B + w3 * C + w4 *) D) Here, w1, w2, w3, and w4 are weight constants.

Now, the weight constants are defined as w1 = w2 = w3 = 0,
If w4 = 1.0 is set, an evaluation function equivalent to that used for normal wiring length evaluation is obtained. On the other hand, in the present embodiment, the weighting constants w1, w2, and w3 are set to certain positive numbers, but this aim will be described.

First, the reason why the diffusion can be optimized by evaluating the spread of the wiring must be basically explained. This is because the wiring is evaluated by the arrangement on the mask diagram. If the diffusion sharing is advanced and the diffusion separation part is reduced, the channel width can be reduced in a mask manner. Therefore, although the cell width is reduced, it can be strongly expected that if the cell width is reduced, the sum of the spreads of the nets, that is, the value of D in the arrangement evaluation function S becomes smaller. That is, as long as the net spread is accurately evaluated, it is considered that the minimization of the net spread D and the optimization of the diffusion are correlated to some extent.

If the diffusion electrodes are to be further actively shared, the above-mentioned net spreads A and B may be added to the arrangement evaluation function. If two diffusion electrodes can be shared, the spread of the diffusion electrodes in the channel A,
This is because the value of B should be greatly reduced. In addition, since only the signal net is evaluated here, reducing the spread of the diffusion electrode and promoting the sharing of the diffusion electrode leads to a reduction in the drain capacitance.
Adding the net spreads A and B to the placement evaluation function also takes into account the reduction in drain capacitance. As described above, the above-described placement evaluation function S is an evaluation function capable of indirectly optimizing diffusion while directly optimizing wiring. Finally, the term C in the placement evaluation function S is added with consideration to promote gate alignment. Rather than performing grouping based on the extraction of partial circuits as in the past and forcibly guaranteeing gate alignment by arrangement within a group, the grouping and arrangement evaluation function according to the present invention adapts to the transistor arrangement of the entire cell. However, the gate alignment can be more flexibly realized.

Step ST50 is a step of changing the arrangement. Conventionally, in most cases, a change in the arrangement of the transistors has a constraint that some kind of coupling relationship is provided between the P-type transistor and the N-type transistor, and the coupled transistors must always operate at the same time. However, the transistor arrangement method according to the present embodiment intends to optimize the arrangement of all transistors by the arrangement evaluation function without previously setting the coupling relationship between the P-type transistor and the N-type transistor. The feature of this step ST50 is that the arrangement change of each time is limited to the group arrangement change in one channel.

As described above, the transistor arrangement method according to the present embodiment optimizes the arrangement on the mask diagram based on the mask design rule, and indirectly optimizes the diffusion while optimizing the wiring. Can also proceed. Since the grouping process for improving the processing efficiency is limited to the minimum grouping of grouping serial connections without branches, the applicable range of cells is wide.

FIGS. 26 and 27 are diagrams showing the result of executing the transistor arrangement method according to the present embodiment on the circuit shown in FIG. 4, and FIG. 26 is a diagram showing data representing the arrangement on the lattice point sequence. FIG. 27 is a diagram showing a transistor arrangement on a mask diagram. In this case, the processing time of the computer is about 5 minutes, which indicates that the transistor arrangement method according to this embodiment is sufficiently practical.

[0129]

As described above, according to the present invention, 1
By combining two-dimensional and two-dimensional placement, and by using circuit concepts for placement optimization,
In layout synthesis of standard cells, it is possible to obtain an optimal transistor arrangement in a practical time, which is equal to that of a human.

Further, according to the present invention, in the one-dimensional transistor layout style, optimization of diffusion and optimization of wiring are simultaneously performed, thereby providing a transistor layout with a high integration degree in a practical time in cell layout synthesis. can do.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a flow of processing of a cell layout synthesis (cell synthesis) method.

FIG. 2 is a diagram showing a cell model targeted by a transistor arrangement method according to the present invention.

FIG. 3 is a flowchart illustrating a process flow of a transistor arrangement method according to the first embodiment of the present invention.

FIG. 4 is a circuit schematic diagram showing an example of a circuit represented by a netlist.

FIG. 5 is a diagram showing a result of executing a group forming process according to the present invention on the circuit of FIG. 4;

6A and 6B are diagrams for explaining transistor arrangement in a group formed by a group formation process according to the present invention, wherein FIG. 6A is a diagram illustrating transistors belonging to one group, and FIG. Layout.

FIG. 7 is a diagram showing a one-dimensional lattice space and a one-dimensional transistor placement model, which corresponds to the circuit shown in FIG. 5;

8 is a diagram illustrating a result of mapping the one-dimensional transistor arrangement results illustrated in FIG. 7 into a two-dimensional lattice space.

FIG. 9 is a diagram showing a two-dimensional transistor arrangement in a process of executing a two-dimensional transistor arrangement optimizing process;

FIG. 10 is a diagram showing an execution result of a transistor two-dimensional arrangement optimization process.

11A is an example of a mask pattern, and FIG. 11B is an arrangement in a two-dimensional lattice space corresponding to the mask pattern shown in FIG.

FIG. 12 is a diagram illustrating an example of a typical wiring structure, and is a diagram for describing evaluation of a wiring length according to the present invention.

FIG. 13 is a flowchart illustrating a process flow of a transistor arrangement method according to the second embodiment of the present invention.

FIG. 14 is a diagram for explaining the concept of a stage, and is a diagram showing a stage in the circuit shown in FIG. 4;

FIG. 15 is a flowchart illustrating a process flow of a transistor arrangement method according to a third embodiment of the present invention.

FIG. 16 is a diagram for explaining a gate turn-back process of the transistor according to the third embodiment of the present invention;
FIG. 7A is a diagram illustrating the one-dimensional transistor arrangement before the gate folding process, and FIG. 7B is a diagram illustrating the result of performing the gate folding process on the one-dimensional transistor configuration illustrated in FIG.

FIG. 17 is a flowchart showing a process flow of a transistor arrangement method according to a fourth embodiment of the present invention.

FIG. 18 is a diagram showing an example of a transistor arrangement on a grid point sequence.

19A and 19B are diagrams showing that a group formed by the group forming process according to the present invention has a degree of freedom of inversion, wherein FIG. 19A shows transistors belonging to one group, and FIG. FIG. 4 is a diagram showing two types of arrangements of the transistors of the group shown in FIG.

FIG. 20 is a diagram showing an example of data representing an arrangement on a grid point sequence.

FIG. 21 is a diagram showing a result of converting an arrangement on the grid point sequence shown in FIG. 20 into an arrangement on a mask diagram by a conventional conversion method.

FIG. 22 is a flowchart showing a basic processing flow of a method of converting an arrangement on a grid point sequence to an arrangement on a mask diagram according to the present invention.

FIG. 23 is a flowchart showing a process (LtoR) of determining a position while tracing a transistor from left to right in one channel region in a method of converting an arrangement on a grid point sequence to an arrangement on a mask diagram according to the present invention. is there.

FIG. 24 is a diagram showing a result of converting the arrangement on the grid point sequence shown in FIG. 20 into the arrangement on the mask diagram by the conversion method according to the present invention.

FIG. 25 is a diagram showing a net spread used in the placement evaluation according to the present invention.

FIG. 26 is a diagram showing an arrangement on a grid point sequence as a result of executing the transistor arrangement method according to the fourth embodiment of the present invention on the circuit shown in FIG. 4;

FIG. 27 is a diagram showing a transistor arrangement on a mask diagram obtained as a result of executing the transistor arrangement method according to the fourth embodiment of the present invention on the circuit shown in FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Netlist 6 P-type transistor 7 N-type transistor 8 P-channel region 9 N-channel region 15 Group 51 Lattice point 52 P-type transistor 53 N-type transistor 113 Expansion of P-type diffusion electrode group 114 Expansion of N-type diffusion electrode group 115 Gate Spread of electrode group 116 Spread of all electrode group

Claims (14)

(57) [Claims] 1. A method for arranging transistors in a cell region, based on a netlist describing connection information of transistors in a cell and size information of each transistor, for a cell having at least one transistor. When the height of the cell in the vertical direction is set to a predetermined value and the width of the cell in the horizontal direction is variable, the cell region is vertically divided into a P-channel region and an N-channel region. Based on the list, the cell has P
Type transistors are arranged vertically in a row in the left and right direction of the cell with the vertical direction of the cell and the gate width direction aligned in the P channel region, and the N type transistors of the cell are arranged vertically in the N channel region. A one-dimensional arranging step of arranging the cells in one column in the left-right direction of the cell;
In each channel region, the transistors can be arranged in a plurality of columns in the left-right direction of the cell, and the transistors can be arranged in a horizontal state where the left-right direction of the cell and the gate width direction are aligned, and the cell width is reduced. And a two-dimensional arrangement step of changing the arrangement of the transistors. 2. The transistor arrangement method according to claim 1, wherein transistors of the same conductivity type in which the diffusion electrodes form a serial connection that does not include a branch are extracted from the netlist, and the extracted transistors are identified as one transistor. A group forming step of grouping the transistors, wherein the one-dimensional arrangement step and the two-dimensional arrangement step perform the transistor arrangement by using the transistors grouped in one group in the group formation step as a single arrangement element; Transistor placement method. 3. The transistor arrangement method according to claim 1, wherein the one-dimensional arrangement step and the two-dimensional arrangement step arrange the transistors using an evaluation index based on an estimated value of a wiring length in the cell. Transistor arrangement method. 4. The transistor arrangement method according to claim 3, wherein in the one-dimensional arrangement step and the two-dimensional arrangement step, the wiring of each net is divided into a plurality of components based on the positioning in the net, and the wiring is performed for each of the divided components. A transistor arrangement method comprising estimating a length and adding a weighted value to an estimated value of a wiring length of each component as an evaluation index for transistor arrangement. 5. The transistor arranging method according to claim 4, wherein the one-dimensional arranging step and the two-dimensional arranging step divide a wiring of each net into a component to be assigned to a polysilicon layer and a component to be assigned to a metal layer. A transistor arrangement method characterized in that a value obtained by adding different weights to an estimated value of a wiring length of a component to be assigned to a layer and an estimated value of a wiring length of a component to be assigned to a metal layer is used as an evaluation index for transistor placement. . 6. The transistor arrangement method according to claim 1, wherein the cell is a MOS logic cell, and a gate on a path from the transistor to a signal output terminal to which the transistor belongs for each transistor based on a netlist. A stage setting step of setting the number of stages, wherein the one-dimensional arrangement step uses the stages of the transistors set in the stage setting step to determine an arrangement order of the transistors. Placement method. 7. The transistor arrangement method according to claim 1, wherein a wiring density of a horizontal wiring component is determined for each transistor arrangement position in the horizontal direction of the cell from the transistor arrangement result in the one-dimensional arrangement step, and one transistor arrangement is performed. When the layout height, which is the sum of the transistor height at the position and the wiring density of the wiring horizontal component, exceeds the set value of the cell height, the transistor arranged at the one transistor arrangement position is divided by gate folding and divided. A transistor arrangement method, comprising: a transistor folding step of correcting a transistor arrangement result in the one-dimensional arrangement step using a transistor as a new arrangement element. 8. A method for arranging transistors in a cell region, based on a netlist describing connection information of transistors in the cell, for a cell having at least one transistor, comprising: Is divided into a plurality of components based on the position in the net, a wiring length is estimated for each of the divided components, and a value obtained by adding the weighted value to the estimated value of the wiring length of each component as an evaluation index is used as an evaluation index. A method of arranging transistors, wherein the arrangement is determined. 9. The transistor arrangement method according to claim 8 , wherein the wiring of each net is divided into a component to be allocated to a polysilicon layer and a component to be allocated to a metal layer. A transistor arrangement method characterized in that a transistor arrangement is determined by using, as an evaluation index, a sum of values obtained by assigning different weights to an estimated value of a wiring length of a component to be assigned to a layer. 10. A transistor arranging method for deciding an arrangement of each transistor in a cell region on the basis of a net list describing connection information of a transistor in a MOS logic cell having at least one transistor, the method comprising: A stage setting step of setting, for each transistor, a stage which is the number of gates on a path from the transistor to a signal output terminal to which the transistor is based on the list; and a transistor included in a cell based on the netlist. And arranging the transistors in columns in a cell region, wherein the arranging step uses the stages of the respective transistors set in the stage setting step to determine an arrangement order of the transistors. . 11. A transistor arrangement for determining a transistor arrangement in a cell region for a cell having at least one transistor, based on a netlist describing connection information of the transistor in the cell and a mask design rule derived from a semiconductor manufacturing technique. A plurality of grid points are arranged in the lateral direction of the cell to set a grid point row, and a P-channel region for arranging a P-type transistor and an N-channel area for arranging an N-type transistor are arranged in parallel with the grid point row. Based on the netlist, P-type transistors included in the cell are arranged one by one at grid points in the P-channel region, and N-type transistors included in the cell are allocated one in the N-channel region. By arranging one for each grid point position A first step of forming a transistor arrangement on the lattice point sequence, and satisfying the mask design rule in order from one side in the horizontal direction of the cell to the other side in each channel region based on the transistor arrangement on the lattice point line A second step of arranging transistors on the mask diagram to form a transistor arrangement on the mask diagram from the transistor arrangement on the lattice point sequence; and a transistor arrangement on the mask diagram formed in the second step. And a third step of changing the transistor arrangement in the transistor arrangement on the lattice point sequence based on the evaluated transistor arrangement on the mask diagram based on the evaluation result, wherein the second and third steps are performed. Is repeated, and in the second step, at the beginning of the repetition, the transistor arrangement on the grid point sequence formed in the first step is performed. While the transistor arrangement on the mask diagram is formed from the
Forming a transistor arrangement on a mask diagram from a transistor arrangement on a lattice point sequence in which the arrangement of the transistors is changed in the step (b). 12. The transistor arrangement method according to claim 11 , wherein, in the second step, an arrangement position of one transistor on a mask diagram is set to one of the one transistors in the same channel region as the one transistor. When a transistor is arranged at a lattice point position from one side, it is determined based on the arrangement position on the mask diagram of this transistor, while when it is not arranged, the transistor is arranged in a channel region different from the one transistor. When a transistor is arranged at the same grid point position as one transistor and the arrangement position of this transistor on the mask diagram has already been determined, it is necessary to determine the transistor based on the arrangement position of this transistor on the mask diagram. Characteristic transistor arrangement method. 13. The method for arranging transistors according to claim 11 , wherein the third step estimates a spread of each net on a mask diagram by dividing the spread of each net into a plurality based on the electrodes of the transistors constituting the net.
A transistor arrangement method comprising: evaluating a transistor arrangement on a mask diagram by using, as an evaluation index, a sum of weighted values of estimated values of respective spreads. 14. The transistor arrangement method according to claim 13 , wherein the third step includes: expanding a net on a mask diagram by expanding a diffusion electrode of a P-type transistor; Estimating the spread of the gate electrode and the spread of all electrodes separately and evaluating the transistor arrangement on the mask diagram using the sum of the weighted values and the estimated value of each spread as the evaluation index A transistor arrangement method characterized by the above-mentioned.