JP3219324B2 - Sense amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier included in a reading section for reading data from a data storage section provided in an integrated circuit.

[0002]

2. Description of the Related Art As shown in FIG. 16, in an integrated circuit in which a logic circuit section and a memory circuit section 50 are provided in the same chip, the memory circuit section 50 is, as shown in FIG. An input unit to which address data specifying a memory transistor from which stored data is to be read is supplied; a decoder unit for creating X and Y-direction data for specifying a memory transistor based on the address data; and a storage unit read from a memory array unit. A selection section 52 for selecting based on an output signal of the decoder section;
Amplifier 5 for detecting the potential of the data sent from
3, and an output unit 54 for sending data sent by the sense amplifier 53 to the outside of the memory circuit. The circuit of the memory array 51 has a well-known configuration as shown in FIG. 19, and the circuit of the selection section 52 has a well-known configuration as shown in FIG. Further, the memory array unit 51 and the selection unit 52 are referred to as semiconductor memory means 600.

The above-mentioned sense amplifier 53 is conventionally configured as shown in FIG. In FIG. 18, the same components as those shown in FIG. 17 are denoted by the same reference numerals. The input side of the sense amplifier 53 to which the selection unit 52 is connected includes the source sides of N-channel MOS (hereinafter referred to as NMOS) transistors 63 and 64 and the inverter 61.
Of the inverter 61 is connected to the input side of the NMO.
Connected to the gates of S transistors 63 and 64. N
The drain side of the MOS transistor 63 is connected in series to the drain side of a P-channel MOS (hereinafter referred to as PMOS) transistor 65 to which a signal φp described later is supplied to the gate and the source side is connected to a positive power supply. Also, NMOS
A PMOS transistor 6 having a gate grounded and a source connected to a positive power supply is provided on the drain side of the transistor 64.
6 are connected in series.

An NMOS transistor 67 is provided between the output side of the inverter 61 and the input side of the sense amplifier 53 for direct negative feedback of the inverter 61 for the purpose of removing positive direction noise applied to the sense amplifier 53. And 68 are connected in series. The gate of the NMOS transistor 67 is connected to a connection point between the PMOS transistor 66 and the NMOS transistor 64, and the gate of the NMOS transistor 68 is supplied with the signal of φp.
A connection point between the PMOS transistor 66 and the NMOS transistor 64 is connected to an input side of the output unit 54 via an inverter 69.

[0005]

The operation of the above-configured sense amplifier will be described below. Selector 5
2 is first supplied to the inverter 61, the signal level of which is inverted, and the NMOS transistor 64
Of the NMOS transistor 6
4 on / off control. That is, the inverter 61 acts to maintain the input-side potential of the detection amplifier 53 near the inverted potential level of the inverter 61. For example, if the selected memory transistor in the memory array unit 51 is in a high resistance or off state, the detection amplifier 53
Is higher than the inverted potential, the signal level supplied to the gate of the NMOS transistor 64 changes due to the action of the inverter 61, and the NMOS transistor 64 is turned off. Therefore, the sense amplifier 5
3 is connected to the positive power supply via the PMOS transistor 66 which is always on, so that the input side of the inverter 69 is high.
(H) level, and the output side of the detection amplifier 53 changes to low (L) level by the action of the inverter 69.

On the other hand, when the memory transistor is in a low resistance or on state, the NMOS transistor 64 is kept on by the action of the inverter 61.
The input side of the inverter 69 is connected to a PMOS transistor 66.
And a relatively low level of potential determined by the current flowing through the memory transistor and the ON current of the memory transistor. in this case,
The input side of the sense amplifier 53 is connected to a PMOS transistor 66.
Depending on the on-resistance value of the inverter 61, the above-mentioned potential cannot be maintained and the potential may be lower than the inversion potential of the inverter 61. After such a state, if the next selected memory transistor is in a high resistance or off state, the sense amplifier 53 is reset until the input side potential of the sense amplifier 53 recovers.
Does not work properly. That is, the NMOS transistor 6
4 does not go off. The time required for this recovery is P
The resistance value is determined by the on-resistance value of the MOS transistor 66. Usually, this resistance value is set to a considerably large value for the purpose of generating a sufficient potential difference with a not so large on-state current of the memory transistor. Therefore, there is a disadvantage that the above recovery requires a long time.

In order to solve this drawback, a PMOS transistor 65 whose operation is controlled by using a clock signal φp and inputting the clock signal φp to the gate,
The inverter 6 connected in series to the OS transistor 65
And an NMOS transistor 63 to which an output potential of 1 is applied to the gate.
By setting the on-resistance value of the S transistor 63 to a relatively low value, the input-side potential of the detection amplifier 53 is quickly recovered. However, in the sense amplifier 53 thus configured, during the period when the clock signal φp is at the L level, the current is bypassed by the PMOS transistor 65 and the NMOS transistor 63 in addition to the ON current of the memory transistor on the input side of the inverter 69. Therefore, there is a first problem that the input side potential of the inverter 69 cannot show a normal potential, and the detection amplifier 53 does not operate normally. Therefore, the access time cannot be shortened more than a certain amount regardless of the presence or absence of a solution having a long recovery time.

Further, there is a second problem that a sufficient L potential may not be supplied to the inverter 69 depending on the variation of the ON resistance value of the PMOS transistor 66 and the variation of the ON current of the memory transistor.

In order to remove positive noise applied to the sense amplifier 53, NMOS transistors 67 and 68 are provided for direct negative feedback of the inverter 61. As described above, since the inverter 61 that applies the negative feedback does not operate normally with respect to the NMOS transistor 64, the clock signal φp is separately supplied to the gate of the NMOS transistor 68 to control the operation of the NMOS transistor 68. ing. Further, since it is considered that the positive direction noise is normally input only when the selected memory transistor is in a high resistance or off state, the fact that the input of the inverter 69 is at the H level in such a state is used to make use of the NMOS transistor 67. Is connected to the input side of the inverter 69. Thus, when the memory transistor is high resistance or off, and when the clock signal φp is at the H level, the input and output of the inverter 61 are short-circuited, and the input of the detection amplifier 53 temporarily has a low resistance value, noise is absorbed, and the inverter 61 To maintain the inversion potential of. In this case, as described above, there is a third problem that the sense amplifier 53 cannot operate normally. Also, it takes a long time to recover this potential,
The access time cannot be made faster than a certain value.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and maintains the access time to the memory transistor in a short state, and further improves the current-to-voltage amplification factor to improve the detection accuracy. It is an object of the present invention to provide a sense amplifier that performs a reliable operation.

[0011]

According to the present invention, there is provided a first transistor having a low on-resistance and connected in series to a first positive power supply between a first positive power supply and a semiconductor memory means. A second transistor connected in series to the first transistor between the first transistor and the semiconductor memory means and connected to a negative feedback circuit having a first inverting element; a second positive power supply and a sense amplifier output unit; A third transistor which is connected in series to the second positive power supply and has a current mirror structure with the first transistor.

When the output of the sense amplifier is connected to the output of the third transistor, and the first and third transistors have a current mirror structure, the current flowing through the third transistor and the current flowing through the first transistor are different. Make the value proportional. Therefore, since the potential of the contact portion between the first transistor and the second transistor is not directly related to the output signal of the detection amplifier, the current mirror structure of the first transistor and the third transistor requires the on-resistance of the first transistor. The value can be set low, and the resistance value of the negative feedback circuit of the first inversion element can be reduced. Therefore, the above configuration enables the potential of the input terminal of the sense amplifier to be set to be constant in a short time, and acts to shorten the access time to the memory transistor.

Further, the present invention has a fourth transistor in which an output signal of the first inverting element is supplied to a gate of a second inverting element, and wherein a sense amplifier is provided between the second transistor and the semiconductor memory means. There may be provided a noise removing means for preventing a rise in the potential of the detection amplifier input section caused by noise inputted to the input section.

The noise elimination means operates to detect a rise in the potential of the sense amplifier input section due to noise input to the sense amplifier input section and suppress the rise in the potential. Therefore, having the noise removing means
The value of the current flowing through the first transistor, that is, the third transistor is stabilized, and acts to stabilize the output signal level of the sense amplifier.

Further, according to the present invention, the third positive power supply is connected in series between the third positive power supply and the dummy semiconductor memory means,
A fifth transistor having a low on-resistance value;
A sixth transistor connected in series with the fifth transistor between the transistor and the dummy semiconductor memory means and connected to a negative feedback circuit having a third inverting element;
A seventh transistor connected in series to a positive power supply and forming a current mirror structure with the fifth transistor, and an eighth transistor whose output signal from the third inversion element is supplied to a gate via a fourth inversion element; Noise removing means for preventing a potential rise of the input section caused by noise inputted to an input section between the sixth transistor and the dummy semiconductor memory means; and a third transistor and a seventh transistor respectively. Ninth and first connected in series
And an output signal stabilizing section in which the 0 transistor forms a current mirror structure.

Since the dummy semiconductor memory means is composed of a semiconductor memory transistor having a low on-resistance, the current flowing through the seventh transistor simulates a value obtained when a semiconductor memory transistor having a low on-resistance is selected. Connecting the ninth transistor having a current mirror structure and the ninth transistor connected in series to the third transistor in series with the tenth transistor connected to the seventh transistor in this way means that the current value flowing through the seventh transistor and the third transistor And the current flowing therethrough is proportional to the current value. Therefore, with the above-described configuration, even when the memory transistors have different on-resistance values due to manufacturing conditions, the detection operation is corrected, and the detection amplifier operates to transmit a signal of a correct level.

The present invention further provides an eleventh transistor having a low on-resistance value, which is connected in series to the fifth positive power supply between the fifth positive power supply and the semiconductor memory means; Between the eleventh and
A twelfth transistor connected in series to the transistor and to which a negative feedback circuit having a fifth inverting element is connected; and a twelfth transistor connected in series to the fifth positive power supply between a fifth positive power supply and the ground, and a current connected to the eleventh transistor. The thirteenth mirror structure
A transistor, a fourteenth transistor connected between the thirteenth transistor and ground, a fifteenth transistor connected in series to the sixth positive power supply between a sixth positive power supply and a sense amplifier output, A sixteenth transistor, which is connected between the output of the sense amplifier and the ground and has a current mirror structure with the fourteenth transistor, is provided.

The eleventh to thirteenth transistors have the same functions as the first to third transistors, respectively. Further, the fourteenth transistor is turned on when a current flows through the thirteenth transistor, and the fourteenth and sixteenth transistors form a current mirror structure, so that the current flowing through the fourteenth transistor is proportional to the current flowing through the sixteenth transistor. . Further, the output potential of the sense amplifier depends on the current characteristic flowing through the fifteenth transistor and the first characteristic.
And the characteristics of the current flowing through the six transistors. As described above, since the fifteenth transistor has a circuit connection not related to the precharge operation for restoring the potential on the input side of the sense amplifier, the current characteristic of the fifteenth transistor is such that the constant current value of the fifteenth transistor is substantially constant. The ideal characteristic value can be set as follows. Since the constant current value of the sixteenth transistor is substantially constant, the connection between the fifteenth transistor and the sixteenth transistor is set as the output terminal of the detection amplifier, so that the fifteenth transistor and the sixteenth transistor are connected to the detection amplifier. Of the semiconductor memory means, thereby improving the accuracy of detecting the potential on the output side of the semiconductor memory means.

Further, according to the present invention, the seventh positive power supply is connected in series between the seventh positive power supply and the dummy semiconductor memory means,
A seventeenth transistor having a low on-resistance value, and an eighteenth transistor connected in series with the seventeenth transistor between the seventeenth transistor and the dummy semiconductor memory means and connected to a negative feedback circuit having a sixth inversion element And a nineteenth transistor connected in series to the seventh positive power supply between the seventh positive power supply and ground, forming a current mirror structure with the seventeenth transistor, and connected between the nineteenth transistor and ground. 20th transistor and 8th transistor
A twenty-first transistor connected in series with the eighth positive power supply between the positive power supply and the sense amplifier output part and forming a current mirror structure with the fifteenth transistor, and connected between the sense amplifier output part and ground; A twenty-second transistor having a current mirror structure with the twentieth transistor may be provided.

With this configuration, when the on-resistance value of the normal-side semiconductor memory means differs depending on the manufacturing conditions, the normal-side detection amplifier having the configuration according to the fourth aspect of the present invention does not operate normally. Even if
The dummy-side sense amplifier having the seventeenth through the twenty-second transistors and performing the detection operation of the dummy semiconductor memory means operates so as to correct the detection operation according to the difference in the on-resistance value to enable the normal detection operation. .

Further, according to the present invention, one dummy memory transistor having the same structure as that of the memory transistor constituting the semiconductor memory means and being turned on is connected, and a reference current of a predetermined multiple of a current value that can be passed by the dummy memory transistor is provided. A reference voltage value transmitting means for detecting a voltage value;
The first transistor and the gate of the thirteenth transistor are connected to the output side of the reference voltage value sending means, and the current value flowing through the eleventh transistor is compared with the current value flowing through the eleventh transistor and the reference current value. And a precharge detecting means for detecting a precharge state in the semiconductor memory means, wherein an output side of the precharge detecting means is connected to the semiconductor memory means. A current supply means for supplying a current between the eleventh transistor and the semiconductor memory means in addition to a current flowing through the eleventh transistor when detecting that the battery is in a charged state; it can.

With this configuration, the precharge detecting means functions to detect that the output side of the semiconductor memory means is in the precharge state, and when the output side is in the precharge state, supplies the voltage via the thirteenth transistor. In addition to the current supplied, the precharge enhancing current supply means acts to supply a precharge current to the output side of the semiconductor memory means. Therefore, the precharge detecting means and the like act to shorten the time required for the precharge operation of the semiconductor memory means and to shorten the access time to the memory transistor.

Further, according to the present invention, the seventh positive power supply is connected in series between the seventh positive power supply and the dummy semiconductor memory means,
A seventeenth transistor having a low on-resistance value, and an eighteenth transistor connected in series with the seventeenth transistor between the seventeenth transistor and the dummy semiconductor memory means and connected to a negative feedback circuit having a seventh inversion element And a nineteenth transistor connected in series to the seventh positive power supply between the seventh positive power supply and the ground, forming a current mirror structure with the seventeenth transistor, and connected between the nineteenth transistor and the ground. 20th transistor and 8th transistor
A twenty-first transistor connected in series to a positive power supply and forming a current mirror structure with the fifteenth transistor;
A twenty-second transistor connected between the first transistor and the ground and forming a current mirror structure with the twentieth transistor, a gate of the seventeenth transistor and the nineteenth transistor, and an output side of the reference voltage value sending means are connected; By comparing a current value flowing through the seventeenth transistor and the nineteenth transistor with the reference current value, a current value flowing through the seventeenth transistor and the nineteenth transistor becomes equal to or greater than the reference current value.
Second precharge detection means for detecting a precharge state in the dummy semiconductor memory means is connected to an output side of the second precharge detection means, and the dummy semiconductor memory means is precharged by the second precharge detection means. A second precharge enhancing current supply means for supplying a current between the seventeenth transistor and the dummy semiconductor memory means in addition to a current value flowing through the seventeenth transistor when the state is detected. You may do it.

With this configuration, the dummy-side sense amplifier including the seventeenth through the twenty-second transistors, the second precharge detection means, and the second precharge enhancement current supply means can detect the normal side sense amplifier. Even in the case where normal operation cannot be performed due to memory transistor characteristics that differ depending on manufacturing conditions, the above-described detection operation is corrected and normal operation is performed.

Further, the present invention relates to a detecting and amplifying means having a current mirror structure, wherein the input side is connected to the output side of the semiconductor memory means, and the detecting and amplifying means has a current mirror structure and performs a detecting operation of a current value transmitted by a detection target memory transistor in the semiconductor memory means. A dummy detection amplifier having a current mirror structure, wherein an input side is connected to an output side of the dummy semiconductor memory means simulating the semiconductor memory means, and a detection operation of a current value transmitted by a dummy memory transistor in the dummy semiconductor memory means is performed. Means, a load terminal connected to the input side of the detection output means connected to the output side of the detection amplification means, and a control current input terminal connected to the output end of the dummy detection amplification means, The current value sent from the detection output means is determined in relation to the current value at the output side of the detection amplification means. Load means for flowing the reference current of the semiconductor memory means, wherein the dummy semiconductor memory means has a maximum current value and a minimum current value among the current values of the detection target memory transistors selected by the semiconductor memory means. And a comparison current generating means for generating a current having a current value between the current value and the current value.

With this configuration, the comparison current generating means has a current value between the maximum current value and the minimum current value among the current values flowing through the memory transistor to be detected selected by the semiconductor memory means. Since a current is generated, the reference current flowing through the load means is set to a current value corresponding to the maximum current value and the minimum current value, thereby improving detection accuracy.

Further, the comparison current generating means has a dummy semiconductor memory array having a low on-resistance value, and a low-resistance dummy semiconductor memory means connected to an input side of the dummy detection amplification means, and a high on-resistance value. A high-resistance dummy semiconductor memory means connected to an input side of the dummy detection amplification means in parallel with an output side of the low resistance dummy semiconductor memory means, and an equivalent of the dummy detection amplification means. The high-resistance and low-resistance dummy semiconductor memory means, which have the same equivalent resistance value as the resistance value, may include a shunt means having an input side connected to an output side connected in parallel.

With this configuration, the low-resistance dummy semiconductor memory means, the high-resistance dummy semiconductor memory means, and the shunting means set the reference current flowing through the load means to a current corresponding to the maximum current value and the minimum current value. Set to a value to improve detection accuracy.

Further, according to the present invention, there is provided a detecting and amplifying means having a current mirror structure, wherein an input side is connected to an output side of a semiconductor memory means, and a detecting operation of a current value transmitted by a memory transistor to be detected in the semiconductor memory means is performed. A dummy mirror having a current mirror structure, wherein an input side is connected to an output side of the dummy semiconductor memory means simulating the semiconductor memory means, and an operation of detecting a current value transmitted by a dummy memory transistor in the dummy semiconductor memory means is performed. Amplifying means, having a load terminal connected to the input side of the detection output means connected to the output side of the detection amplification means, and a control current input terminal to which the output terminal of the dummy detection amplification means is connected, To determine the current value sent from the detection output means in relation to the current value on the output side of the detection amplification means Load means for flowing a reference current, the dummy semiconductor memory means has a dummy semiconductor memory array having a low on-resistance value, and a low-resistance dummy semiconductor memory means connected to the input side of the dummy detection amplifier means; Having a dummy semiconductor memory array having an on-resistance value, and having a high-resistance dummy semiconductor memory means connected to an input side of the dummy detection amplification means in parallel with an output side of the low-resistance dummy semiconductor memory means, A detection amplifier which is a comparison current generating means for generating a current having a current value between a maximum current value and a minimum current value among the current values flowing through the detection target memory transistor selected by the semiconductor memory means; Therefore, the current amplification factor of the current amplification structure of the detection amplification means is smaller than the current amplification factor of the dummy detection amplification means of the current mirror structure. Characterized in that it is a major.

With this configuration, the ratio of the current amplification factor between the detection amplification means and the dummy detection amplification means is determined by setting the reference current value flowing through the load means to the current flowing through the detection target memory transistor selected by the semiconductor memory means. Of the values, the current value is set so as to be between the current value corresponding to the maximum current value and the current value corresponding to the minimum current value, thereby improving the detection accuracy.

The comparison current generating means according to claims 8 and 10 may be configured so that the number of series connection stages of memory transistors is equal to or greater than the number of series connection stages of memory transistors in a current path to the ground of the semiconductor memory array included in the semiconductor memory means. A semiconductor memory transistor having a low on-resistance value that forms a current path to ground, and the same or as many as the number of serially connected memory transistors in the current path to ground of the semiconductor memory array included in the semiconductor memory means. A semiconductor memory transistor having a high on-resistance value, which is formed in parallel with the semiconductor memory array, may form a current path leading to the ground having a greater number of stages.

With this configuration, the comparison current generating means can output the current value of the memory transistor to be detected,
The current value is set so as to be between the current value corresponding to the maximum current value and the current value corresponding to the minimum current value, thereby improving detection accuracy.

[0033]

【Example】

First Embodiment: A first embodiment of the sense amplifier of the present invention will be described with reference to FIG. The input side of the sense amplifier 1 to which the output side of the selection unit 52 is connected has an NMO
A source of the S transistor 4 is connected, and a source of the NMOS transistor 4 is connected to the positive power supply 2 at a drain of the NMOS transistor 4.
3 are connected in series. In addition, PM
The on-resistance value of the OS diode 3 is set lower than the on-resistance value of the conventional PMOS diode when used in the above-described circuit configuration. For example, in the above-described circuit configuration, the voltage drop value due to the on-resistance of the conventional PMOS diode is almost equal to the power supply voltage value of 5 V, but the voltage drop value of the PMOS diode 3 in this embodiment is about 0.5.
V, which is about 10 times different from the conventional one. To further explain the voltage drop value, the lower limit value of the voltage drop value is a value that is not lower than the voltage value of a so-called bit line connected to the sense amplifier from the memory array unit 51 via the selection unit 52. The upper limit is a value sufficient for the PMOS diode 3 to operate as a current mirror structure as described later.

The input side of the sense amplifier 1 is connected to the inverter 5 of the inverters 5 and 6 connected in series.
Are connected to each other, and the drain side of an NMOS transistor 7 whose source side is grounded and whose gate is connected to the output side of the inverter 6 is connected to each other. The inversion potential of the inverter 6 is set to an intermediate potential between the inversion potential of the inverter 5 and the potential obtained by adding the threshold voltage of the NMOS transistor 4 to the inversion potential. The connection point between the PMOS diode 3 and the NMOS transistor 4 is connected to the gate of the PMOS diode 3 and the gate of the PMOS transistor 9 whose source is connected to the positive power supply 8. still,
The on-resistance value of the PMOS transistor 9 may be different from the on-resistance value of the PMOS diode 3 described above, but it is preferable that the on-resistance value is designed to be the same value or a larger value during normal design. This is because it is desirable that the current amplification factor by the current mirror circuit described later be 1 or more.

An NMOS transistor 10 whose source is grounded is connected in series to the drain of the PMOS transistor 9.
The connection point with the transistor 10 is connected to the output unit via the inverter 11. Note that, for the sake of explanation, the above-described constituent part 2
The portion composed of the components 9 to 9 is referred to as a detection amplification section.

With this configuration, the PMOS diode 3 and the PMOS transistor 9 form a current mirror structure. Therefore, the value of the current that the PMOS transistor 9 intends to flow is proportional to the value of the current flowing through the PMOS diode 3. Therefore, like the conventional sense amplifier, PM
The output signal level of the detection amplifier does not reach the potential of the connection point between the OS transistor and the NMOS transistor. Therefore, even if the selected memory transistor has a low resistance, the PMOS diode 3 and the N
By adjusting the on-resistance value of the MOS transistor 4, it is possible to prevent the input potential of the detection amplifier from becoming unnecessarily lower than the inversion potential of the inverter 5.

In the manufacture of an integrated circuit, when a large number of memory transistors constituting a semiconductor memory array to be formed have low on-resistance values,
Or, conversely, it may vary from wafer to wafer, such as when the on-resistance value is high and many are configured. Therefore, the present sense amplifier 1 is configured such that a large number of memory transistors constituting a semiconductor memory array have low on-resistance values, or conversely, a large number of memory transistors having high on-resistance values. Even
H, L in which the output signal level of the inverter 11 is stable
In order to automatically adjust the resistance value of the load of the PMOS transistor 9 to a level, a dummy detection amplification unit 12 having a circuit configuration substantially similar to that of the above-described detection amplification unit is provided.

The input side of the dummy sense amplifier 12 is provided with a known semiconductor memory array, that is, a dummy memory array unit 13 having only the same configuration as the memory array unit 51 and having only a low on-resistance value. The output side of the dummy selection unit 14, which is connected to the output side and has the same configuration as the selection unit 52, is connected. Note that a decoder section is connected to the dummy memory array section 13 and the dummy selection section 14 as shown in FIG. A circuit portion including the dummy memory array unit 13 and the dummy selection unit 14 is referred to as a dummy semiconductor memory unit 601.

The dummy sense amplifier 12 is configured as follows, similarly to the sense amplifier. That is, the input side of the dummy detection amplification unit 12 is connected to the source side of the NMOS transistor 17 at the input side, and the drain side of the NMOS transistor 17 is connected to the source side to the positive power supply 15. 16 are connected in series. In addition, PMOS
The on-resistance value of the diode 16 is equal to the above-mentioned PMO
It is set low similarly to the S diode 3.

Further, the input side of the dummy sense amplifier 12 is connected to the input side of the inverter 18 in the inverters 18 and 19 connected in series, and the source side is grounded and the gate is connected to the output side of the inverter 19. The drain sides of the transistors 20 are respectively connected. The connection point between the PMOS diode 16 and the NMOS transistor 17 is connected to the gate of the PMOS diode 16 and a PMO having a source connected to the positive power supply 21.
Connected to the gate of S transistor 22. In addition, PMO
The ON resistance value of the S transistor 22 may be different from the ON resistance value of the PMOS diode 16,
It is preferable that the values be the same or more.

The drain side of the PMOS transistor 22 is connected in series with an NMOS transistor 23 whose source side is grounded. The drain side of the NMOS transistor 23 is connected to the NMOS transistor 23 and the above-described NMOS transistor.
Connected to each gate of transistor 10.

The operation of the sense amplifier 1 configured as described above will be described below. The inverter 5 and the NMOS transistor 4 operate to keep the input-side potential of the detection amplification unit constant, similarly to the operation of the conventional detection amplifier. That is,
As described above, the NMOS transistor is turned off and on by the high resistance or the low resistance of the selected memory transistor among the memory transistors constituting the memory array unit 51. Further, as described above, the PMOS diode 3 and the PMOS transistor 9 have a current mirror structure.

Therefore, when the selected memory transistor has a high resistance, the NMOS transistor 4 is turned off, so that both the PMOS diode 3 and the PMOS transistor 9 pass little or no current. . Therefore, the input side potential of the inverter 11 becomes L level, and an H level signal is sent to the output unit.

On the other hand, when the memory transistor is in a low resistance or on state, the NMOS transistor 4 is kept on by the action of the inverter 5. Therefore, the input side of the detection amplification unit is connected to the PMOS diode 3 and the NM
Although the potential is determined by the on-resistance of the OS transistor 4, the resistance value via the NMOS transistor 4 is reduced by the PMOS transistor due to the current mirror structure.
This can be reduced by lowering the on-resistance value of the diode 3. Therefore, current can be supplied from the positive power supply 2 via the PMOS diode 3 at high speed.

Therefore, after the low-resistance memory transistor is selected, even if the next selected memory transistor is in the high-resistance or off state, the input-side potential of the detection amplifier, which is a drawback of the conventional detection amplifier, is low. The problem that the sense amplifier does not operate normally until recovery is solved. Therefore, the potential of the input section of the sense amplifier can be kept constant for a very short time without requiring a separate clock signal unlike the conventional sense amplifier, and high-speed access is possible.

When the selected memory transistor has a low resistance, a current flows through the PMOS diode 3, so that a current also flows through the PMOS transistor 9 by the current mirror structure. Therefore, the input side potential of the inverter 11 becomes H level, and an L level signal is sent to the output unit.

Since the present sense amplifier operates as described above, the potential on the output side of the inverter 5 is usually the inverted potential of the inverter 5 plus the threshold voltage of the NMOS transistor 4 during the above-described operation period. It does not drop below the potential. However, when positive-direction noise is input to the input side of the sense amplifier, the above potential may decrease.

In such a case, as described above, the inverted potential of the inverter 6 is set to an intermediate potential between the inverted potential of the inverter 5 and the potential obtained by adding the threshold voltage of the NMOS transistor 4 to the inverted potential. When the above noise is input, the output side of the inverter 6 becomes H level,
MOS transistor 7 is turned on. Therefore, the potential at the input section of the detection amplification section decreases, and the noise is removed. When the output potential of the inverter 5 rises, the output potential of the inverter 6 changes to L level and NM
The OS transistor 7 changes to the off state.

By providing the inverter 6 in this manner, when a positive-direction noise input to the detection amplifier is input,
By controlling the gate voltage of the NMOS transistor 7, the input resistance of the detection amplification unit can be reduced, and the noise can be quickly eliminated. Therefore, the NMOS transistor 4
Is stabilized, the signal level sent from the inverter 11 to the output section can be stabilized without delay.

Further, the provision of the dummy detection amplifier 12 makes it possible to simulate the output current of the detection amplifier when the ON resistance value of the selected memory transistor is low. That is, in the dummy detection amplification unit 12, the selected memory transistor has a low on-resistance value, and as described above, the PMOS transistor 22
Current flows. Therefore, the NMOS transistor 23 is turned on, and the NMOS transistor 10 having a current mirror structure with the NMOS transistor 23 is also turned on.
A current proportional to the current flowing through the S transistor 23 flows. Therefore, the magnitude of the current flowing through the PMOS transistor 9 can be made proportional to the magnitude of the current flowing through the PMOS transistor 22 in the dummy detection amplifier.

As described above, when the on-resistance value of the memory array section 51 is biased to a lower value due to the manufacturing conditions, the amount of current flowing through the PMOS transistor 9 is automatically adjusted accordingly to the smaller value. When the on-resistance value is biased toward the higher side, the current amount flowing through the PMOS transistor 9 can be automatically adjusted so as to increase. Therefore, a stable H or L level potential is supplied to the input side of the inverter 11, and an erroneous output level is not sent from the detection amplifier 1. Therefore, the sense amplifier 1
Is guaranteed, the reliability of the memory circuit operation can be improved.

Further, since the dummy detection amplifier 12 is provided, the detection limit due to the variation of the ON current of the memory transistor in the memory array 51 due to the manufacturing conditions depends on the relative error from the absolute error by the automatic correction function. As a result, the yield of the product of the sense amplifier is improved. Therefore, the reliability of the operation as the detection amplifier is improved.

Second Embodiment: By adopting the circuit configuration described in the first embodiment, as described above, the P shown in FIG.
Although the on-resistance of the MOS diode 3 can be reduced, the reduction of the on-resistance is limited due to the limitation of the current mirror operation with the PMOS transistor 9. That is,
For example, in the case of a low-voltage operation in which the power supply voltage is 2 to 3.6 V, the on-state current of the memory transistor in the memory array unit 51 decreases, but even in that case, the voltage of the PMOS diode 3 required for the current mirror operation is reduced. The descent must be kept constant. Therefore, the on-resistance value of the PMOS diode 3 needs to be set to a certain value or more. Therefore, in the circuit configuration of the first embodiment, the output side of the memory array unit 51 and the column selection unit 52, in other words, the input of the sense amplifier The above P
There is a disadvantage that the precharge operation for supplying a current via the MOS diode 3 cannot be accelerated more than a certain level.

Since the PMOS diode 3 and the PMOS transistor 9 have a current mirror structure,
The impedance of the PMOS transistor 9, which appears at the drain of the transistor, changes relative to the on-current of the memory transistor. The response speed at this time is almost P
The response speed is determined by the gate capacitance of the MOS diode 3 and the PMOS transistor 9, and when the gate capacitance is large, the response speed is reduced. Therefore, it is necessary to select the minimum length of the gate channel of these transistors allowed in the process.

However, for example, the on-resistance value is reduced by shortening the gate channel length of the PMOS transistor. However, as shown in FIG. By turning on and off, the slope of the graph showing the current characteristic in the saturation region as shown by the graph shown by the dotted line becomes large. On the other hand, the characteristics of the NMOS transistor 10 do not change since the channel length is not changed unlike the PMOS transistor 9, and exhibit substantially constant current characteristics in the saturation region.

In the first embodiment, the PMO
Since the potential at the connection point between the S transistor 9 and the NMOS transistor 10 is used as the detection amplifier output, the inverter 1
6 to provide a sufficient logic level at the input of
As shown by "A" in (a), the voltage between the drain and the source of the PMOS transistor 9 needs to be made to substantially swing from the ground potential to the positive power supply potential. Therefore, when the drain-source voltage as shown in the above “A” is set, the PMO
P when the gate channel length of S transistor is shortened
The constant current characteristic of the MOS transistor is represented by a dotted line graph B.
1, B2. For example, the gate voltage of the PMOS transistor when the drain voltage value is “D” in FIG. 6A will be obtained from FIG. 6B. FIG. 6B shows the relationship between the gate voltage and the drain current of the PMOS transistor.

At the drain voltage value “D”, the graph B
The drain current values of the PMOS transistor when exhibiting the characteristics 1 and B2 are "D1" and "D2". As shown in FIG. 6B, the change in the gate voltage of the PMOS transistor at this time is "D1" and "D2". E ". On the other hand, the characteristics of the PMOS transistor in the case where the gate channel length is made longer without being shortened is shown by a dashed line graph C in FIG.
1 and C2. In such a current characteristic, as in the case described above, the drain current value of the PMOS transistor when the drain voltage value is, for example, “D” is “D3” and “D4”, as shown in FIG. The change in the gate voltage of the PMOS transistor at this time is "F".

As can be seen from FIG. 6A, when the drain voltage value is "D", the change in the drain current value of the PMOS transistor of each characteristic is smaller than that of the PMOS transistor having a shorter gate channel length. There are fewer PMOS transistors with longer channel lengths. As described above, when the variation of the output of the sense amplifier is fixed to "A", the drain of the PMOS transistor having a longer gate channel length is longer than the variation (D1-D2) of the drain current of the PMOS transistor having a shorter gate channel length. Since the change in the current (D3-D4) is smaller, there is a disadvantage in that when the gate channel length is shortened, the amplification ratio of current to voltage in the PMOS transistor becomes worse. That is, the improvement of the operation speed of the PMOS transistor and the improvement of the current-to-voltage amplification factor are of opposite properties.

The sense amplifier according to the second embodiment eliminates these disadvantages, and allows faster access to the memory transistor by precharging the bit line at a higher speed. It is configured for the purpose of improving the rate and improving the detection accuracy.

The second embodiment will be described below with reference to FIGS. Although FIGS. 2 and 3 are originally shown in a diagram, they are divided for the sake of space, and the portions corresponding to * 1 to * 4 shown in FIGS. By connecting them together, they are combined into one figure. or,
2 and 3, the same components as those shown in FIG. 1 referred to in the first embodiment are denoted by the same reference numerals. Therefore, the operations and the like of these components are the same as those described in the first embodiment, and the description thereof will be omitted unless otherwise specified.

As in FIG. 1, the source of the PMOS diode 3 is connected to the positive power supply 100,
The drain of the NMOS transistor 4 is connected to the drain, and the source of the NMOS transistor 4 is connected to the output of a column selection unit 52 connected to the memory array unit 51. The output side of the column selection unit 52 is connected to the gate of the NMOS transistor 4 via the inverter 5 and
The drain side of the S diode 3 is the PMOS diode 3
Connected to the gate.

Further, the source is connected to the positive power supply 100, the gate of the PMOS diode 3 is connected to the gate of the PMOS transistor 9, and the drain side of the PMOS transistor 9 forming a current mirror structure with the PMOS diode 3 is connected to the NMOS diode. 101 is connected to the drain. Further, the drain side of the NMOS diode 101 is connected to the gate of the NMOS diode 101,
The source side of MOS diode 101 is grounded. still,
As described below, the output point of the sense amplifier is
Since the configuration is taken from the connection portion between the transistor 102 and the PMOS transistor 104, the PMOS transistor 9 has a structure in which the gate channel length of the PMOS transistor 9 is as short as possible for the purpose of improving the operation speed.

As described above, the gate channel length of the PMOS transistor 9 is reduced, and the NMOS transistor 9 shown in FIG.
The transistor 10 is an NMOS diode 10 shown in FIG.
By setting to 1, the PMOS transistor 9 and the NMOS transistor
The current characteristics of the diode 101 are as shown in FIG. The current characteristic of the PMOS transistor 9 shown in FIG. 7 is equal to the current characteristic of the PMOS transistor 9 shown by a dotted line in FIG. Therefore, the value of the drain current flowing through the contact portion between the PMOS transistor 9 and the NMOS diode 101 is obtained from the intersection of the current characteristic graph of the PMOS transistor 9 and the current characteristic graph of the NMOS diode 101, and the change is apparent from FIG. As shown in FIG. Thus, the drain side of the NMOS diode 101 is connected to the NMOS diode 1.
Since the current characteristic of the NMOS diode 101 shows a steep rise by connecting to the gate of the gate 01, the change "G" in the drain current value becomes larger than that of a simple resistance load.

PMO whose source is connected to positive power supply 103
The drain side of the S transistor 104 is connected to the output terminal of the sense amplifier of this embodiment,
Connected to the drain of the transistor 102. In addition, PM
Since the OS transistor 104 has nothing to do with the bit line precharge operation, it is not necessary to keep the on-resistance low, and thus it is not necessary to shorten the channel length. Therefore, the drain current characteristic of the PMOS transistor 104 with respect to the drain voltage can be made substantially flat in the saturation region as shown in FIG. Therefore, since the current characteristic of the NMOS transistor 102 is substantially flat from the beginning, the change in the gate voltage of the PMOS transistor 104 can be reduced, for example, as shown by “F” in FIG. By setting the connection point between the transistor 104 and the NMOS transistor 102 as the output terminal of the detection amplifier, the current-to-voltage amplification factor of the detection amplifier can be improved.
In addition, the improvement in the current-to-voltage amplification ratio improves the detection capability with respect to the variation in the on-current of the memory transistor, thereby improving the product yield. Therefore, the operation reliability of the product can be improved.

The gate of the NMOS transistor 102 is connected to the gate of the NMOS diode 101,
MOS diode 101 and NMOS transistor 102
Forms a current mirror structure. The source side of the NMOS transistor 102 is grounded.

Further, the drain side of the PMOS transistor 202 whose source is connected to the positive power supply 201 and whose on-resistance is formed lower than that of the PMOS diode 3 is NM.
NMO connected to the drain side of the OS transistor 203
The source side of the S transistor 203 is connected between the source of the NMOS transistor 4 and the connection point on the input side of the inverter 5 on the bit line. Also, NMOS
The output side of the inverter 5 is connected to the gate of the transistor 203.

The positive power supply 201, the PMOS transistor 202, and the NMOS transistor 203 constitute a precharge enhancing current supply circuit 200. The precharge enhancing current supply circuit 200 is used to supply a current having a larger current value to the bit line in addition to the current flowing to the bit line via the PMOS diode 3 when the bit line is precharged. This is a circuit for speeding up the precharge operation.

The reference voltage sending circuit 250 and the precharge detecting circuit 300 shown in FIG. 3 are circuits related to the precharge operation of the bit line together with the precharge enhancing current supply circuit 200 described above. That is, as described above, the PMOS diode 3, the PMOS transistor 9, and the PMOS transistor 302 described later have a current mirror structure. As will be described later, in the present embodiment, many other current mirror structures are provided. During precharge, current flows from the positive power supply to the portions forming the current mirror structure, and power consumption increases. The reference voltage value sending circuit 250 and the like are circuits for suppressing power consumption during precharge.

The start of the precharge operation is detected in a state other than the precharge state.
Since the current value flowing through the memory transistor does not exceed the ON current value of the memory transistor, the ON current value of the memory transistor transmitted from the reference voltage value transmitting circuit 250 by utilizing this fact, the current value flowing through the bit line, That is, PMO
This is possible by comparing the value with the current flowing through the S diode 3.

The reference voltage sending circuit 250 is a circuit for generating a current value corresponding to the above-mentioned ON current value of the memory transistor. The ON current value of the memory transistor sent from the output terminal of the sense amplifier shown in FIG. A voltage used for the purpose of detecting a reference current having a value equal to or several times the ON current is transmitted. Therefore, the circuit configuration of the reference voltage value sending circuit 250 includes a portion in which the memory transistor 251 in the ON state is connected to the input side of the inverter 5 shown in FIG.
Except for 0, the circuit configuration is the same as that shown in FIG. The characteristics of each element such as the on-resistance value are determined by the reference voltage value sending circuit 2.
In the case where the reference current value indicated by the output voltage value of 50 and the output current value of the detection amplifier are the same, the conditions are exactly the same,
To set the output voltage value of the reference voltage value sending circuit 250 to a value several times the output current value of the detection amplifier, for example, the PMOS diode 253 and the PMOS transistor 256 or the NMOS diode 257 and the NMOS
The ratio of the channel width to the transistor 258 may be changed.

Therefore, the circuit configuration of reference voltage value sending circuit 250 will be briefly described, but positive power supply 100 shown in FIG.
Corresponds to the positive power supply 252 shown in FIG.
Is a PMOS diode 253, and N
The one corresponding to the MOS transistor 4 is the NMOS transistor 254, the one corresponding to the inverter 5 is the inverter 255, the one corresponding to the PMOS transistor 9 is the PMOS transistor 256,
The one corresponding to the S diode 101 is the NMOS diode 257, the one corresponding to the NMOS transistor 102 is the NMOS transistor 258,
A transistor corresponding to the transistor 104 is a PMOS transistor 259. The drain side of the PMOS transistor 259 is provided with a gate of the PMOS transistor 259 and a precharge detection circuit.
The gate of the transistor 305 is connected. In addition, PMO
The voltage value sent from the drain side of S transistor 259 is a voltage value indicating the reference current value provided from reference voltage value sending circuit 250.

The precharge detection circuit 300 includes a PMOS
This circuit compares the value of the current flowing through the diode 3 with the reference current value provided by the above-described reference voltage value sending circuit 250, and sends a signal level corresponding to the comparison result to the precharge enhancing current supply circuit 200. .

The precharge detection circuit 300 has the following circuit configuration. PM whose source side is connected to the positive power supply 301
The gate of the OS transistor 302 is connected to the PM shown in FIG.
The OS diode 3 and the gate of the PMOS transistor 9 are connected. Therefore, the PMOS transistor 302
Forms a current mirror structure together with the PMOS diode 3 and the PMOS transistor 9. The drain side of the PMOS diode 302 is connected to the drain side of the NMOS diode 303, the source side of the NMOS diode 303 is grounded, and the drain side of the NMOS diode 303 is connected to the gate of the NMOS diode 303.

As in the circuit configuration described above, the positive power supply 301
As described above, the gate of the PMOS transistor 305 whose source is connected to
Output terminals are connected. Therefore, the PMOS transistor 305 is the PMOS transistor included in the reference voltage sending circuit 250.
The transistor 259 has a current mirror structure. PM
The drain side of the OS transistor 305 is connected to the drain side of the NMOS transistor 304, the source side of the NMOS transistor 304 is grounded, and the gate of the NMOS transistor 304 is connected to the NMOS transistor 3
03 is connected to the gate. Therefore, the NMOS diode 303 and the NMOS transistor 304 form a current mirror structure. Further, the drain side of the PMOS transistor 305 is connected to the gate of the PMOS transistor 202 provided in the precharge enhancement current supply circuit 200 described above.

In the precharge detection circuit 300 configured as described above, since the PMOS transistor 302 has a current mirror relationship with the PMOS transistor 3 and the like, PM
A current having a value several times the value of the current flowing through the OS transistor 3 flows through the PMOS transistor 302.

Further, since the NMOS diode 303 and the NMOS transistor 304 in the precharge detection circuit 300 are in a current mirror relationship, a current several times the value of the current flowing through the NMOS transistor 303 flows through the NMOS transistor 304. That is, NMO
The value of the current flowing through the S transistor 304 is a value corresponding to the value of the current flowing through the PMOS transistor 3.

Further, since the PMOS transistor 305 has a current mirror relationship with the PMOS transistor 259 provided in the reference voltage sending circuit 250, the value of the saturation current characteristic flowing through the PMOS transistor 305 is several times the reference current value. Become.

Therefore, the PMOS transistor 305
, The potential applied to the gate of the PMOS transistor 202 provided in the precharge enhancement current supply circuit 200 is the value of the saturation current characteristic flowing through the PMOS transistor 3, in other words, the saturation current characteristic flowing through the NMOS transistor 304. And the value of the saturation current characteristic flowing through the PMOS transistor 305,
OS transistor 305 and NMOS transistor 304
Becomes the drain voltage determined from the drain current characteristic of

The output voltage from the precharge detection circuit 300 determines the P level of the precharge enhancement current supply circuit 200.
The MOS transistor 202 performs an on / off operation. That is, when the current value flowing through the PMOS transistor 3 is larger than the reference current value, that is, at the time of precharge, the output voltage of the precharge detection circuit 300 becomes L level and the PMOS transistor 202 is turned on.
Further, the NMOS transistor 203 is turned on by the output voltage of the inverter 5. Therefore, a current flows from the positive power supply 201 to the bit line via the PMOS transistor 202 and the NMOS transistor 203.

It should be noted that, of course, a PMOS is used for the bit line.
Although a current is supplied from the positive power supply 100 via the diode 3, as described above, since the transistor is formed so that the on-resistance value of the PMOS transistor 202 is smaller than the on-resistance value of the PMOS transistor 3, A large amount of current flows into the bit line from the positive power supply 201 side. Therefore, as in the first embodiment, the PMOS
Since the precharge operation is not performed only through the transistor 3, the time required for the precharge can be further reduced. Further, the shortening of the time required for the precharge and the bypass of the current result in the reduction of the current flowing through the PMOS transistor 9 having a current mirror relationship with the PMOS transistor 3.

When the value of the current flowing through the PMOS diode 3 is smaller than or equal to the reference current value, that is, when the current is other than the precharge, the output voltage of the precharge detection circuit 300 becomes H level and the PMOS transistor 202 is turned on. It turns off. Therefore, the positive power supply 20
No current flows from 1 to the bit line.

The operation of the sense amplifier thus configured will be described below. The operations of the NMOS transistor 4 and the inverter 5 are the same as those described in the first embodiment.
The operation of the MOS transistor 3 and the PMOS transistor 9 is the same as the operation described in the first embodiment, and the description is omitted.

In this embodiment, the NMOS diode 101
In this case, the gate and the drain of the NMOS diode 101 are connected to form a MOS diode, which is used as a load. When a current flows through the PMOS transistor 9 due to a current mirror relationship with the PMOS transistor 3, a current also flows through the NMOS diode 101.
When a current flows through the NMOS diode 101, NM
NM in current mirror relationship with OS diode 101
A current also flows through the OS transistor 102.

As will be described later, the gate of the PMOS transistor 104 is connected to the gate of a PMOS transistor 359 provided in the dummy side sense amplifier, and the PMOS transistor 104 and the PMOS transistor 359 form a current mirror relationship. And PMOS
A current several times larger than the current flowing through the PMOS transistor 359 flows through the transistor 104. When the dummy side sense amplifier is not provided, the gate of the PMOS transistor 104 is grounded.

Therefore, the PMOS transistor 104 and N
The potential at the connection point with the MOS transistor 102 is
The potential becomes a potential corresponding to a current value determined by a correlation between the current characteristics flowing through the PMOS transistor 104 and the current characteristics flowing through the NMOS transistor 102.

The current flowing through the PMOS transistor 104 is the current flowing through the PMOS transistor 3 in the dummy side sense amplifier.
Although it depends on the current flowing through the memory transistor 59, since the dummy memory array is constituted by memory transistors having a low on-resistance value as described later, the memory transistor selected by the memory array 51 on the normal side has an on-resistance value. , The current sent from the memory transistor selected from the memory array 51 on the normal side can be accurately detected from the output terminal of the sense amplifier of this embodiment.

Since the PMOS transistor 104 has a circuit configuration so as not to be related to the PMOS diode 3 and the PMOS transistor 9 involved in the precharge operation of the bit line at all, it is necessary to keep the on-resistance value low. No need to shorten the channel length. Therefore, the drain current characteristic of the PMOS transistor 104 with respect to the drain voltage can be made substantially flat in the saturation region.

On the other hand, the drain current characteristic of the NMOS transistor 102 with respect to the drain voltage is flatter than that of the PMOS transistor 9 in the saturation region. Therefore, as shown in FIG. 5, the output potential of the sense amplifier according to the present embodiment is determined by the two transistors having substantially flat drain current characteristics in the saturation region. It is improved compared to the example. Accordingly, the accuracy of the current detection of the sense amplifier is determined by the ratio of the width of the current change required for the output potential of the sense amplifier to make a full swing with respect to the average value of the ON current value of the memory transistor. Can be improved.

The current supply circuit 200 for enhancing precharge,
The operations of the reference voltage value sending circuit 250 and the precharge detection circuit 300 are briefly described above, but the precharge detection circuit 300 detects whether or not the bit line is in the precharge state and enters the precharge state. In some cases, a current is supplied to the bit line by the precharge enhancing current supply circuit 200.

Next, a case where a dummy memory array is further provided will be described. Although described in the first embodiment, in order to further improve the detection operation accuracy, in the second embodiment, the dummy memory array and other circuits associated with the dummy memory array have the circuit configuration described above. The configuration is exactly the same. Note that the reference current value sending circuit 250 is not separately provided because sharing the reference current value does not cause a problem. Note that the detection amplifier that performs the operation of detecting the dummy memory array is called a dummy-side detection amplifier, whereas the detection amplifier that performs the operation of detecting the normal memory array described above is called the normal-side detection amplifier.

The circuit on the dummy side will be described with reference to FIG. The connection and the like of each element are exactly the same as the above-mentioned connection relation, and since the identity can be easily determined from the drawings, detailed description is omitted below and only the correspondence relation of each element is described. First, reference is made to FIG. 2 and FIG. The dummy memory array unit 35 corresponds to the memory array unit 51.
0. Note that all of the memory transistors constituting the dummy memory array section 350 are formed of memory transistors having a low on-resistance value. The dummy column selection unit 351 corresponds to the column selection unit 52, the positive power supply 355 corresponds to the positive power supply 100, the PMOS diode 352 corresponds to the PMOS diode 3, and the NMO
The NMOS transistor 353 corresponds to the S transistor 4, the PMOS transistor 356 corresponds to the PMOS transistor 9, the NMOS diode 357 corresponds to the NMOS diode 101, and the NMOS transistor 102 corresponds to the NMOS transistor 102. NMO
An S transistor 358 corresponds to the positive power supply 103 and a positive power supply 360 corresponds to the PMOS transistor 104.
Corresponds to the PMOS transistor 359.

The gate of the PMOS transistor 104 and the gate of the PMOS transistor 359 are connected.
The PMOS transistors 104 and 359 form a current mirror relationship. Further, the gate of the PMOS transistor 359 and the drain of the PMOS transistor 359 are connected.

Further, a current supply circuit 400 for enhancing the precharge on the dummy side corresponds to the current supply circuit 200 for enhancing the precharge. For each element in the precharge enhancement current supply circuit, the positive power supply 401 corresponds to the positive power supply 201, the PMOS transistor 402 corresponds to the PMOS transistor 202, and the NMOS transistor
The NMOS transistor 403 corresponds to the transistor 203.

Next, reference is made to FIG. 2 and FIG. The precharge detection circuit 450 corresponds to the precharge detection circuit 300. For each element in the precharge detection circuit, the positive power supply 45 corresponds to the positive power supply 301.
1, the PMOS transistor 452 corresponds to the PMOS transistor 302, the NMOS diode 453 corresponds to the NMOS diode 303, and the NMO corresponds to the NMOS transistor 304.
S transistor 454, and PMOS transistor 3
05 corresponds to the PMOS transistor 455.

The gate of the PMOS transistor 452 is connected to the gates of the PMOS diode 352 and the PMOS transistor 356.
2, 352, 356 constitute a current mirror relationship. The drain side of the PMOS transistor 455 is P
Connected to the gate of the MOS transistor 402, the PMO
The gate of S transistor 455 is connected to the output terminal of reference voltage sending circuit 250 shown in FIG.

The operation in the case where the circuit such as the dummy memory array unit 350 is configured as described above will be described. The dummy memory transistor corresponding to the memory transistor selected on the memory array unit 51 side is
The sense operation of the selected dummy memory transistor selected from 0 is performed by the same operation as the above-described operation.
In this case, the PMOS transistor 35 provided on the dummy side
9 and the normal-side PMOS transistor 104 are in a current mirror relationship, so that a current several times larger than the current flowing through the PMOS
Flow through 4. Therefore, as described in the first embodiment, the PMOS transistor 359 can be used even when a memory transistor having a low on-resistance value is selected in the normal memory array unit 51. This ensures that an accurate detection output value is sent out from the CPU.
The current characteristics flowing through the PMOS transistor 104 are preferably set to be about 0.5 times the current characteristics flowing through the PMOS transistor 359.

The precharge detection circuit 450 detects when the bit line of the dummy memory array section 350 is precharged, and the current supply circuit 4 for enhancing the precharge on the dummy side.
The operation of supplying the current from 00 to the dummy bit line is the same as the operation of the normal sense amplifier described above.

In the second embodiment, the positive power supply 10
0, 103, etc. may be provided separately as described above, or circuits may be connected so as to be shared.

Third Embodiment In the first and second embodiments described above, the current appearing at the output of the sense amplifier is the same as that shown in FIG.
2, the intersection of the drain current characteristics of the PMOS transistor 9 and the NMOS transistor 10, and in FIG. 2, the PMOS transistor 104 and the NMOS transistor 1
02 so that the criterion for determining “0” or “1” as data at the output of the sense amplifier is not biased to either “0” or “1” at the output of the sense amplifier. The drain current characteristics of the NMOS transistors 10 and 102 serving as a reference for judging “0” or “1” as data at the output of the sense amplifier are almost の of the maximum current characteristics of the drain current characteristics of the PMOS transistors 9 and 104. Thus, in the detection amplification unit connected to the semiconductor memory 600 and the dummy detection amplification unit connected to the dummy semiconductor memory 601, transistors constituting each current mirror, for example, in the detection amplifier shown in FIG. PMOS transistor 3 and PMOS transistor 9, PMOS transistor 16 and PMOS transistor 22, NMOS The ratio of the size of the transistor 10 and NMOS transistor 23 has been adjusted.

The dummy memory array sections 13 and 350 shown in FIGS. 1 and 4 are composed of only transistors having a low on-resistance as described above. This is, for example, FIG.
In the first and second embodiments, transistors having a low on-resistance value are read based on the assumption that no leak current flows from the transistors having a high on-resistance value constituting the memory array section 51 of the semiconductor memory 600 shown in FIG. As described above, the size ratio of the transistors constituting the current mirror is reduced to よ う such that the current characteristic of オ ン of the current characteristic of the PMOS transistor 9 or the like due to the ON current becomes the current characteristic of the NMOS 10, for example. Was set.

However, actually, the memory array 51
In some cases, a voltage higher than the threshold voltage of the transistor having a high on-resistance value is applied to the gate of the transistor having a high on-resistance value. In such a case, a leak current flows from the transistor having the high on-resistance value. When such a leakage current flows, for example, as shown in FIG.
Is set to の of the drain current characteristic 701 of the PMOS transistor 9 when a memory transistor having a low on-resistance value is selected, for example, the PMOS transistor is selected when a memory transistor having a high on-resistance value is selected.
The drain current characteristic 702 of the transistor 9 approaches the above-mentioned current characteristic 700 as indicated by a dotted line, and it becomes difficult to determine “0” or “1” at the detector output unit, and the determination may be erroneous. Therefore, in order to further improve the detection accuracy, it is necessary to consider the leak current, and the detection amplifier shown in the third embodiment improves the detection accuracy in consideration of the leak current. The configuration and operation of the third embodiment will be described below.

In the figures and the like, "low threshold value" means that the on-resistance value is low, and "high threshold value" means that the on-resistance value is high. In addition, a leak current refers to a current flowing through a memory transistor having a high on-resistance value, and an on-current refers to a current flowing through a memory transistor having a low on-resistance value. Further, in the following description, the case where the circuit in the third embodiment is applied to the first embodiment will be described as an example, but it is needless to say that the circuit can be applied to the second embodiment.

FIG. 8 shows a schematic configuration of the third embodiment. The same components as those shown in FIG. 1 are denoted by the same reference numerals, and description of these components is omitted. I do. In the present embodiment, the dummy semiconductor memory 60 shown in FIG.
1 instead of the reference current NM
A comparison current generator 650 for supplying a current having a value such as to be applied to the gate of the OS 10 or 102 to the input unit is connected. Hereinafter, a specific circuit configuration of the comparison current generator 650 will be described.

As an example of the comparison current generator 650, a circuit configuration shown in FIG. 9 can be considered. This circuit configuration includes dummy semiconductor memories 653 and 656 and a shunt circuit 661. The dummy semiconductor memory 653 has a dummy memory transistor array 651 having a memory transistor with a low on-resistance value as shown in FIG. The side is connected to the “input section” of the dummy detection amplification section 662 shown in FIG.

The dummy semiconductor memory 656 has a dummy memory transistor array 654 having memory transistors with a high on-resistance value, and a dummy selection section 655 of the dummy memory transistor array 654. The output of the dummy selection section 655 is the dummy Connected to the output side of selector 652.

FIG. 10 shows a specific circuit configuration of a dummy memory transistor array 651 having a memory transistor with a low on-resistance value in the dummy semiconductor memory 653, and a memory transistor with a high on-resistance value in the dummy semiconductor memory 656. FIG. 11 shows a specific circuit configuration of the dummy memory transistor array 654 having the following. FIG.
0 and the circuit configuration itself shown in FIG. 11 is not different from the circuit configuration in a general semiconductor memory, and the description is omitted. In the figure, the transistor indicated by “M” indicates a transistor having a low threshold value, The transistor indicated by “C” indicates a transistor having a high threshold.

In FIGS. 10 and 11, "A" is H
When (high), this memory block is selected,
When "C" is H, the memory data transistor region is selected, "B" is H, "D" is L (low), the memory transistor on the left side of the memory data transistor region in the figure is selected, and "B" is selected. When L and "D" are H, the memory transistor on the right side of the drawing of the memory data transistor region is selected.

The shunt circuit 661 is obtained by removing the positive power supply 21 and the PMOS transistor 22 from the circuit configuration of the dummy detection amplifier 662 to which the dummy semiconductor memory 653 is connected.
It has a positive power supply 657, a PMOS transistor 658, an NMOS transistor 659, and an inverter 660, which have the same circuit configuration as the circuit composed of the transistor 17 and the inverter 18. The shunt circuit 661 is connected to the positive power supply 15 and the PMO
It has an equivalent resistance value to the circuit including the S transistor 16, the NMOS transistor 17, and the inverter 18, and the output side of the dummy selection unit 655 of the dummy semiconductor memory 656 is NM.
Connected to the source side of OS transistor 659.

As described above, the comparison current generator 650
Dummy semiconductor memories 653 and 656 and shunt circuit 66
The operation in the case of the configuration from 1 will be described below. The on-current value of the low-value memory transistor including the leak current is represented by i
₂ , the on-current value of the high-value memory transistor is i ₁ , the output current value of the comparison current generator 650 is i, NM shown in FIG.
The saturation current appearing at the gate of the OS transistor 10 is represented by Ir
Assuming that ef, i = (ai ₁ + bi ₂ ) / (a + b). Here, a and b are arbitrary positive numbers.

The ratio of the input to the output in the detection amplifier 662 shown in FIG. 8, that is, the current amplification factor is α, the ratio of the input to the output in the detection amplifier 663 shown in FIG. 8, ie, the current amplification factor is β, and FIG. The ratio of the input to the output of the current mirror used as the load circuit 664 shown, that is, the current amplification factor is γ, for example, α = β · γ, and the current amplification factor is connected to the output of the dummy detection amplification unit 663. The current value appearing at the output of the load circuit is I ₁ with respect to the current value i ₁ , and the current value i ₂
When I ₂ relative, since it is _{Iref = α · (ai 1 +} bi 2) / (a + b) I 1 = αi 1, I 2 = αi 2, Iref = (aI 1 + bI 2) / a (a + b) Become. Note that the ratio α is, for example, PM in FIG.
The ratio β indicates how many times the OS transistor 9 flows the current of the PMOS transistor 3. The ratio β is, for example, a ratio indicating how many times the current of the PMOS transistor 22 flows in the PMOS transistor 16 in FIG. The ratio γ is, for example, a ratio indicating how many times the current of the NMOS transistor 23 flows in the NMOS transistor 10 in FIG.

In the case where the comparison current generator 650 is composed of the dummy semiconductor memories 653 and 656 and the shunt circuit 661, for example, the values of a and b are set to approximately 1, and the value of i ₂ is the output from the dummy semiconductor memory 653. And i ₁ is the output current from the dummy semiconductor memory 656. The sum of these output currents, i ₁ + i _2, is attenuated by the shunt circuit 661. In the present embodiment, as described above, since the shunt circuit 661 is configured to have an equivalent resistance value to the dummy detection amplification unit 663 shown in FIG. 8, the value of i ₁ + i ₂ is halved, and the value of Iref is reduced. the value is in the oN current value i ₂ of the low-value memory transistors, a value corresponding to approximately 1/2 of the oN current value i ₁ of the high-frequency value memory transistor. As described above, in the present embodiment, the Iref value is determined in consideration of the leak current, so that more accurate detection can be performed.

In the above description, for example, the reference current value flowing through the NMOS ₁₀ is about 1/2 of the on-current value i ₂ of the low-frequency memory transistor and the on-current value i ₁ of the high-frequency memory transistor. The values are set to correspond to each other, but are not limited thereto. According to the configuration of the present embodiment, for example, the ratio of each current mirror, that is, the ratio α,
By changing β and γ, the reference current value can be set to correspond to an arbitrary value between the ON current value i ₂ of the low-frequency memory transistor and the ON current value i ₁ of the high-frequency memory transistor. Can be set.

Further, in this embodiment, the shunt circuit 661 is provided as described above to attenuate the value of i ₁ + i ₂ . adjust the alpha, beta, the gamma alpha: the I ₂ to change the ratio, the corresponding current values of the reference, for example through the NMOS transistor 10 to turn on the current value of the low-value memory transistor (β · γ), The value may be set to an intermediate value from I ₁ corresponding to the on-current value of the high-value memory transistor.

Since the comparative current generator 650 has the above-described structure, the circuit scale is slightly increased.
As a configuration example of the comparison current generating device 650, a configuration as shown in FIG. 12 or FIG. 13 can be adopted. These are structures in which the structure of the dummy semiconductor memory is changed to control the leak current or the ON current itself sent from the dummy semiconductor memory array. That is, the dummy semiconductor memory usually has the structure shown in FIG. 10 or FIG.
In the case of the dummy semiconductor memory array indicated by 0, the on-current value is determined by a low threshold memory transistor, for example, the memory transistors 665, 666, and 6 connected in series in the block selector and the memory data transistor region.
67. Therefore, as shown in FIG. 12, the low threshold memory transistors 668 to 671 are connected in parallel to the transistors constituting the high threshold memory data transistor region.

As shown in FIG. 12, five memory transistors having low threshold values are connected because the memory transistors having low threshold values connected in series in FIG.
5, 666, 667, so that the number of memory transistors having low threshold values connected in series is doubled, so that the on-current value is transmitted from the dummy semiconductor memory array shown in FIG. This is because the ON current value is set to about 1/2.

With this configuration, in this case, for example, in the above α, β, and γ, α = β and γ = 1 should be set, but when the leak current is less than half of the memory ON current, As shown in FIG. 15, when there is no leakage current, for example, the current characteristic 700 of the NMOS transistor 10 is located almost in the middle of the current characteristic 701. 700 is close to the current characteristic 702. However, by adding the leakage current as described above, the current characteristic 700 is changed to the current characteristic 703 indicated by the dotted line, so that the margin for the proximity to the current characteristic 702 can be increased. In other words, Iref can be corrected so that the leakage current value is added to the current characteristic 700.

Therefore, for example, the NMOS transistor 1
The reference current flowing through 0 is a value in a direction in which the detection accuracy is higher than an intermediate value between I ₂ corresponding to the ON current value of the low-value memory transistor and I ₁ corresponding to the ON current value of the high-value memory transistor. Can be set to

Although the dummy semiconductor memory array shown in FIG. 12 is configured to apply the leak current as it is, as shown in FIG. 13, memory transistors having a high threshold value are connected in parallel so as to reduce the leak current. May be configured. Even with this configuration, the same effect as in the case of the configuration shown in FIG. 12 can be obtained. In this case, the leak current does not have to be less than half of the ON current of the memory transistor.

Although the circuit configuration shown in FIG. 12 cannot be adopted unless the leak current value is less than half of the on-current value, the on-current value of a normal memory transistor is about 250 microamperes. Since the leak current value is about 10 to 20 microamps, the above condition is sufficiently satisfied. Therefore, providing the dummy semiconductor memory array shown in FIG. 12 and the like is very effective as a detection amplifier having a small circuit scale and high detection accuracy.

In the above-described first to third embodiments, the conductivity type of each transistor and the like including the memory transistor is not limited to the above, and the P-type and the N-type are reversed in each of the transistors and the like. It may be what you did.

[0121]

As described in detail above, according to the present invention, since the first transistor and the third transistor have a current mirror structure, the on-resistance value of the first transistor can be set low. Can be controlled in a short time, and the access time to the memory transistor can be shortened. Further, according to the present invention, by providing the noise removing means, even if noise is input to the input section of the detection amplifier, it is possible to prevent the output signal of the detection amplifier from being affected.

Further, by providing a dummy detection amplifier and a current mirror structure of the ninth transistor and the tenth transistor, even when a memory transistor having a low on-resistance value is selected, the output of the detection amplifier can be reduced. A signal of a normal signal level can be transmitted from the unit even according to the memory transistor characteristics that vary depending on the manufacturing conditions.

Further, according to the present invention, the connection between the sixteenth transistor having a current mirror structure and the fifteenth transistor with respect to the fourteenth transistor acting as a load element of the thirteenth transistor having a current mirror structure with the eleventh transistor is provided. Since the fifteenth transistor has a circuit connection irrelevant to the precharge operation of the semiconductor memory means by adopting a circuit configuration having a point as the output terminal of the detection amplifier, the channel length of the fourteenth, fifteenth and sixteenth transistors is The constant current characteristics of these transistors can be set to be substantially constant. Therefore, it is possible to improve the current-to-voltage amplification factor of the detection amplifier determined by the current characteristics of the fifteenth transistor and the sixteenth transistor, and to improve the detection accuracy of the output terminal potential of the semiconductor memory means.

Further, the same dummy-side detection amplifier as that described in claim 4 for detecting the output terminal potential of the dummy semiconductor memory means is connected to the normal-side detection amplifier having the structure described in claim 4. Thus, even if the detection operation of the normal-side detection amplifier becomes unstable, the dummy-side detection amplifier can correct the normal-side detection amplifier to perform the normal operation.

Further, according to the present invention, when it is detected that the output side of the semiconductor memory means is in the precharge state, a precharge current is supplied from the precharge enhancing current supply means to the output side, whereby the semiconductor memory means is supplied. , The time required for precharging on the output side can be shortened, the current flowing through the thirteenth transistor and the like can be suppressed low, and power consumption can be reduced.

Further, a dummy semiconductor memory means is provided,
7. The detection operation of the normal side detection amplifier by connecting the dummy side detection amplifier loaded with the dummy side precharge detection unit and the precharge enhancement current supply unit to the normal side detection amplifier having the configuration according to claim 6. However, even in the case where the characteristics of the memory transistor differ depending on the manufacturing conditions, the dummy side detection amplifier can correct the normal side detection amplifier so that the normal operation can be performed.

Further, according to the present invention, the dummy semiconductor memory means generates a current having a current value between the maximum current value and the minimum current value flowing through the memory transistor to be detected selected by the semiconductor memory means. By using the comparison current generation means, the reference current flowing through the load means is set to the current value corresponding to the maximum current value and the current value corresponding to the minimum current value among the current values flowing through the detection target memory transistor selected by the semiconductor memory means. It can be set to a current value between the values and the detection amplifier can normally perform the detection operation even when a leak current flows from a memory transistor having a high on-resistance value.

Further, since a low-resistance dummy semiconductor memory means, a high-resistance dummy semiconductor memory means, and a shunting means are provided as the comparison current generating means, the reference current flowing through the load means is selected by the semiconductor memory means. Of the flowing current values, the current value between the current value corresponding to the maximum current value and the current value corresponding to the minimum current value can be set. The sense amplifier can operate normally even in a flowing case.

According to the present invention, the current amplification factor by the current mirror structure in the detection and amplification means is set to be larger than the current amplification factor by the current mirror structure of the dummy detection and amplification means, so that the load means is improved. The reference current flowing through the memory transistor becomes a current value between the current value corresponding to the maximum current value and the current value corresponding to the minimum current value among the current values flowing through the memory transistor to be detected selected by the semiconductor memory means. Therefore, even when a leak current flows from a memory transistor having a high on-resistance value, the sense amplifier can operate normally.

Further, the saturation current characteristic that appears at the gate of the ninth transistor, for example, is close to the current characteristic of the dummy semiconductor memory having a high threshold value due to the presence of the leak current. By providing a dummy semiconductor memory transistor having a low or high on-resistance value with an increased number of stages, a reference current is increased by an amount corresponding to a leak current, and a current of a semiconductor memory having a low threshold value and a semiconductor memory having a high threshold value Can be set at a substantially intermediate position with respect to the current characteristic of In other words, the saturation current characteristic can be corrected so that the leakage current value is added to the saturation current characteristic.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment in a sense amplifier of the present invention.

FIG. 2 is a circuit diagram showing a part of a configuration of a second embodiment in the sense amplifier of the present invention.

FIG. 3 is a circuit diagram showing a part of the configuration of a second embodiment in the sense amplifier of the present invention.

FIG. 4 is a circuit diagram showing a part of the configuration of a second embodiment in the sense amplifier of the present invention.

FIG. 5 shows the NMOS transistor 102 and P shown in FIG.
4 is a graph showing characteristics of the MOS transistor 104.

FIG. 6 is a graph showing current characteristics of a PMOS transistor and an NMOS transistor in a detection amplifier output unit.

FIG. 7 shows a PMOS transistor 9 and an NMO shown in FIG.
5 is a graph showing current characteristics of an S diode 101.

FIG. 8 is a circuit diagram showing a configuration of a first embodiment in the sense amplifier of the present invention.

FIG. 9 is a block diagram illustrating an example of a comparison current generating unit illustrated in FIG. 8;

10 is a circuit diagram showing an example of a dummy memory array of memory transistors having low threshold values shown in FIG. 9;

11 is a circuit diagram showing an example of a dummy memory array of memory transistors having low threshold values shown in FIG. 9;

FIG. 12 is a circuit diagram showing one example of a dummy memory array showing another example of the comparison current generating means shown in FIG. 8;

FIG. 13 is a circuit diagram showing another example of the dummy memory array showing another example of the comparison current generating means shown in FIG. 8;

FIG. 14 is a graph showing current characteristics when memory transistors having low and high band values are selected and characteristics of a reference current flowing through the NMOS 10;

FIG. 15 is a graph showing current characteristics when memory transistors having low and high band values are selected and characteristics of a reference current flowing through the NMOS 10;

FIG. 16 is a diagram illustrating a concept of an integrated circuit including a memory circuit unit.

FIG. 17 is a block diagram showing components for reading data from a memory circuit unit.

FIG. 18 is a circuit diagram showing a configuration of a conventional sense amplifier.

FIG. 19 is a circuit diagram illustrating a configuration example of a selection unit illustrated in FIG. 17 and the like;

20 is a circuit diagram illustrating a configuration example of a memory array unit illustrated in FIG. 17 and the like;

[Explanation of symbols]

2 Positive power supply, 3 PMOS transistor, 4 NMOS transistor, 5 and 6 inverter, 7 NMOS transistor, 8 positive power supply, 9 PMOS transistor, 1
0 ... NMOS transistor, 11 ... Inverter, 12 ...
Dummy detection amplification section, 13 ... Dummy memory array section, 14
... Dummy selection section, 23 ... NMOS transistor, 51 ...
Memory array section, 52 selection section, 101 NMOS diode, 102 NMOS transistor, 104 PM
OS transistor, 200: current supply circuit for enhancing precharge, 250: reference voltage sending circuit, 300: precharge detection circuit, 350: dummy memory array, 400
... Current supply circuit for enhancing precharge on the dummy side, 450 ...
Dummy-side precharge detection circuit, 650... Comparison current generator, 653.
56 ... Dummy semiconductor memory for flowing minimum current, 661 ... Shunt circuit, 665 to 671 ... Memory transistor with low threshold value.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 16/00-16/34 G11C 17/18

Claims (5)

(57) [Claims] 1. A fifth positive power supply (100) and semiconductor memory means
(600) in series with the fifth positive power supply, and an eleventh transistor (3) having a low on-resistance value; and the eleventh transistor and the semiconductor memory means (60).
0) is connected in series with the eleventh transistor,
A first to which a negative feedback circuit having a fifth inverting element (5) is connected;
A second transistor (4), a thirteenth transistor (9) connected in series with the fifth positive power supply between the fifth positive power supply and the ground, and forming a current mirror structure with the eleventh transistor; First connected to ground
Fourth transistor (101), and a fifteenth transistor (10) connected in series to the sixth positive power supply between the sixth positive power supply (103) and the sense amplifier output unit.
4), a sixteenth transistor (102) connected between the output of the sense amplifier and ground and forming a current mirror structure with the fourteenth transistor, a seventh positive power supply (355), and a dummy semiconductor memory means (601). )
A seventeenth transistor (352) connected in series to the seventh positive power supply and having a low on-resistance value; and the seventeenth transistor and the dummy semiconductor memory means.
(601), an eighteenth transistor (353) connected in series to the seventeenth transistor and having a negative feedback circuit having a sixth inverting element (354) connected between the seventh positive power supply and ground. A nineteenth transistor (356) connected in series to the seventh positive power supply and forming a current mirror structure with the seventeenth transistor; and a second transistor connected between the nineteenth transistor and ground.
0th transistor (357), a 21st transistor (35) connected in series with the eighth positive power supply between the eighth positive power supply (360) and the sense amplifier output section, and forming a current mirror structure with the 15th transistor.
9), a 22nd transistor (358) connected between the output of the sense amplifier and ground and forming a current mirror structure with the 20th transistor, and a memory transistor constituting the semiconductor memory means. A reference voltage value sending means (250) for detecting a reference current value that is a predetermined multiple of a current value that can be passed by the dummy memory transistor, and connected to the one dummy memory transistor in the on state; The gate of the thirteenth transistor and the output side of the reference voltage value sending means are connected, and the current value flowing through the eleventh transistor is compared with the reference current value so that the current value flowing through the eleventh transistor becomes the reference current value. A precharge detecting a precharge state in the semiconductor memory means that is equal to or greater than a value; The eleventh transistor and the semiconductor memory are connected when the precharge detection means detects that the semiconductor memory means is in a precharge state. And a current supply means (200) for enhancing a precharge for flowing a current in addition to the current flowing through the eleventh transistor between the first and second transistors. 2. The seventeenth transistor and the nineteenth transistor
The gate of the transistor and the output side of the reference voltage value sending means are connected, and the value of the current flowing through the seventeenth transistor and the nineteenth transistor is compared with the reference current value, whereby the seventeenth transistor and the first
A second precharge detecting means for detecting a precharge state in said dummy semiconductor memory means, wherein a current value flowing through said nine transistors is equal to or greater than said reference current value;
When the output side of the second precharge detecting means is connected and the second precharge detecting means detects that the dummy semiconductor memory means is in a precharge state,
The second precharge enhancing current supply means (400) for flowing a current between the seventeenth transistor and the dummy semiconductor memory means in addition to the current flowing through the seventeenth transistor, further comprising: Sense amplifier. 3. A detecting and amplifying means having a current mirror structure, wherein an input side is connected to an output side of the semiconductor memory means (600), and the detecting and amplifying means having a current mirror structure performs an operation of detecting a current value transmitted by a memory transistor to be detected in the semiconductor memory means. 66
2) having a current mirror structure in which the input side is connected to the output side of the dummy semiconductor memory means simulating the semiconductor memory means and performs an operation of detecting a current value transmitted by the dummy memory transistor in the dummy semiconductor memory means. A control for connecting the dummy detection amplification means (663), the load terminal connected to the input side of the detection output means (11) connected to the output side of the detection amplification means, and the output terminal of the dummy detection amplification means; A load means having a current input terminal and flowing a reference current for determining a current value sent from the detection output means in relation to a current value at the output side of the detection amplification means (664)
And a dummy semiconductor memory means, comprising: a dummy semiconductor memory means having a low on-resistance value; and a low-resistance dummy semiconductor memory means connected to an input side of the dummy detection and amplification means. (653) a high-resistance dummy semiconductor memory means having a dummy semiconductor memory array having a high on-resistance value and connected to the input side of the dummy detection amplifier means in parallel with the output side of the low-resistance dummy semiconductor memory means (656), the input side is connected to the parallel-connected output side of the high-resistance and low-resistance dummy semiconductor memory means, and the input side is connected to the high-resistance and low-resistance dummy semiconductor memory means. A shunting means (661) for generating a current in consideration of a leak current flowing from the resistance dummy semiconductor memory means; ) And is, that sense amplifier according to claim. 4. The current generated by the current dividing means is a current value between a maximum current value and a minimum current value among current values flowing through a memory transistor to be detected selected by the semiconductor memory means. The sense amplifier according to claim 3, wherein the current is: 5. The comparison current generating means forms a current path to ground with a number of series connection stages twice as large as the number of series connection of memory transistors in a current path to ground of a semiconductor memory array included in the semiconductor memory means. The sense amplifier according to claim 3, further comprising a semiconductor memory transistor having a low on-resistance value.