JP3217931B2 - Crosstalk simulation method for design board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention calculates the amount of crosstalk noise of a wiring pattern formed on a printed circuit board,
The present invention relates to a crosstalk simulation method for evaluating a board design.

[0002]

2. Description of the Related Art For example, in the design work of a printed circuit board using an electronic computer, it is necessary to verify crosstalk noise of each part of a wiring pattern formed on the circuit board. That is, when a wiring pattern is designed so as to generate crosstalk noise that is equal to or larger than an assumed allowable value, it is necessary to promptly notify the designer of this and correct it. For this purpose, a crosstalk simulation is performed in which the crosstalk noise of each part of the wiring pattern is actually calculated and totaled. As this method, the following two types of methods are well known.

First, a first method is to check whether the parallel length of a wiring pattern and the pattern gap value are within a certain allowable range. In this method, after the completion of the wiring pattern design, the length of a portion parallel to an adjacent pattern is calculated for all wiring patterns. If the length exceeds the allowable value, it is determined that crosstalk noise of a predetermined level or more is generated, and the pattern is displayed as an error. Further, a gap value between adjacent patterns is calculated, and it is determined whether or not the gap value exceeds a certain allowable value. If it is closer than the allowable value, it is displayed as an error pattern unconditionally.

Another method is an arithmetic processing method using an electromagnetic field simulator. In this case, not only the pattern gap of the actually designed substrate, but also all the main data relating to the physical substrate cross-sectional structure, such as the pattern width, the pattern thickness, the substrate thickness, the resist thickness, etc., are input. Then, electromagnetic field analysis is performed based on these, and self-capacity, self-inductance, mutual capacitance, mutual inductance, and the like are calculated. Thereby, an equivalent four-terminal network is obtained in consideration of the capacitance matrix and the inductance matrix of the wiring pattern to be analyzed. A circuit simulation is performed when this is connected to devices and circuits connected before and after this wiring pattern, and crosstalk noise is obtained from the result.

[0005]

However, the conventional crosstalk simulation method as described above has the following problems to be solved. First, in the method of processing focusing only on the parallel pattern length and the gap value of the pattern,
Since the actual coupling coefficient and device characteristics are not taken into account, there is a problem in the accuracy of the obtained data. In addition, the quality may not be ensured because the amount of noise is not known quantitatively. Conversely, there is also a problem that the safety side is taken too much, resulting in excessive quality, increasing the difficulty of design, and increasing the design period.

On the other hand, the method using the electromagnetic field simulator has an advantage that a simulation can be performed with high accuracy because the result is derived by sufficiently considering the constituent materials and design of the device. However, even when calculating the self-capacitance, self-inductance, mutual capacitance, mutual inductance, and the like of a set of parallel patterns, specifically, several hours of calculation processing time are required. Therefore, a huge amount of time is required to completely perform a crosstalk simulation of each part of a complicated wiring pattern on a printed circuit board. Also, it takes an enormous amount of time to measure parameters of devices connected before and after, and to execute a simulation when combined with circuits and devices connected before and after. Therefore, if such a precise simulation is frequently performed during the board design process, there is a problem that a great deal of man-hours and a design period are required until the board design is completed.

[0007]

The present invention employs the following structure to solve the above problems. The present invention relates to a method of simulating crosstalk noise of a designed board at a workstation including a processor , the method being obtained by calculating for each of a plurality of standard board models having different conductor arrangements or conductor intervals of a wiring pattern. The coupling coefficient table corresponding to the coupling coefficient and the change rate table obtained by tabulating the rate of change obtained from the change of the coupling coefficient due to each structure of the substrate are stored in the storage unit, and are stored by the processor. The coupling coefficient of the standard board model having the wiring pattern similar to the wiring pattern of the design board is determined by referring to the coupling coefficient table of the section, and the processor refers to the change rate table of the storage section to determine the structure of the design board. determining a corresponding rate of change, the more the processor, cross the determined coupling coefficient corrected by the determined change rate talk Determining the effective coupling coefficient of the designed board for calculating the sound,
It is characterized by.

Another invention is a method of simulating crosstalk noise of a designed board at a workstation including a processor , the method comprising a plurality of two parallel line standards having different conductor intervals of a wiring pattern. Calculation for each board model
A coupling coefficient table in which the coupling coefficients obtained by the above are associated with each other , and a change rate table in which a change rate obtained by calculating from a change in the coupling coefficient due to each structure of the substrate is tabulated are stored in the storage unit. The processor stores the coupling coefficient of the two parallel line standard board model having the wiring pattern similar to the wiring pattern of the design board with reference to the coupling coefficient table of the storage unit, and the processor determines the rate of change of the storage unit. Determine the rate of change corresponding to the structure of the design board with reference to the table,
Further , the present invention is characterized in that an effective coupling coefficient of a design board for calculating a crosstalk noise is obtained by correcting the determined coupling coefficient by the determined change rate by a processor .

Each part of the wiring pattern of the design board is approximated by a two parallel line standard board model, and the crosstalk noise voltage is calculated from each effective coupling coefficient obtained by correcting the coupling coefficient of each model, and the sum is calculated. May be used as crosstalk noise induced on the design board. Further, each pair of combinations of the pattern to be analyzed and all the wiring patterns in the vicinity thereof is approximated to the two parallel line standard substrate model, and the crosstalk voltage is calculated from the effective coupling coefficient of each model. The sum can be used as crosstalk noise induced in the pattern to be analyzed. Further, when there are a plurality of parameters attributable to the structure of the substrate, a table may be prepared in which the rate of change of the coupling coefficient is made to correspond to each parameter and referred to.

[0010]

[Action] and the wiring pattern of the analyzed portion serving for example 2 parallel lines standard board model of the wiring pattern of the substrate designed <br/> approximated. The coupling coefficient is obtained from a coupling coefficient table. Then, in order to eliminate the error of the coupling coefficient due to the substrate structure, the coupling coefficient is corrected with reference to the change rate table focusing on the difference in the substrate structure. From the effective coupling coefficient thus obtained, a crosstalk noise voltage based on the two parallel line standard substrate model can be obtained. If the part to be analyzed on the design board is a pattern in which a plurality of models are combined, the sum of the individually obtained crosstalk noise voltages is obtained. If the limit value is exceeded, it is displayed as a design error. Such a simulation can be performed at a sufficiently high speed as compared with the arithmetic processing by the electromagnetic field simulator.

For each standard board model, a precise calculation is performed in advance to obtain a coupling coefficient. The model in that case targets the basic conductor arrangement that frequently appears on the substrate. Since the coupling coefficient is largest for parallel lines,
The use of a two parallel line standard board model is appropriate when considering the safety side of the design. In the case of two parallel lines, the calculation can be simplified and facilitated.

The part to be analyzed may be only a part of the wiring pattern of the design board, or may be, for example, a certain range of the wiring pattern along a specific signal transmission line. When the wiring pattern cannot be approximated by one 2-parallel standard board model when viewed in the longitudinal direction,
Approximate as a combination of two or more models, each crosstalk
The sum of the noise voltages is the crosstalk noise induced on the design board . When attention is paid to a very small part of the wiring pattern, if this may cause crosstalk noise with a plurality of wiring patterns in the vicinity thereof, the superposition of these becomes crosstalk noise.

When there are a plurality of parameters due to the structure of the substrate, if the change rate is tabulated, the coupling coefficient of the two parallel line standard substrate model is corrected in order according to each parameter by the change rate. it can. This enables accurate correction regardless of the number of parameters.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the drawings. [Outline of Simulation] FIG. 1 shows a flowchart of a crosstalk simulation method according to the present invention. In the present invention, as shown in this figure, when a wiring pattern 1 on a substrate 10 is designed, a portion 1A to be analyzed is similar to an assumed standard substrate model.
The two-parallel standard board model is a highly practical model. For such a model, a coupling coefficient calculated in advance using a conductor structure, for example, a conductor interval as a parameter, is calculated in advance, and a coupling coefficient table 4 is generated.

The coupling coefficient obtained by referring to the coupling coefficient table 4 in step S1 in the figure is corrected in step S2. In the case where the coupling coefficient is calculated by focusing only on the conductor spacing, parameters due to various substrate structures such as a substrate material and a substrate thickness are not considered. Thus, for example, the change rate of the coupling coefficient with respect to the base material thickness is determined in advance as the change rate table 6. Of course, such a change rate table is obtained for each other necessary parameter. Then, the coupling coefficient is corrected with the change rate to obtain an effective coupling coefficient. Thereafter, as shown in this flowchart, the calculation of the crosstalk noise voltage using the coupling coefficient is performed (step S3).

When the portion 1A of the design board 10 to be analyzed is composed of a combination of several standard board models, steps S1 to S3 are repeated. Then, by obtaining the sum of the obtained crosstalk noise voltages (step S4), the crosstalk noise of the portion 1A to be analyzed is obtained. In step S5, the crosstalk noise voltage is compared with a certain limit value to determine whether this portion is a design error pattern. If a crosstalk noise exceeding the limit value is generated, an error is displayed in step S6.

The above-described coupling coefficient table 4 and change rate table 6 can be obtained in advance by precise arithmetic processing. Therefore, the actual simulation itself is performed at a very high speed with reference to such a table. In addition, due to the correction of the coupling coefficient or the like, it is performed with sufficient precision as compared with the case where the determination is made only based on the parallel length or the conductor interval. Also,
The calculation processing time can be remarkably reduced as compared with the electromagnetic field simulation. Therefore, at each stage of board design, it can be easily and comparatively frequently used as a simulation for checking whether or not there is an error in the design. If wiring is designed while performing simulations with this level of accuracy, the rate at which errors are found when the calculation is performed precisely with an electromagnetic field simulator or the like at the final stage of design will be sufficiently low, and re-design etc. will be required. Can be prevented.

FIG. 2 is an explanatory diagram of the preliminary processing of the simulation. In carrying out the above-described crosstalk simulation, various table data and the like are prepared in advance by such a procedure. First, two types of standard board models 1 are prepared, for example, as shown in FIG. The one shown on the left side of the figure is the micro trip line 1-1, and the one shown on the right side is the strip line 1-2. The cross-sectional structure of a wiring pattern formed on a substrate is almost represented by these two types.

FIGS. 3 and 4 show the cross-sectional structure details of the microstrip line model and the strip line model. In the microstrip line model, a base material 22 having a thickness H1 is formed on a ground plane 21, and conductors 23 and 24 exposed thereon are arranged at a distance d. In the strip line model, the base material 22 is arranged on the ground plane 21 at a thickness H1, the conductors 23 and 24 are arranged thereon at an interval d, and the base material 26 having a thickness H2 is further arranged.
And the ground plane 25 are overlapped.

Referring back to FIG. 2, the coupling coefficient sampling process 3 is performed on the standard substrate model as described above. In this case, the coupling coefficient analysis 3 using the standard board model
The calculation of the change rate of the coupling coefficient due to the structural change of -1 is performed 3-2. Specifically, as described later, the conductor spacing of the wiring pattern is changed stepwise at an appropriate pitch from 0.254 mm to 2 mm for two parallel lines, and the far-end coupling coefficient and the near-end coupling, respectively. Find the coefficients and make a table.

Here, as the parameters attributable to the structure of the substrate, the relative permittivity of the substrate and the thickness of the base material are employed.
Changes in the coupling coefficient when these are changed stepwise are tabulated as described later. Thus, a coupling coefficient table 4 of the standard substrate model, a change rate table 5 based on the relative dielectric constant, and a change rate table 6 based on the base material thickness are obtained. The crosstalk simulation process is executed with reference to the tables 4, 5, 6, the library 7, and the layout database 8. The layout database is a data base on which the layout of each part is numerically displayed for all the wiring patterns under design, and is the basis of the wiring design. Such data is created by a printed circuit board design tool 9 or the like shown in the figure. Library 7
Stores various other constant data.

[Hardware] In implementing the present invention, for example, hardware as shown in FIG. 5 is used. FIG. 5 is a hardware block diagram for implementing the present invention. As shown, a processor 13 is connected to a network 11 via a transceiver 12. Further, a magnetic disk device 15, a CD-ROM device 16, a display 17, a keyboard 18, a magnetic tape device 19, and the like are connected to the processor 13 via a bus line 14. Such workstations
The simulation process is executed by taking in design data and the like through the network 11 and referring to the layout database 8 stored in the magnetic disk device 15 and the various tables described above.

[Coupling Coefficient Table] FIG. 6 shows a coupling coefficient table of the standard board model. In this example, the microstrip line obtains the far-end coupling coefficient and the near-end coupling coefficient, and the strip line obtains the near-end coupling coefficient for seven types of conductor intervals. This uses a two-dimensional electromagnetic field simulation to obtain a self-resistance R, a self-inductance L, a self-conductance G, a self-capacitance C, a mutual inductance Lm, a mutual capacitance Cm, and a propagation velocity τ per unit length. End coupling coefficient,
The near-end coupling coefficient is obtained by an arithmetic processing. Such a calculation process of the coupling coefficient is performed with a sufficient time in advance, and thus can be obtained with high accuracy.

[Change Rate Table] FIGS. 7 and 8 are explanatory diagrams of the change rate table of the coupling coefficient depending on the substrate thickness and the explanatory views of the change rate table of the coupling coefficient depending on the relative permittivity. The coupling coefficient of the above-mentioned standard substrate model is obtained, for example, when the substrate thickness is 130 micrometers as shown in FIG. When the thickness of the base material changes, the coupling coefficient also changes. In this rate-of-change table, the far-end coupling coefficient and the near-end coupling coefficient when the base material thickness is changed stepwise are calculated, and the ratio to the coupling coefficient of the standard model is displayed on the right side as the rate of change. ing. Thus, the effective coupling coefficient can be obtained by calculating the coupling coefficient of the standard substrate model, and when the base material thickness is different from that of the standard substrate model, by calculating the product of the corresponding change rate and each coupling coefficient.

The rate of change of the relative dielectric constant of the substrate shown in FIG. 8 is the same. When the standard model is the one having the relative dielectric constant of 4.3, as shown in the figure, the relative dielectric constant is changed stepwise. The rate of change in the case where it is dynamically changed is required. In addition, if a change rate table is provided for each parameter of the substrate structure as described above, when a product is multiplied by a corresponding change rate when focusing on a certain parameter, error correction due to the difference between the parameters is immediately performed. Becomes possible. Even if two or more parameters are prepared, it is possible to easily and accurately correct the coupling coefficient by preparing such a change rate table.

[Crosstalk Noise] FIG. 9 is a diagram for explaining the principle of crosstalk noise generation. The evaluation of the crosstalk noise, as shown in FIG.
When a predetermined current flows in a pattern connecting terminals A and B formed adjacent to a pattern formed between * and B *, what kind of pattern is applied to the pattern connecting terminals A * and B * do than crab that noise voltage is generated. It is assumed that a noise power source having a drive amplitude Vs shown in the figure is connected to the pattern connecting the terminals A and B, for example. The length of the pattern being parallel is S. At this time, due to the mutual capacitance Cm and the mutual inductance Lm between these patterns, electrical coupling occurs between the two patterns, and crosstalk noise occurs. That is, as shown in this figure, a current iC flows through the pattern between the terminals A * and B * due to the mutual capacitance Cm. Also, the mutual inductance Lm
Causes the current iL to flow. Note that the currents iC and iL flowing to the near end (drive point) side have the same polarity, and the currents iC and iL flowing to the far end side have opposite polarities.

FIG. 10 is a diagram for explaining a crosstalk noise calculation method. In this figure, the meanings of the characters shown in FIG. 9 and the sign of the data to be obtained from now on are shown in the frame displayed as data. In this data, Vs is the terminal A, B
It is a drive amplitude voltage of a signal of a pattern connecting between them. Also,
The rise time Tr indicates the rise time of the signal. The larger the drive amplitude Vs, the greater the noise, and the shorter the rise time, the greater the rate of crosstalk. Also,
VF is the maximum value of the near-end crosstalk noise, and VB is the maximum value of the far-end crosstalk noise. Since the maximum value of the crosstalk noise obtained by the calculation is substantially the worst value, the value should be adopted as a result in the simulation. Therefore, such a value is set.

As shown in the calculation processing frame of FIG.
In the equation (1), the maximum value VF of the far-end side crosstalk noise is obtained by the product of the far-end coupling coefficient KF, the reciprocal of the rise time Tr of the signal, and the drive amplitude Vs. Also, as shown in equation (2), the propagation velocity τ and the mutual inductance L
m, self inductance L, mutual capacitance Cm,
The far-end coupling coefficient KF is obtained from the self-capacitance C and the like. On the other hand, the maximum value V of the near-end side crosstalk noise
B is obtained by the product of the near-end coupling coefficient KB and the drive amplitude Vs. Then, as in equation (4), the near-end coupling coefficient KB
Is determined by the mutual inductance Lm, the self inductance L, the mutual capacitance Cm, and the self capacitance C.

From the above relationship, the near-end coupling coefficient and the far-end coupling coefficient are obtained by arithmetic processing based on the substrate structure.
A table as described above can be generated. Further, the maximum value of the crosstalk noise can be obtained by using the coupling coefficient and other data. This is used for the crosstalk noise calculation processing.

[Table Interpolation] As described above, the crosstalk noise voltage is calculated with high accuracy by correcting the coupling coefficient of the standard substrate model with the change rate table based on the relative permittivity or the change rate table based on the base material thickness. Can be processed. Although the table is set by changing parameters in a range in which the arithmetic processing can be appropriately and easily performed, a matching value may not be found. In this case, the value of the missing part is calculated by the arithmetic processing. A well-known Lagrange interpolation method or spline interpolation method is suitable for this calculation method.

FIG. 11 is an explanatory diagram of the Lagrange interpolation formula. Lagrange's interpolation is widely used in mathematical tables and the like to find values between tables. For example, given real numbers X0, X1,... Xn and predetermined function values F (X0), F (X1),... F (Xn), the n-th order polynomial passing through n + 1 points is FIG.
1 is represented by Lagrange's interpolation polynomial. Here, Lk in the figure is a Lagrange's interpolation coefficient, which is obtained by the equation in the figure. When the points X0, X1,... Xn are plotted on the coordinates, the intervals may be unequal, and a polynomial that always passes through these points can be obtained even if the number of points is large. The required value is obtained by inserting necessary data into the polynomial.

FIG. 2 is a diagram for explaining Lagrange interpolation calculation. In this figure, coordinates (X, Y) of four points are displayed, and based on the coordinates, four Lagrange interpolation coefficients L0 to L0 are displayed.
L3 is provided. As a result, the Lagrange's interpolation polynomial has the contents shown at the bottom. If an arbitrary X is given to such an interpolation polynomial, the value of P can be obtained. For example, if X is 22.5, P (X) in FIG.
The value is 382686. Thus, even if the coupling coefficient and the change rate are tabulated in a stepwise manner, a smooth curve can be used to interpolate the table to obtain a highly accurate change rate.

As a result, when the portion to be analyzed is approximated by a predetermined standard substrate model, the coupling coefficient is K *
When the rate of change due to the base material thickness and the rate of change due to the relative permittivity are α1 and α2, respectively, the effective coupling coefficient can be immediately obtained from the product of these.

Next, a crosstalk noise voltage is determined using the effective coupling coefficient as described above. First, some patterns that are problematic in terms of crosstalk noise are specified near the pattern to be analyzed. Then, for all these patterns, the pattern length of the parallel portion is calculated from the layout database 8 shown in FIG. Further, the logic amplitude voltage, rise time, fall time, and the like of the driver element of each line are read from the library 7 shown in FIG. Based on these, the far-end crosstalk noise voltage and the near-end crosstalk noise voltage are obtained by the equations (1) and (3) shown in FIG. These are obtained for each of the two parallel line standard board models, and the total sum is obtained. This is the crosstalk noise induced on the line to be analyzed. In addition,
The propagation velocity τ of the signal in the equation (2) can be obtained by the square root of L and C.

[Total Sum of Crosstalk Voltage] FIG.
FIG. 4 is an explanatory diagram illustrating the calculation of the sum of crosstalk voltages. As shown in the figure, for example, assuming that the patterns a, b, and c are adjacent to the pattern to be analyzed connecting the terminals A * and B *, as shown in the figure, Crosstalk noise voltage Vca, Vcb, V
cc occurs. Generally, these noises are not always induced at the same time, but considering the worst case, it is preferable that the value obtained by cumulatively adding them all does not exceed the limit value. Therefore, as described above, the crosstalk noise voltage is individually calculated, and the sum thereof is obtained.

FIG. 14 is a sectional view of a part of the wiring pattern actually analyzed in this manner. By the above processing, as shown in FIG.
The distance d between 3, 24 is 0.254 mm, the substrate thickness H1 of the polyimide substrate 22 is 15 μm,
The effective coupling coefficient when the relative dielectric constant was 3.3 was determined. This arithmetic processing can be performed in an extremely short time as compared with the processing using an electromagnetic field simulator or the like. Even if it is required that the crosstalk simulation of all parts is performed relatively frequently in the course of designing a complicated board, the method of the present invention can sufficiently withstand practical use and shorten the design period.

[Comparison of Specific Effects] FIG. 15 is a diagram (part 1) for explaining the effects of the present invention. This figure is a comparison between two types of practical simulators currently on the market and simulators that carry out the method of the present invention for actually designed wiring patterns having a sectional structure as shown in FIG. is there. The horizontal axis indicates the number of circuits to be analyzed for the wiring pattern. That is, the number indicates how many sets of standard board models are combined for the wiring pattern. The vertical axis indicates the time required for the simulation. The unit is seconds. For example, in the simulator of Comparative Example 2, the number of circuits to be calculated is 20 or less, and the simulation requires 1 hour or more. Also,
Even if a relatively high processing speed simulator is used among commercially available software, the number of circuits is about 150 and the processing time is also required about 1 hour.

On the other hand, in the present invention, the number of circuits is 15
If it is about 0, a simulation result can be obtained in 100 seconds or less. Therefore, it can be seen that the method of the present invention is extremely practical if a simulation of a pattern having a complicated configuration is frequently performed during the pattern design to evaluate the pattern.

FIG. 16 is a view for explaining the effect of the present invention (part 2).
Is shown. FIG. 16A shows a comparison between a measured value of an actually completed circuit and a value obtained by simulation for the near end coupling coefficient and FIG. 16B shows the far end coupling coefficient.
(A) shows the near-end coupling coefficient on the vertical axis, and (b) shows the far-end coupling coefficient on the vertical axis. The horizontal axis indicates the length of the parallel portion of the pattern. The crosses in the figure are the coupling coefficients calculated using the comparative example 1 shown in FIG. In addition, the squares indicate actual measured values, and the triangles indicate coupling coefficients calculated by the method of the present invention. As shown in this figure, in the method of the present invention, the actually measured value and the value of the coupling coefficient agree relatively well, and there is no inferiority to a commercially available simulator in terms of error. Therefore, as shown in FIG. 15, if high-speed arithmetic processing of a complicated circuit is possible, simulation can be performed at any appropriate timing in the pattern design stage, and efficient design work can be supported. Become.

The present invention is not limited to the above embodiment. The standard board model may employ not only a parallel pattern, for example, but also a typical pattern that is frequently used. Therefore, the standard board model has not only the conductor spacing,
An appropriate arrangement of the conductor can be tabulated as a parameter.

[0041]

According to the crosstalk simulation method of the present invention described above , the wiring pattern of the designed board is
Standard board model with wiring patterns corresponding to
By approximating by a joint coefficient and correcting an error caused by the substrate configuration with reference to a change rate table of the joint coefficient, an effective joint coefficient with relatively high accuracy can be calculated in a short time.
Then, the crosstalk is calculated from the effective coupling coefficient thus obtained.
If the noise voltage is calculated or each part of the wiring pattern is approximated by a two-parallel standard board model, and the sum of the results is used as crosstalk noise, precise crosstalk can be obtained for a design board having a wiring pattern with a complicated configuration. Calculation of the noise voltage becomes possible.

When there are a plurality of parameters due to the substrate structure, if the change rate of the coupling coefficient is tabulated for each parameter, the correction of the coupling coefficient can be performed independently using the change rate regardless of the number of parameters. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an embodiment of a crosstalk simulation method according to the present invention.

FIG. 2 is an explanatory diagram of preliminary processing of a simulation.

FIG. 3 is a sectional view of a microstrip line model.

FIG. 4 is a sectional view of a strip line model.

FIG. 5 is a hardware block diagram for implementing the present invention.

FIG. 6 is an explanatory diagram of a coupling coefficient table of a standard board model.

FIG. 7 is an explanatory diagram of a change rate table of a coupling coefficient depending on a base material thickness.

FIG. 8 is an explanatory diagram of a change rate table of a coupling coefficient depending on a relative permittivity.

FIG. 9 is a diagram illustrating the principle of crosstalk noise generation.

FIG. 10 is an explanatory diagram of a crosstalk noise calculation method.

FIG. 11 is an explanatory diagram of a Lagrange interpolation formula.

FIG. 12 is an explanatory diagram of Lagrange interpolation calculation.

FIG. 13 is an explanatory diagram of calculating a total sum of crosstalk voltages.

FIG. 14 is a sectional view of a portion to be analyzed.

FIG. 15 is an explanatory diagram (part 1) of the effect of the present invention.

FIG. 16 is an explanatory diagram (part 2) of the effect of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wiring pattern 1A Part to be analyzed 4 Coupling coefficient table 6 Change rate table S1-S6 Processing steps

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-240567 (JP, A) JP-A-7-182405 (JP, A) JP-A-3-67371 (JP, A) Masao Izumi, "Digital Circuit trends and countermeasures-High-speed circuits-Design examples (features and requests)-", Circuit Technology-Circuits and Implementations, Japan Society of Printed Circuits, June 1993, Vol. 8, no. 4, p. 297-301 (58) Fields surveyed (Int. Cl. ⁷ , DB name) G06F 17/50 666 G06F 17/50 658 JICST file (JOIS)

Claims (2)

(57) [Claims] [Claim 1] crosstalk noise of a substrate on which design professional
A method for simulating at a workstation including a processor, comprising: a coupling coefficient table in which coupling coefficients obtained by calculating for each of a plurality of standard board models having different conductor arrangements or conductor intervals of a wiring pattern are associated; Due to each structure of substrate
Tape change rate obtained by calculation from the change in the coupling coefficient of
The stored change rate table is stored in the storage unit, and the processor refers to the coupling coefficient table in the storage unit to calculate the coupling coefficient of the standard board model having a wiring pattern that is similar to the wiring pattern of the design board. The processor determines the change rate corresponding to the structure of the design board by referring to the change rate table in the storage unit, and further determines the change rate of the determined coupling coefficient by the processor. Calculating an effective coupling coefficient of the design board for calculating the crosstalk noise by correcting the crosstalk noise in the design board. [According to claim 1, wherein the cross-talk noise of a substrate on which design professional
A method of simulating at a workstation including a processor, comprising: a coupling coefficient table in which coupling coefficients obtained by calculating each of a plurality of two parallel line standard board models having different conductor intervals of a wiring pattern are associated; Table of the rate of change obtained from the change of the coupling coefficient caused by each structure of the substrate
The change coefficient table is stored in a storage unit, and the processor refers to the coupling coefficient table in the storage unit and refers to the coupling coefficient table of the storage unit. And the processor determines the change rate corresponding to the structure of the design board by referring to the change rate table in the storage unit, and further, the processor determines the determined coupling coefficient by the determined change. Calculating an effective coupling coefficient of the design board for calculating the crosstalk noise by correcting the crosstalk noise by a correction factor.